Received December 15, 2021, accepted January 13, 2022, date of publication January 18, 2022, date of current

version January 27, 2022.

Digital Object Identifier 10.1109/ACCESS.2022.3144575

Simulation-Assisted Design of a Power Stack for

Improving Static Current Sharing Among Three
IGBT Modules Connected in Parallel
ZHENG-FENG LI 1 , (Student Member, IEEE), NOBUYA NISHIDA 2 , HIROTOSHI AOKI3 ,
HISASHI SHIBATA3 , CHIH-CHIA LIAO 1 , AND MING-SHI HUANG 1 , (Member, IEEE)
1 Department of Electrical Engineering, National Taipei University of Technology, Taipei 106, Taiwan
2 Mitsubishi Electric Corporation, Fukuoka 810-8686, Japan
3 TAMURA Corporation, Saitama 350-0214, Japan
Corresponding author: Zheng-Feng Li (u94102@gmail.com)
This work was supported by TAMURA Corporation under Grant 208Q12.

ABSTRACT In this study, cosimulation with Q3D and Simplorer were adopted to design a single-phase
power stack with equal output current on three paralleled IGBT modules in high power application, therefore,
the derating of total current will be reduced, which can improve the current utilization and power density
of power stack. The performance of the designed stack was verified using a double-pulse test (DPT). The
circuit used in the DPT regarded the power stack output current as static current, which is a critical index to
evaluate current sharing. The static current sharing among the IGBT modules was mainly dependent on the
stray inductance of the DC busbar, IGBT modules, and phase output bar (POB), which is used to connect
the IGBT modules to load, in parallel paths of the power stack. Cosimulation was performed to determine the
stray inductance of the IGBT modules, DC busbar and POB, and a constant-current-slope method was used
to verify the inductance. Subsequently, design the shapes of DC busbar and POB for attaining maximum
ratio of imbalanced current (MRIC) of the three IGBT modules is within 3% under 200% (2400A) rated
current. The cosimulation results indicated that the MRIC of the current paths in power stack were 0.8%.
Finally, three IGBT modules and a gate driver were used to construct power stack with 1000V DC link.
The experimental results obtained by DPT indicated that the MRIC was 0.9% under 200% rated current,
demonstrating the effectiveness of the proposed stray inductance design method.

INDEX TERMS IGBT module, power stack, cosimulation, current sharing, paralleled operation.

I. INTRODUCTION current to each IGBT [9]. The authors of [10] demonstrated

Insulated-gate bipolar transistors (IGBTs) are widely used that the derating of total current must be conducted by consid-
in medium-voltage, high-voltage, and high-power systems ering the current imbalance of IGBTs connected in parallel.
because of their high current rating, high withstand voltage, They derived a formula that indicates that the derating of total
and low loss. A half-bridge module with two IGBTs con- current is 17.4% under an imbalance current ratio of 15% for
nected in series is typically used as a basic unit in converter or three IGBTs connected in parallel.
motor drive applications for the convenience of these appli- To reduce cost and stock, the inverter used in wind gen-
cations [1], [2]. Therefore, a converter or an inverter is com- eration applications usually contains multiple IGBT modules
posed of low- or medium-voltage IGBT modules connected connected in parallel for constructing a single-phase power
in series [3], [4] or parallel to increase the output power [5], stack. A three-phase inverter is formed using three power
which reduces the cost of wind turbine [6], traction driver [7], stacks [11], [12]. According to the current change rate, the
and ventilation [8] applications. Although IGBTs connected current of a power stack with IGBTs connected in parallel can
in parallel can effectively increase the output current, the be divided into static current and dynamic current, which have
power circuit should be designed such that it provides equal low and high change rates, respectively. Fig. 1(a) displays the
dynamic and static current flow paths of a power stack with
The associate editor coordinating the review of this manuscript and IGBT modules connected in parallel in a double-pulse test
approving it for publication was Ramani Kannan . (DPT) method. The relationship between the IGBT module

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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current and the DPT pattern is shown in Fig. 1(b). The static preselected and the parallel modules should be connected to
current provides the required load current when the low-side the same heatsink to achieve superior current balancing [19].
IGBT is turned on, and dynamic current occurs at the turn-
on and turn-off transients of the low-side IGBT. The main TABLE 1. Studies on current balancing in IGBTs connected in parallel.
difference between the static and dynamic current flow paths
is that static current flows through the load inductor to the
POB, whereas dynamic current flows through the parasitic
diode of the high-side IGBT and the Coss of the low-side
IGBTs. Because of the low switching frequency of IGBTs in
high-power applications, the power stack loss is dominated
by static current [13] when compared with short turn-on and
turn-off transient times.

Moreover, the DC+ and DC− terminals of IGBT modules

connected in parallel should be adjacent to each other on the
same side [20], [21] for reducing the stray inductance differ-
ence between the DC busbar and each IGBT module. In addi-
tion to IGBT modules, the gate driver circuit can effectively
improve current sharing. In [19] and [22], active gate voltage
control with online IGBT current detection was implemented
to achieve superior static current sharing. Because of the
requirement of real-time control during the IGBT turn-on
period, most circuits are constructed using complex FPGAs,
DSPs, and high-bandwidth current sensors [23]. However,
such circuits cannot drive parallel IGBT modules by using
a single-gate driver. In [24], [25] chokes were added to the
phase outputs of IGBT modules connected in parallel to
achieve balanced current distribution.
Studies [24], [26] have indicated that a gate driver with
a common mode choke can achieve balanced static current
distribution. A study [14] used a slotted DC busbar to improve
dynamic current sharing; however, the optimal method for
balancing static current remains unclear because the DC
busbar incorporates a small percentage of stray inductance
FIGURE 1. Schematic of the power stack used in the DPT: (a) circuit;
into the static current path. Moreover, the POB of the power
(b) definitions of the static and dynamic current. stack is used to not only connect the IGBT modules [26]–[28]
but also achieve static current balancing for IGBT modules.
To ensure static current balancing, some studies [27], [28]
Table 1. summarizes recent studies on current balancing have employed the same individual stray inductance from
for IGBTs connected in parallel. The factors affecting cur- each IGBT module to load terminal in the POB. However, the
rent distribution are as follows [14], [15]: characteristics of studies cited in the aforementioned text have not described the
IGBTs, the gate driver circuit, the DC busbar, and the POB. POB design method and have not mentioned why the stray
Turn-on saturation voltage, stray resistance, and inductance inductance of each IGBT path in the POB must be similar
of IGBTs, and the temperature difference among IGBT mod for achieving static current balancing. IGBT modules are
ules connected in parallel may affect the current sharing included in the static current flow path depicted in Fig. 1(a);
[14]–[18]; therefore, the same die production batch should be however, limited research has been conducted on the

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influence of the stray inductance of these modules on static current balancing of IGBT modules connected in parallel.
current balancing. Furthermore, the DPT [22], [29] is gener- Design results indicated that the POB is the main part to be
ally used to test the current balancing of IGBT modules con- modified for ensuring that the stray inductances are the same.
nected in parallel. Studies [9], [14], [17], [30] have indicated
that the wiring from the load inductor to the POB in the DPT TABLE 2. Electrical specifications of proposed power stack.
setup affects output current balancing.
The aforementioned discussion indicates that appropri-
ately designing the DC busbar and POB is important.
The traditional design method for DC busbars is based on
Maxwell’s equations for calculating the trend of stray induc-
tance [31], [32]. For complex-shaped POBs and DC busbars,
Ansys Q3D or Maxwell 3D has been used for the quantitative
analysis of the stray inductance [33]–[36]. The measure-
ment of stray inductance inside the IGBT module is crucial.
Studies [18] have only described the measurement of the
internal resistance of IGBT modules but have not described
the measurement of the stray inductance.
In this study, a single-phase power stack containing three
half-bridge IGBT modules connected in parallel was con-
structed for achieving static current balancing. To design a
laminated DC busbar and POB, the Q3D simulation soft-
ware was adopted for analyzing the stray inductance of the
IGBT modules. Moreover, the Simplorer software was used
with Q3D to ensure that the stray inductances in the three
static current paths of the IGBT modules were nearly the
same for achieving static current balancing. The current bal-
ancing of the three IGBT modules was analyzed through
cosimulations, and the suitability of the design was verified
through careful measurements. Finally, a single-phase power
stack with a DC link voltage of 1000V was constructed
according to the specifications presented in Table 2. to verify
the effectiveness of the design. The designed power stack FIGURE 2. Exploded view of the proposed power stack.

contains a DC link capacitor tank with nine film capaci-

tors (50.R19-764NT1, ELECTRONICON); three half-bridge
IGBT modules (Mitsubishi Electric CM1200DW-34T) with
1200A rated current connected in parallel; a single-gate driver
(Tamura, 2DUC51008CML1), which is used to drive the
IGBT modules; a carefully designed DC busbar; and a care-
fully designed POB. The results by the DPT method indicated
that the maximal current difference among the three IGBT
modules was 38A at 200% rated current per IGBT module.
Moreover, the maximum ratio of imbalanced current (MRIC)
was 0.9% under a 200% (2400A) rated current of an IGBT
module. The aforementioned results indicate the effective-
ness of the proposed stray inductance design method.

II. DESIGN OF THE POWER STACK

The proposed power stack comprises a DC busbar, DC link
capacitors, IGBTs, a gate driver, a heat sink, a POB, and a FIGURE 3. Equivalent circuit of current flow paths for the proposed
ferromagnetic-metal housing. The exploded view of this stack power stack in the DPT.
is presented in Fig. 2. Because limited energy is required by
the designed power stack in the DPT method, the DC link The design procedure for the proposed power stack is
capacitors are regarded as ideal voltage sources, with each displayed in Fig. 4. First, IGBT module, gate driver and DC
capacitor providing the same current for testing in the DPT. link capacitors are selected according to requirements. Sub-
Therefore, the stray inductances from the DC busbar, IGBTs, sequently, Q3D is employed to analyze the stray inductance
and POB (Fig. 3) are major factors influencing the static of the IGBT modules as a design basis for the laminated

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DC busbar and POB. Moreover, the DC busbar and POB are Table 2 in (1). The DC link capacitor for a single stack Cstack
designed and analyzed through cosimulation with Simplorer is one-third that for the inverter (i.e., Cstack is 6956µF). Film
and Q3D to obtain nearly the same stray inductance for the capacitors have been widely adopted in power stacks used
three current paths from the DC link capacitors to the phase in wind power generation because of their favorable perfor-
output terminal. If the MRICs for the three IGBT modules is mance at low temperatures, safety and robustness [34]. There-
within 3% under 200% rated current, then the designed power fore, the ELECTRONICON E50.R19-764NT1 film capacitor
stack is constructed for performance verification; otherwise, was adopted in this study. The total capacitance of a single
the POB is redesigned. stack Cstack comprising nine film capacitors with a rated
voltage of 1300V each and a capacitance of 760µF each
that are connected in parallel is 6840µF under an operating
temperature range of −40◦ C∼85◦ C.

B. GATE DRIVER
The adopted gate driver (Tamura 2DUC51008CML1), which
contains an in-built isolated DC–DC converter and performs
soft turn-off and desaturation, is used to drive the three IGBT
modules (Fig. 5). The gate driver serves as a master and
connects two expansion slave boards with similar matching
impedances to drive the three IGBT modules simultaneously,
the gate resistance Rg is 0.6, turn on and off gate to emitter
voltage are 15V (Vge_on ) and −9.6V (Vge_off ), respectively.

FIGURE 4. Design procedure for the proposed power stack.

A. SELECTION OF THE DC LINK CAPACITORS

Front-end AC–DC rectifier with a capacitor tank is widely
used in high-power applications to provide the DC voltage
required by multiple power stacks. This study analyzed the
current sharing among IGBT modules connected in parallel.
The selection of DC link capacitors was based only on the
specifications presented in Table 2. and the power require-
FIGURE 5. Connection of the adopted gate driver to the three IGBT
ment of the load [37], [38]. Moreover, the designed power modules connected in parallel.
stack was constructed to test its current balancing by the DPT
method. Through the use of the aforementioned selection
procedure, the capacitance of the DC link capacitors should C. DETERMINATION OF THE STRAY INDUCTANCE FROM
be sufficient for the DPT method. The DC link voltage of THE IGBT MODULES
an inverter is usually 1000–1100V in applications with a The stray inductances of the IGBT modules were extracted
grid voltage of 690Vrms [39]–[41]. Therefore, the required using Q3D, which adopts the simplified flat copper bonding
capacitance of DC link capacitors for an inverter with three model of the IGBT module of Mitsubishi Electric that is
power stacks can be expressed as follows: displayed in Fig. 6. Moreover, the stray inductances belong
2×Q to the dynamic and static current paths, which are shown in
C =  
2 2
VDC(max.) − VDC(min.) ×f Fig. 7(a) and 7(b), respectively. The stray inductances in an
IGBT module can be expressed as follows:
2 × P × tan(θ)
=   (1)
2
VDC(max.) 2
− VDC(min.) ×f Lσ _S = Lo + L3 + L4 (2)
Lσ _D = L1 + L2 + L3 + L4 − 2M (3)
where
VDC(max.) : maximal DC link voltage where
VDC(min.) : minimal DC link voltage Lσ _S and Lσ _D : total stray inductances of the static and
Q: rated reactive power dynamic current paths in the IGBT module, respectively.
f : line frequency of the grid Lo : stray inductance between the phase terminal and the
P: rated active power IGBT die.
The capacitance of the DC link capacitors was calculated L1 and L2 : stray inductances from DC+ to the die and from
to be 20869µF by substituting the parameters presented in the die to the Lo of the high-side IGBT die, respectively.

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L3 and L4 : stray inductances from Lo to the die and from and Lσ _S were 12.5nH and 30.3nH, respectively, under a fre-
the die to the DC− of the low-side IGBT die, respectively. quency of 1.25kHz. The frequency of 1.25kHz represents the
M : mutual inductance between (L1 , L2 ) and (L3 , L4 ) under fundamental operating frequency of the first test pulse in the
the assumption that the bonding wire is symmetrical in the DPT Fig. 1(b). Moreover, the simulated parasitic resistance
high- and low-side IGBTs in the IGBT module. Rσ _S of static current path was 0.14m.
Because the Spice model could not be applied to
the adopted IGBT modules, the simplified IGBT circuit
[Fig. 9(a)] was used to simulate the static current sharing
among the IGBT modules for improving the design of the
POB. The approximate turn-on saturation voltage of the low-
side IGBT VCE(sat.) [18] is expressed as follows:

VCE(sat.) = VCE(0) + IC × RX (4)

where VCE(0) and RX are the turn-on initial voltage and equiv-
FIGURE 6. Adopted IGBT module (Mitsubishi CM1200DW-34T) and its alent resistance of the low-side IGBT die used in the IGBT
simplified flat copper bonding model.
module, respectively. As shown in the die level output curve
depicted in Fig. 9(b), RX was calculated to be 0.75m under
VCE(0) = 1.05V, iC = 200A and iC = 1000A. Because
Rσ _S (=0.14m) is considerably smaller than RX , the effect
of Rσ _S can be disregarded in the further analysis.

FIGURE 8. Simulated stray inductances and parasitic resistance inside the

IGBT module (CM1200DW-34T).

D. DC BUSBAR DESIGN
Because of the usage of a high-voltage film capacitor and the
need for cost reduction, a double-layer laminated busbar was
selected for the designed power stack. To reduce the stray
inductance of the DC busbar, the overlap area of the two
layers should be as high as possible and the gap between the
two layers [42] should be as low as possible under the consid-
eration of safety regulations. The symmetrical connection of
FIGURE 7. Equivalent circuit, approximate wire bonding and
static/dynamic current path of the IGBT module (CM1200DW-34T):
capacitors to the DC busbar can reduce the current imbalance
(a) dynamic path; (b) static path. [34], [43] among them. Moreover, the connections between
capacitors and the DC busbar should have rounded edges for
Fig. 8 displays the simulated results obtained using Q3D reducing the eddy current loss [34]. Fig. 10(a) depicts the
for the stray inductance. A dynamic path enables magnetic shape and dimension of the designed DC busbar. The current
flux canceling because of the wire-bonding structure; there- flow starts from the positive terminals of the capacitors,
fore, Lσ _D is smaller than Lσ _S . The simulated values of Lσ _D passes through the positive layer to the load inductor, and

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from 0 to 2400A in 80µs for each current path. These currents

were used for determining the stray inductances. The stray
inductances of the three parallel paths in the DC busbar are
expressed as follows:
     
v1 Lb11 Lb12 Lb13 i1
 v2  =  Lb21 Lb22 Lb23  d  i2  (5)
v L L L dt i
3 b31 b32 b33 3

where
v1 , v2 and v3 : induced voltages.
i1 , i2 and i3 : injected currents.
Lb11 , Lb22 and Lb33 : self-inductance.
Lb12 , Lb13 , Lb21 , Lb23 , Lb31 and Lb32 : mutual inductance
If equal injected currents are assumed along the three paths,
then i1 = i2 = i3 = i. In this case, (5) can be simplified as
follows:
   
v1 Lb1
 v2  =  Lb2  d [i] (6)
v L dt
3 b3

where is the equivalent stray inductance in the DC busbar and

is expressed as Lbx = Lbx1 + Lbx2 + Lbx3 , x = 1, 2, 3.

FIGURE 9. (a) Equivalent circuit of the low-side IGBT in the turn-on

period of the DPT; (b) die level output curve of the IGBT [21].

moves from the POB to the negative layer through the neg-
ative terminal of the IGBT modules; finally, it returns to the
negative terminals of the capacitors. Therefore, the magnetic
field coupling effect occurs. This effect is induced by the
current that flows between capacitors and IGBT modules.
Consequently, the following assumptions were made in the
adopted stray inductance simulation method [Fig. 10(b)]:
1) The DC link capacitors are ideal.
2) The DC busbar can provide balanced current to the FIGURE 10. Proposed DC busbar and its stray inductance measurement
setup: (a) shape and dimension; (b) measurement setup under
three IGBT modules. simulation.
3) The connection between the capacitor and the DC bus-
bar can be regarded as a short circuit. Fig. 11 depicts the simulated waveforms and results of the
On the basis of the aforementioned assumptions, the DC DC busbar. The simulated values of Lb1 , Lb2 and Lb3 were
link capacitors can be regarded as ideal voltage sources, with 22nH, 19nH, and 22nH, respectively. The parameter Lb2 is
each capacitor providing the same current. Therefore, the smaller than Lb1 and Lb3 because of the DC busbar struc-
terminals of these capacitors can be set as short circuits during ture and location of load inductor. The maximum difference
the simulation. In the cosimulation conducted with Simplorer among the stray inductances was only 3nH, which indicates
and Q3D, the ideal current with a fixed slope increased that the DC busbar design and proposed stray inductance

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simulation method were effective for achieving near-equal

stray inductances among the three current flow paths.

FIGURE 11. Simulated stray inductance values of the DC busbar.

FIGURE 12. POB structure: (a) traditional POB; (b) proposed POB.
E. POB DESIGN
A T-type POB, which is an improvement over the traditional
POB, was designed using Q3D to connect and enable sat- 3
P
isfactory current sharing among the three IGBT modules. LPOBC,k
Fig. 12 presents the structures of the traditional and pro- k=1
LPOBC(Avg.) = (8)
posed POB. According to the current flow, the aforemen- 3
tioned POBs can be divided into two parts: the convergence where LPOBC,1 , LPOBC,2 and LPOBC,3 are the equivalent stray
and common parts. The convergence part is used to merge inductances of the proposed convergence part along three
the three IGBT module currents. In Fig. 12, the red, blue, paths.
and green paths correspond to the current paths of IGBT 1,
IGBT 2, and IGBT 3, respectively. Because the blue path
(IGBT 2) of the traditional POB is the shortest path to the
load inductor in Fig. 12(a), this path has the lowest stray
inductance. This finding is in line with the results of the DC
busbar simulation. The proposed POB [Fig. 12(b)] contains
a polygonal hollow part for adjusting its stray inductances.
Moreover, it compensates for the stray inductance of path 2
(blue path) of the DC busbar. The common part of the afore-
mentioned two POBs is used for conducting current with the
same stray inductance; therefore, this part has no influence
on the current balancing and can be regarded as part of the
load inductor. Consequently, the polygonal hollow part is the
only part that affects the current balancing.
FIGURE 13. Design procedure for the proposed POB structure.
The design procedure for the proposed POB (Fig. 13) is
described as follows:
Fig. 14 displays the simulated results for the relationship
1) STEP1: DESIGN THE SIZE OF THE POB among the length (L), width (W), and MRID of the conver-
gence part. The MRID can be minimized by adjusting the
Because the stray inductances are varied by changing the
hollow dimensions under the assumption that the inductances
hollow area, the convergence part of the proposed POB is
of paths 1 and 3 in the convergence part are nearly the
larger than that of the traditional POB.
same because of the symmetrical structure of this part. The
simulation results indicated that the smallest MRID is less
2) STEP2: DETERMINE THE LENGTH (L) AND WIDTH (W)
than 2% in the area where L is greater than 140mm and W is
The maximum ratio of inductance difference (MRID) and
approximately 10-15mm. Because the shape of the POB can
average inductance LPOBC(Avg.) of the convergence part can
be easily adjusted for obtaining the required stray inductances
be defined as follows:
which compared with 20nH average value of the DC busbar,
LPOBC,1 − LPOBC,2 the stray inductance of the convergence part dominates the
MRID(%) = × 100 (7)
LPOBC(Avg.) adjustment of all the stray inductances.

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FIGURE 14. Relationship between the hollow dimensions (L and W) and

MRID of the proposed convergence part.

Fig. 15 displays the simulated stray inductances of the

convergence part for the L and W values presented in Fig. 13.
The stray inductances of the three paths are nearly 30nH
which are larger than those of DC busbar when L = 140mm
and W = 15mm. Although the stray inductances can be
increased by enlarging the hollow area of the convergence
part, the voltage drop induced by the path impedance under a
large current must be considered in the design of the POB.

TABLE 3. Simulated stray inductance of the convergence parts of the

traditional and proposed POBs.

FIGURE 15. Simulated inductance of the convergence part: (a) W = 15mm

and L from 0mm to 180mm; (b) L = 140mm and W from 0mm to 20mm.

3) STEP3: FINE-TURN THE PROPOSED POB higher than those along paths 1 and 3 for compensating for
the stray inductance in the DC busbar.
To compensate for the low stray inductance along current
path 2 of the DC busbar, the rectangular area A in Fig. 13 is
removed. In addition, the triangular area B is removed to III. COSIMULATION OF THE STATIC IMBALANCED
reduce the weight of the POB without affecting the required CURRENT OF THE DESIGNED POWER STACK
stray inductance. For further analyzing the current balancing, cosimulation
The stray inductances simulated method of the POB and was conducted using Simplorer and Q3D to predict the cur-
DC busbar was similar (Fig. 16). The current sources exhib- rent distribution among the IGBT modules and examine the
ited a constant-current-slope of 2400A/80µs for testing the validity of the aforementioned stray inductance and current
convergence part and entire POB. The simulation results of balancing estimations. Fig. 17 shows the cosimulation setup
the traditional and proposed POBs are presented in Table 3, of the power stack in the DPT. The parameters and settings
which indicates that the stray inductances of the proposed of the cosimulation environment are listed as follows:
convergence part are closer and larger than those of the tradi- 1) The DC source voltage VDC was 1000V.
tional POB. The simulated stray inductances of the common 2) The nine film capacitors had the same electric parame-
parts of the proposed and traditional POBs were near 106nH ters, and these capacitors, including their ESR and ESL,
and 102nH, respectively. Moreover, the stray inductance of were connected one-by-one to the nine connectors of
the proposed convergence part along path 2 was marginally the DC busbar that was constructed using Q3D.

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IGBT having a rated current of 1200A. The required

load inductance was calculated to be 9.5µH by con-
sidering a VDC of 1000V, which was also assumed
to be the voltage drop of the resistance; a maximal
current of 7200A; and the signal sequence of gate
driver. Moreover, the inductive load was replaced by
a RL series circuit in the cosimulation to neglect the
magnetic coupling effect induced by the load inductor.
7) Cosimulation was conducted using Simplorer and Q3D
to consider the proximity effect caused by various cur-
rents along each path of the POB.
Fig. 18 displays the simulated current sharing results for
the designed power stack in the traditional and proposed
POBs. The inferences drawn from the simulation results are
as follows:
1) Because path 2 of the traditional POB exhibited the
lowest stray inductance (Table. 3), the peak current of
this path (ipeak ,2 ) was larger than those of the other two
paths (ipeak ,1 and ipeak ,3 ), which were equal.
2) Similarly, ipeak ,2 was smaller than the other two peak
currents because path 2 had highest stray inductance,
with ipeak ,1 being equal to ipeak ,3 for the proposed
POB.

FIGURE 16. Stray inductance measurement setup for the POB in the
cosimulation: (a) convergence part; (b) entire POB.

3) Because the Spice model of the IGBT modules was

not available, the high-side IGBT was assumed to be
always off and the low-side IGBT was assumed to be
driven by an ideal gate driver in the DPT. Moreover,
the relationship between the turn-on voltage VCE(sat.)
of the low-side IGBT and the current was determined
using (4) to simulate the behavior of this IGBT.
4) The simulated results of two types of POBs, namely the FIGURE 17. Cosimulation setup of the designed power stack in the DPT:
traditional and proposed POBs, were compared. (a) function block; (b) implementation of the power stack simulation
model in Simplorer.
5) The output signal of the gate driver was ideal, and the
signal sequence comprised two on--off cycles with on The MRIC can be defined as follows:
and off periods of 40µs each. 3
6) The maximal current of the IGBT modules in the DPT
P
ipeak,k
was 200% rated current; thus, the total output current ipeak(Avg.) =
k=1
(9)
was 7200A for the three IGBT modules, with each 3

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reducing the influence of traditional POB. Thus, the

stray inductances of the IGBT modules have an impor-
tant influence on static current balancing.

FIGURE 19. Cosimulation results of current sharing in the power stack in

the proposed POB when only considering the convergence part.
(VDC : 1000V, load inductor: 9.5µH, drive signal: ideal PWM, IGBT
module: CM1200DW-34T).

FIGURE 18. Cosimulation results for current sharing in the power stack:
(a) traditional POB and (b) proposed POB. (VDC : 1000V, load inductor:
9.5µH, drive signal: ideal PWM, IGBT module: CM1200DW-34T).

ipeak,k − ipeak(Avg.)
MRIC(%) = Max. × 100 (10)
ipeak(Avg.)
where ipeak,k is the peak current of the IGBT module along
path k and ipeak(Avg.) is average peak current of the three
IGBTs. The MRIC of the traditional and proposed POBs
were 5.9% and 0.8%, respectively, and the and maximal
current difference (MCD) of these POBs were 216 and 30A,
respectively. These results indicate that the proposed POB
enabled better current sharing among the IGBT modules than
did the traditional POB.
Fig. 19 shows the cosimulation results of current sharing in
the power stack in the proposed POB when only considering
the convergence part. The three path currents displayed in
Fig. 19 are close to those depicted in Fig. 18(b), which
indicates that the common part of the POBs had no influence
on current sharing. Fig. 20 depicts the stray inductance dis-
tribution presented in Table 4. Table 4 summarizes the stray
inductances of the DC busbar, IGBT modules, and conver-
gence part of the POB along the three static current flow paths
in the designed power stack. The following phenomena can
be observed from Table 4:
1) The proposed POB (Design 2) exhibited almost iden-
tical stray inductances along the three current paths. FIGURE 20. Stray inductance distribution of the power stack: (a) the
traditional POB; (b) the proposed POB.
Thus, current balancing occurred among the three
IGBT modules.
2) Although the stray inductances of the traditional POB IV. EXPERIMENTAL RESULTS
varied considerably, the stray inductances of the IGBT Fig. 21 illustrates the proposed power stack and its setup
modules represented nearly 50% of the total, thus in the DPT. The dimensions of the power stack are

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Z.-F. Li et al.: Simulation-Assisted Design of Power Stack for Improving Static Current

TABLE 4. Stray inductances (nH) of two type of power stack designs. depicted in Fig. 9. Therefore, the lower-arm voltage of the
IGBT modules in the DPT is expressed as follows:
diC(t)
VCE(module) − VCE(sat.) = Lσ _S + iC(t) × Rσ _S (11)
dt
To increase the measurement accuracy and considered volt-
age drop, a DC link voltage of 30V and load inductance
of 0.68µH were selected for achieving a constant-current-
slope (i.e., dic(t) /dt = 35.1A/µs) during calculation period
5.7µs as shown in Fig. 22. The achieved current slope was
equivalent to that of a 1000V DC link voltage with a 9.5µH
680 × 425 × 230mm3 . The experimental conditions were
inductor. Therefore, a voltage probe with a 10:1 attenuation
the same as the simulation conditions. The Lecroy HRO 64Zi
was adopted to measure the IGBT voltage VCE(module) . This
and Rohde & Schwarz RTE1054 digital oscilloscopes and
probe provides a higher accuracy than does that with an
PEM CWT Mini HF30B 6kA current probes were used for
attenuation of 100:1. The measured waveforms of the low-
measurements. The gating signal of the DPT was generated
side IGBT voltage VCE(module) and current ic are illustrated in
using a DSP-based (TMS320F28075) control board, and the
Fig. 22. The VCE(sat.) values were 1.2V and 1.35V at 200A
constant-current-slope of load inductor obtained in the DPT
and 400A calculated from Fig. 9(b), respectively. Moreover,
had to be the same as that depicted in Fig. 18 for comparing
the stray inductance Lσ _S was calculated to be 36.5nH, which
the simulation and experimental results.
was larger than the simulated Lσ _S value obtained using Q3D
(Lσ _S ∼= 30.3nH) possibly because the IGBT module of
Mitsubishi Electric is simplistic. In this module, flat copper
is used to connect dies and terminals instead of a multiple
wire-bonding model. The stray inductance for flat bonding is
smaller than that for wire bonding.

FIGURE 22. Measured waveforms of the voltage VCE (module) and current
ic of the lower-side IGBT. (VDC : 30V, load inductor: 0.68µH, Rg : 0.6,
Vge_on : 15V, Vge_off : −9.6V, temperature: 25◦ C, IGBT module:
CM1200DW-34T).

B. VERIFICATION OF POB INDUCTANCE

The verification method for the stray inductances in the
POB is similar to the inductance extraction in (6). However,
in contrast to the simulation, the manufactured POB is an
integrated structure and cannot be separated into the conver-
gence and common parts in practice. Therefore, the measured
waveforms of the entire POB (Fig. 23) and the measurement
FIGURE 21. Measurement setup and proposed power stack: (a) test setup are the same as those depicted in Fig. 16(b). To reduce
bench and (b) power stack. the influence of resistances in the POB and measured error
caused by high current, the DC voltage is set as 300V to let the
A. VERIFICATION OF IGBT MODULE INDUCTANCE peak current be less than 400A in each current path. The mea-
The test circuit was based on the DPT, and the measurements sured and simulated stray inductances are listed in Table 5.
were based on the equivalent circuits of the IGBT modules The maximal error between the simulation and experimental

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 Z.-F. Li et al.: Simulation-Assisted Design of Power Stack for Improving Static Current

results is less than 3.1%, which indicates a satisfactory match Fig. 18, which are also good match with experimental
between the cosimulation and measurement results. results. Possibly because the proximity effect on the
three IGBT modules was considered in the experiment,
which resulted in an increase in the impedance of
IGBT 2 for reducing the current along path 2.

TABLE 6. Comparison between the simulation and experimental results

for the three IGBT modules.

FIGURE 23. Measured stray inductance measurements for the proposed

POB. (VDC : 300V, load inductor: 9.5µH, Rg : 0.6, Vge_on : 15V, Vge_off :
−9.6V, temperature: 25◦ C, IGBT module: CM1200DW-34T).

TABLE 5. Simulation and experimental results for the stray inductance of

the proposed POB.

Sim. − Exp.
Error(%) =
Exp.
The parameters LPOBE,1 , LPOBE,2 and LPOBE,3 denote the
entire stray inductances of the proposed POB along paths 1,
2, and 3, respectively.

C. CURRENT SHARING TEST OF SINGLE POWER STACK

Table 6 and Fig. 24 present the experimental results for the
three IGBT modules and a comparison between the simula-
tion and experimental results of these modules, respectively.
The following inferences can be drawn from the results pre-
FIGURE 24. Measured current sharing of the power stack in different
sented in Table 6: POBs: (a) the traditional POB; (b) the proposed POB. (VDC : 1000V, load
1) The simulated and experimental MRIC and MCD inductor: 9.5µH, Rg : 0.6, Vge_on : 15V, Vge_off : −9.6V, temperature: 25◦ C,
of the proposed POB were smaller than those of IGBT module: CM1200DW-34T).

the traditional POB. Moreover, the proposed POB

met the design criterion of the MRIC being less Notably, the method of wiring the load inductor in the DPT
than 3%. The simulated and experimental MRIC val- affects the test results. Fig. 25(a) indicates that the imbalance
ues of the proposed POB were 0.8% and 0.9%, currents of the IGBTs increased when the wiring of the load
respectively. In the experiment, the MCD decreased inductor was parallel to the POB. Therefore, the wiring of
from 161 to 38A when the traditional POB was the load inductor must be perpendicular to the POB and DC
replaced with the proposed POB. Such a decrease in the busbar during the DPT, as depicted in Fig. 25(b), to reduce
MCD can reduce the derating current of the three IGBT the effect of electromagnetic coupling on current sharing.
modules. In order to keep the maximum current less than 2400A in each
2) The proposed design method of POB can improve IGBT module under serious EM coupling condition, VDC is
current sharing from simulation results as shown in adjusted to 800V.

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Z.-F. Li et al.: Simulation-Assisted Design of Power Stack for Improving Static Current

3) A design procedure is proposed for achieving suit-

able current sharing among IGBT modules connected
in parallel. The DC busbar and POB were designed
through cosimulation with Simplorer and Q3D to
enable each stray inductance along the three static cur-
rent paths to be nearly equal for achieving static current
balancing. The stray inductances could be varied effec-
tively by changing the shape of the hollow part in the
proposed POB. The proposed POB exhibited almost
identical stray inductance along the three current paths
in the simulation.
4) The simulated and experimental MRIC and MCD of
the power stack with proposed POB were smaller than
those of traditional POB. Moreover, the proposed POB
met the design criterion of the MRIC being less than
3%. The simulated and experimental MRIC values of
the proposed POB were 0.8% and 0.9%, respectively.
In the experiment, the MCD decreased from 161A
to 38A when the traditional POB was replaced with
the proposed POB. The almost-equal stray inductances
along the three static current flow paths in the pro-
posed POB enabled satisfactory current balancing to be
achieved among the three IGBT modules.

FIGURE 25. Influence of the method of wiring the load inductor on the
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degrees in electrical engineering from Kumamoto
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University, Japan, in 1997 and 1999, respectively.
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HIROTOSHI AOKI received the B.S. degree from CHIH-CHIA LIAO received the B.S., M.S., and
the Department of Electrical Engineering, Tokyo Ph.D. degrees in electrical engineering from the
Denki University, in 1986. He joined Shindengen National Taipei University of Technology, Taiwan,
Electric Mfg. Company Ltd., in 1986. Since 1999, in 2014, 2016, and 2021, respectively. He is cur-
he has been working with Tamura Corporation. rently a Firmware Engineer with the Appliances
He is mainly engaged in research and develop- Business Unit (APBU), Delta Electronics, Inc.
ment of switching power supplies and power elec- His research interests include bidirectional ac–dc/
tronics related products. In 2012, he succeeded dc–dc converter, wireless power transfer, resonant
in commercializing the world’s first ac adapter converter, energy storage systems, power electron-
for notebook PCs with 0W standby power. His ics, and digital control.
research interests include gate driver, ac/dc converter, LED power supply, and
current sensor.

MING-SHI HUANG (Member, IEEE) received

the B.S. degree in electrical engineering from
the National Taiwan University of Science and
Technology, Taiwan, in 1987, the M.S. degree
in electrical engineering from Tatung University,
HISASHI SHIBATA received the B.S. degree in Taiwan, in 1991, and the Ph.D. degree in elec-
communication engineering from the Shibaura trical engineering from the National Tsing Hua
Institute of Technology, in 1993. He joined Tamura University, Taiwan, in 2004. From 1987 to 2004,
Corporation, in 1993, and is mainly engaged in he was a Researcher with Mechanical Indus-
research and development of switching power sup- try Research Laboratories, Industrial Technology
plies and power electronics related products. His Research Institute. He is currently a Professor with the Department of Elec-
research interests include gate driver, ac/dc con- trical Engineering, National Taipei University of Technology, Taipei, Taiwan.
verter, LED power supply, and current sensor. His research interests include power electronics, variable-speed drives, and
electrical power train in vehicle applications.

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