Addressing Modes
When the microcontrollers execute an instruction, it performs specific
function on data. The data is stored at some source location. This data
must be moved or copied to destination location. The ways these
addresses location are specified are called as Addressing Modes.
Every Instruction consists of Opcode and Operand:-
Opcode: It is operational code which contains all the
information about which operation is to be performed,
register used and memory location which is to be used.
Operand: It is a data which is to be operated for a
specific task.
Types of addressing modes:
A. Immediate addressing mode
B. Direct addressing mode
C. Register addressing mode
D. Register indirect addressing mode
E. External addressing mode (Indexed addressing mode)
A. Immediate addressing mode :
In this addressing mode transfers 8 bit immediate data to destination.
e.g
1. MOV A, #6BH (This instruction moves immediate data hex 6B to
accumulator.)
2. MOV P1, #0FFH
3. MOV DPTR, #1234H
In this addressing mode we use '#' symbol to indicate immediate data.
Here ‘#’ symbol indicates that operand is a data. If ‘#’ is not present
then the hexadecimal number considered as a address.)
B. Direct addressing mode:
This is type of addressing mode; source operand is specified by its 8
bit addresses in an instruction after opcode.
e.g.
1. MOV B, 20H (The instruction above moves value at address
20H memory location to register B.)
2. MOV R0, 14H
C. Register addressing mode:
This is type of addressing mode, the source operand is specified by
the registers (R0 to R7, A, B)
e.g
1. MOV R0, A
2. ADD A, R5
3. MOV A, R5 (After execution of this instruction content of
register R5 is get copied to location accumulator.)
D. Register indirect addressing mode :
This is type of addressing mode; addresses of operand (data) are
specified indirectly by a register (R0, R1, DPTR).
e.g.
1. ADD A, @R0
2. MOVX A, @DPTR
3. MOV A, @R1 (Here in this instruction register R1 holds the
address, suppose value at R1 is '20H' then after execution of
above instruction value at location 20H is transferred to
accumulator.)
Here symbol '@' indicates address the register as a pointer. In this
type addressing mode only register R0 and R1 to provide indirect
address.
E. External addressing mode (Indexed addressing mode) :
This is type of addressing mode; data accessed from external RAM or
on chip ROM.
a. Code access (External ROM access):
Using these instruction only external memory can be accessed
Eg
1. MOVC A, @A+DPTR
Suppose Accumulator contain '01H' and DPTR contains value
'1000H' then after the execution of instruction 'MOVC A,
@A+DPTR the value at address '1001H' will be transferred to
accumulator.
2. MOVC A, @A+PC
b. Data access (External RAM access):
Using this instruction, the programmer can access the external
data memory.
Eg MOVX @R0, A
Instruction Sets of 8051
A. Transfer Instruction
Sr.
No Instruction Description Example
1 MOV A, Rn A = Rn MOV A, R1
2 MOV A, Direct A = [Direct] MOV A, 40H
3 MOV A, #data A = data MOV A, #31H
4 MOV A, @Ri A = [(Ri)] MOV A, @R1
5 MOV Rn, A Rn = A MOV R2, A
6 MOV Rn, direct Rn = [direct] MOV R3, 20H
7 MOV Rn, #data Rn = data MOV R7, #20H
8 MOV direct, A direct = A MOV 30H, A
9 MOV direct, Rn direct = Rn MOV 15H, R5
10 MOV direct1, direct2 direct1 = direct2 MOV 15H, 20H
11 MOV direct, @Ri direct = [(Ri)] MOV 30H, @R1
12 MOV direct, #data direct = data MOV 15H, #15H
13 MOV @Ri, A [(Ri)] = A MOV @R0, A
14 MOV @Ri, direct [(Ri)] = [direct] MOV @R1, 25H
15 MOV @Ri, #data [(Ri)] = data MOV @R0, #2FH
(DPTR) = #data 15-0
16 MOV DPTR, #data (DPH) = #data 15-8 MOV DPTR, #2467 H
(DPL) = #data 7-0
17 MOVC A, @A + DPTR
A = [(A) + (DPTR)] MOVC A, @A + DPTR
18 MOVC A, @A + PC
A = [(A) + (PC + 1))] MOVC A, @A + PC
19 MOVX A, @Ri A = [Ri] MOVX A, @R1
20 MOVX @Ri, A [Ri] = A MOVX @R0, A
21 MOVX @DPTR, A [DPTR] = A MOVX @1000H, A
A = Rn
22 XCH A, Rn XCH A, R5
Rn = A
A = [Direct]
23 XCH A, direct XCH A, 50H
[direct] = A
A = [(Ri)]
24 XCH A, @Ri XCH A, @R0
[(Ri)] = A
Rn = A
25 XCH Rn, A XCH R5, A
A = Rn
XCHD A, @R1
26 XCHD A, @Ri let A = 25H, R1 contain 37H
holding valu 47H, then A = 27,
@R1 = 45
(SP) = (SP) + 1
27 PUSH direct PUSH 30H
(SP) = direct
direct = (SP)
28 POP direct POP 30H
(SP) = (SP) - 1
B. Arithmatic instruction
Sr.
No Instruction Description Example
1 ADD A, Rn A = A + Rn ADD A, R7
2 ADD A, direct A = A + [direct] ADD A, 37H
3 ADD A, @Ri A = A + [(Ri)] ADD A, @R1
4 ADD A, #data A = A + data ADD A, #37H
5 ADDC A, Rn A = A + Rn + CF ADDC A, R7
6 ADDC A, direct A = A + [direct] + CF ADDC A, 37H
7 ADDC A, @Ri A = A + [(Ri)] + CF ADDC A, @R1
8 ADDC A, #data A = A + data + CF ADDC A, #37H
9 SUBB A, Rn A = A - Rn - CF SUBB A, R7
10 SUBB A, direct A = A - [direct] - CF SUBB A, 37H
11 SUBB A, @Ri A = A - [(Ri)] - CF SUBB A, @R1
12 SUBB A, #data A = A - data - CF SUBB A, #37H
13 INC Rn (Rn) = (Rn) + 1 INC R6
14 INC direct (direct) = (direct) + 1 INC 15H
15 INC @Ri [(Ri)] = [(Ri)] + 1 INC @R0
16 INC #data data = data + 1 INC #15H
DPTR = DPTR + 1
17 INC DPTR DPH = DPH + 1 INC 15FFH
DPL = DPL + 1
20 DEC Rn (Rn) = (Rn) - 1 DEC R6
21 DEC direct (direct) = (direct) - 1 DEC 15H
22 DEC @Ri [(Ri)] = [(Ri)] - 1 DEC @R0
23 DEC #data data = data - 1 DEC #15H
DPTR = DPTR - 1
24 DEC DPTR DPH = DPH - 1 DEC 15FFH
DPL = DPL - 1
(A) x (B), (A)(7-0) A = 50H, B = A0H
25 MUL AB (B) (15-8) MUL AB = (3200H)
A = 00H, B = 32H
(A) / (B), A = Quatient A = FBH, B = 12H
26 DIV AB B = Remainder DIV AB, A = 0DH
B = 11H
C. Logical instruction
Sr.
No Instruction Description Example
1 ANL A, Rn (A) = (A) AND (Rn) ANL A, R5
2 ANL A, direct (A) = (A) AND (direct) ANL A, 35H
3 ANL A, @Ri (A) = (A) AND [(Ri)] ANL A, @R1
4 ANL A, #data (A) = (A) AND (data) ANL A, #35H
5 ANL direct, A (direct) = (direct) AND (A) ANL 20H, A
6 ANL direct, # data (direct) = (direct) AND (A) ANL 15H, # 30H
7 ORL A, Rn (A) = (A) OR (Rn) ORL A, R5
8 ORL A, direct (A) = (A) OR (direct) ORL A, 35H
9 ORL A, @Ri (A) = (A) OR [(Ri)] ORL A, @R1
10 ORL A, #data (A) = (A) OR (data) ORL A, #35H
11 ORL direct, A (direct) = (direct) OR (A) ORL 20H, A
12 ORL direct, # data (direct) = (direct) OR (A) ORL 15H, # 30H
13 XRL A, Rn (A) = (A) XOR (Rn) XRL A, R5
14 XRL A, direct (A) = (A) XOR (direct) XRL A, 35H
15 XRL A, @Ri (A) = (A) XOR [(Ri)] XRL A, @R1
16 XRL A, #data (A) = (A) XOR (data) XRL A, #35H
17 XRL direct, A (direct) = (direct) XOR (A) XRL 20H, A
18 XRL direct, # data (direct) = (direct) XOR (A) XRL 15H, # 30H
19 CLR A A=0 CLR A
20 CPL A A=Ᾱ CPL A
RL A
if A = 58H (0101 1000)
21 RL A
after RL A
A = 1011 0000 = B0H
RLC A
if A = 72H (0111 0010) and CY = 1
22 RLC A
after RLC A
A = (1110 0101) = E5H & CY = 0
RR A
if A = 75H (0111 0101)
23 RR A
after RR A
A = 1011 1010 = BAH
RRC A
if A = 85H (1000 0101) and CY = 1
24 RRC A
after RRC A
A = 1100 0010) = C2H & CY = 1
SWAP A
if A = 87H (1000 0111)
25 SWAP A
After SWAP A
A = 0111 1000 = 78H
D. Boolean Variable manipulation Instruction
Sr.
No Instruction Description Example
CLR P2.3
(Bit) = 0 if Port 2 to has ADH = 1010 1101
1 CLR Bit
after CLR P2.3
port 2 has 1010 0101 = A5H
SET P2.3
if Port 2 to has A5H = 1010 0101
2 SET B (Bit) = 1
after SET P2.3
port 2 has 1010 1101 = ADH
CPL P2.3
if Port 2 to has A5H = 1010 0101
3 CPL Bit
after CPL P2.3
port 2 has 1010 1101 = ADH
ANL C, A.4
if C = 1, and A = 11H (0001 0001)
after ANL C, A.4 i.e. (1 AND 1)
then C = 1
4 ANL C, <Src-bit> C = C AND <Src-bit>
ANL C, /A.4
if C = 1, and A = 11H (0001 0001)
after ANL C, A.4 i.e. (1 AND /1)
then C = 0
ORL C, A.4
if C = 1, and A = 26H (0010 0110)
after ORL C, A.4 i.e. (1 OR 0)
then C = 1
5 ORL C, <Src-bit> C = C OR <Src-bit>
ORL C, /A.4
if C = 1, and A = 26H (0010 0110)
after ORL C, A.4 i.e. (1 OR /0)
then C = 1
MOV A.3, C
if A = 23H (0010 0011) , C = 1
6 MOV bit, C Bit = C
After MOV A.3, C
then A = 0010 1011 =
MOV C, A.5
if A = 11H (0001 0001) , C = 1
7 MOV C, bit C = Bit
After MOV C, A.5
then C = 0
E. Program and Machine controls Instruction
Sr.
No Instruction Description Example
(PC) = (PC) + 2 ACALL add
(SP) = (SP) + 1 let SP = 0AH, PC = 0237H
((SP)) = (PC 7-0) "Add" is at 0435H
1 ACALL addr11 (SP) = (SP) + 1 After ACALL add
PC = 0239H = 0000 0010 0011
((SP)) = (PC 15-8) 1001
(PC 10-0) = PAGE ADDRESS SP is at 0BH = 0011 1001 = 39H
SP is at 0CH = 0000 0010 = 02H
(PC) = (PC) + 3 LCALL add
(SP) = (SP) + 1 let SP = 0AH, PC = 0237H
((SP)) = (PC 7-0) "Add" is at 0435H
2 LCALL addr16 (SP) = (SP) + 1 After ACALL add
PC = 023AH = 0000 0010 0011
((SP)) = (PC 15-8) 1010
(PC) = addr 15-0 SP is at 0BH = 0011 1010 = 3AH
SP is at 0CH = 0000 0010 = 02H
(PC 15-8) = ((SP))
(SP)= (SP) - 1
3 RET
(PC 7-0) = ((SP))
(SP)= (SP) - 1
Stack and its Operations
Stack in the 8051
The stack is a section of a RAM used by the CPU to store information
such as data or memory address on temporary basis. And which work on
LIFO (Last in and first out) basis. The CPU needs this storage area
considering limited number of registers.
As the stack is a section of a RAM, there are registers inside the CPU to
point to it. The register used to access the stack is known as the stack
pointer register.
The storing operation of a CPU register in the stack is known as a PUSH,
and getting the contents from the stack back into a CPU register is called
a POP.
Pushing into the Stack
In the 8051, the stack pointer (SP) points to the last used location of the
stack. When data is pushed onto the stack, the stack pointer (SP) is
incremented by 1. When PUSH is executed, the contents of the register
are saved on the stack and SP is incremented by 1. To push the registers
onto the stack, their RAM addresses must be used.
Popping from the Stack
Popping the contents of the stack back into a given register is the
opposite to the process of pushing. With every pop operation, the top
byte of the stack is copied to the register specified by the instruction and
the stack pointer is decremented once.
Flag – Every bit has different functions
Program Status Word
It is 8 bit register, used to give information of nature of latest result which is obtained from
Arithmetic Logical Unit (ALU).
D7 D6 D5 D4 D3 D2 D1 D0
CY AC F0 RS1 RS0 OV -- P
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0
MSB LSB
Bit D7 (Carry flag “CY”)
When carry is generated from MSB of ALU result, then CY = 1 otherwise CY = 0
Bit D6 (Auxiliary flag “AC”)
When carry is generated from lower nibble ( i.e. from D3 to D4) of ALU result, then
AC = 1 otherwise AY = 0. It is used in BCD operation.
Bit D5 (F0)
It is user defined flag, User can set / reset this flag and assigned functions into it.
Bit D4 and D3 (RS1 and RS0)
This are register bank of select bit. They are used to select any one bank out of 4
register bank at a time. If it is not select then it default consider as Bank 0
RS1 RS0 Bank Selected
0 0 Bank 0
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3
Bit D2 (Overflow flag “OV”)
When the value of result becomes more than destination, then the result cant be stored
and this is overflow, then OV = 1 otherwise OV = 0
Bit D1
It is unused bit.
Bit D0 (Parity Flag)
When parity of the result byte from ALU is even then P = 1 otherwise P = 0
i.e Even no of “1”s P=1
Odd no of “1”s P=0
Data Pointer:
The Data Pointer (DPTR) is the 8051'sonly user-accessible 16-bit (2-byte)
register. It is used by the 8051 to access external memory using the address
indicated by DPTR. DPTR is the only 16-bit register available and is often used
to store 2-byte values.
Program Counter:
The Program Counter (PC) is a 2-byte address which tells the 8051 where the
next instruction to execute is found in memory. When the 8051 is initialized PC
always starts at 0000h and is incremented each time an instruction is executed.
Interrupt:
An interrupt is a signal to the processor emitted by hardware or software
indicating an event that needs immediate attention. Whenever an interrupt
occurs, the controller completes the execution of the current instruction and
starts the execution of an Interrupt Service Routine (ISR).
ISR tells the processor or controller what to do when the interrupt occurs. The
interrupts can be either hardware interrupts or software interrupts.
Subroutines:
Subroutines are the set of instructions that will written separately from main
program regarding a task that occur at main program frequently
Program and Machine Control Instruction
A. LOOP:
Repeating a sequence of instructions a certain number of times is called a loop.
B. CALL:
1. ACALL
Function: Absolute Call Within 2K Block
Syntax: ACALL code address
Bytes: 2
Description: ACALL unconditionally calls a subroutine at the indicated code
address. ACALL pushes the address of the instruction that follows ACALL
onto the stack, least-significant-byte first, most-significant-byte second. The
Program Counter is then updated so that program execution continues at the
indicated address.
The new value for the Program Counter is calculated by replacing the least-
significant-byte of the Program Counter with the second byte of the ACALL
instruction, and replacing bits 0-2 of the most-significant-byte of the Program
Counter with 3 bits that indicate the page. Bits 3-7 of the most-significant-byte
of the Program Counter remain unchanged.
Since only 11 bits of the Program Counter are affected by ACALL, calls may
only be made to routines located within the same 2k block as the first byte that
follows ACALL
2. LCALL Instruction:
Function: Long Call
Syntax: LCALL code addr
Byte: 3
Description: LCALL calls a program subroutine. LCALL increments the
program counter by 3 (to point to the instruction following LCALL) and pushes
that value onto the stack (low byte first, high byte second). The Program
Counter is then set to the 16-bit value which follows the LCALL opcode,
causing program execution to continue at that address.
C. RETURN
1. RET
Function: Return From Subroutine
Syntax: RET
Byte: 1
Description: RET is used to return from a subroutine previously called by
LCALL or ACALL. Program execution continues at the address that is
calculated by popping the topmost 2 bytes off the stack. The most-significant-
byte is popped off the stack first, followed by the least-significant-byte.
2. RETI Instruction: (Return from Interrupt)
Function: Return From Interrupt
Syntax: RETI
Byte: 1
Description: RETI is used to return from an interrupt service routine. RETI
first enables interrupts of equal and lower priorities to the interrupt that is
terminating. Program execution continues at the address that is calculated by
popping the topmost 2 bytes off the stack. The most-significant-byte is popped
off the stack first, followed by the least-significant-byte.
RETI functions identically to RET if it is executed outside of an interrupt
service routine.
D. JUMP (unconditionally jumps)
1. AJMP
Function: Absolute Jump Within 2K Block
Syntax: AJMP code address
Byte: 2
Description: AJMP unconditionally jumps to the indicated code address. The
new value for the Program Counter is calculated by replacing the least-
significant-byte of the Program Counter with the second byte of the AJMP
instruction, and replacing bits 0-2 of the most-significant-byte of the Program
Counter with 3 bits that indicate the page of the byte following the AJMP
instruction. Bits 3-7 of the most-significant-byte of the Program Counter remain
unchanged.
Since only 11 bits of the Program Counter are affected by AJMP, jumps may
only be made to code located within the same 2k block as the first byte that
follows AJMP.
2. LJMP
Function: Long Jump
Syntax: LJMP code addr
Byte: 3
Description: LJMP jumps unconditionally to the specified code addr.
3. SJMP
Function: Short Jump
Syntax: SJMP reladdr
Bytes 2
Description: SJMP jumps unconditionally to the address
specified reladdr. Reladdr must be within -128 or +127 bytes of the instruction
that follows the SJMP instruction.
E. JUMP (conditionally jumps)
1. JB
Function: Jump if Bit Set
Syntax: JB bit addr, reladdr
Byte: 3
Description: JB branches to the address indicated by reladdr if the bit indicated
by bit addr is set. If the bit is not set program execution continues with the
instruction following the JB instruction.
2. JNB
Function: Jump if Bit Not Set
Syntax: JNB bit addr, reladdr
Byte: 3
Description: JNB will branch to the address indicated by reladdress if the
indicated bit is not set. If the bit is set program execution continues with the
instruction following the JNB instruction.
3. JBC
Operation: JBC
Function: Jump if Bit Set and Clear Bit
Syntax: JB bit addr, reladdr
Byte: 3
Description: JBC will branch to the address indicated by reladdr if the bit
indicated by bit addr is set. Before branching to reladdr the instruction will
clear the indicated bit. If the bit is not set program execution continues with the
instruction following the JBC instruction.
4. JC
Function: Jump if Carry Set
Syntax: JC reladdr
Byte: 2
Description: JC will branch to the address indicated by reladdr if the Carry Bit
is set. If the Carry Bit is not set program execution continues with the
instruction following the JC instruction.
5. JNC
Function: Jump if Carry Not Set
Syntax: JNC reladdr
Byte: 2
Description: JNC branches to the address indicated by reladdr if the carry bit is
not set. If the carry bit is set program execution continues with the instruction
following the JNB instruction.
6. JMP
Function: Jump to Data Pointer + Accumulator
Syntax: JMP @A+DPTR
Byte: 1
Description: JMP jumps unconditionally to the address represented by the sum
of the value of DPTR and the value of the Accumulator.
7. JZ
Function: Jump if Accumulator Zero
Syntax: JZ reladdr
Bytes: 2
Description: JZ branches to the address indicated by reladdr if the
Accumulator contains the value 0. If the value of the Accumulator is non-zero
program execution continues with the instruction following the JNZ instruction.
8. JNZ
Function: Jump if Accumulator Not Zero
Syntax: JNZ reladdr
Byte: 2
Description: JNZ will branch to the address indicated by reladdr if the
Accumulator contains any value except 0. If the value of the Accumulator is
zero program execution continues with the instruction following the JNZ
instruction.
9. CJNE
Function: Compare and Jump If Not Equal
Syntax: CJNE operand1,operand2,reladdr
Bytes: 3
Description: CJNE compares the value of operand1 and operand2 and
branches to the indicated relative address if operand1 and operand2 are not
equal. If the two operands are equal program flow continues with the instruction
following the CJNE instruction.
The Carry bit (C) is set if operand1 is less than operand2, otherwise it is
cleared.
10.DCJNZ
Function: Decrement and Jump if Not Zero
Syntax: DJNZ register,reladdr
Byres: 3
Description: DJNZ decrements the value of register by 1. If the initial value
of register is 0, decrementing the value will cause it to reset to 255 (0xFF Hex).
If the new value of register is not 0 the program will branch to the address
indicated by relative addr. If the new value of register is 0 program flow
continues with the instruction following the DJNZ instruction.
11.NOP
Function: None, waste time
Syntax: No Operation
Byte: 1
Description: NOP, as it's name suggests, causes No Operation to take place for
one machine cycle. NOP is generally used only for timing purposes. Absolutely
no flags or registers are affected.
