Module 1

General Aspects of Computer Organization

General Aspects of Computer Organization, Difference between microprocessors and microcontrollers.

Embedded systems and general-purpose computers. Brief description of evolution of x86, ARM, and
AVR computer families. Von Neumann and Harvard CPU architectures. Steps followed by CPU in
instruction execution. Cursory view of general design principles followed to improve performance of
modern computers. Primary memory organization. Types of memory, input and output devices.
Choosing a microcontroller for an application.

General Aspects of Computer Organization

The internal working of every computer can be broken down into three parts: CPU (central
processing unit), memory, and I/O (input/output) devices. The function of the CPU is to execute
(process) information stored in memory. The function of I/O devices such as the keyboard and
video monitor is to provide a means of communicating with the CPU. The CPU is connected
to memory and I/O through strips of wire called a bus. The bus inside a computer allows
carrying information from place to place just as a street allows cars to carry people from place
to place. In every computer there are three types of buses: address bus, data bus, and control
bus.
For a device (memory or I/O) to be recognized by the CPU, it must be assigned an address.
The address assigned to a given device must be unique; no two devices are allowed to have the
same address. The CPU puts the address (in binary, of course) on the address bus, and the
decoding circuitry finds the device. Then the CPU uses the data bus either to get data from that
device or to send data to it. The control buses are used to provide read or write signals to the
device to indicate if the CPU is asking for information or sending information. Of the three
buses, the address bus and data bus determine the capability of a given CPU.
The Data Bus
Because data buses are used to carry information in and out of a CPU, the more data buses
available, the better the CPU. If one thinks of data buses as high- way lanes, it is clear that
more lanes provide a better pathway between the CPU and its external devices (such as printers,
RAM, ROM,). By the same token, that increase in the number of lanes increases the cost of
construc- tion. More data buses mean a more expensive CPU and computer. The average size
of data buses in CPUs varies between 8 and 64 bits. Early personal computers such as Apple 2
used an 8-bit data bus, while supercomputers such as Cray used a 64-bit data bus. Data buses
are bidirectional, because the CPU must use them either to receive or to send data. The
processing power of a computer is relat- ed to the size of its buses, because an 8-bit bus can
send out 1 byte a time, but a 16-bit bus can send out 2 bytes at a time, which is twice as fast.
The Address Bus
Because the address bus is used to identify the devices and memory connected to the CPU, the
more address buses available, the larger the number of devices that can be addressed. In other
words, the number of address buses for a CPU determines the number of locations with which
it can communicate. The number of locations is always equal to 2x, where x is the number of
address lines, regardless of the size of the data bus. For example, a CPU with 16 address lines
can provide a total of 65,536 (216) or 64K of addressable memory. Each location can have a
maximum of 1 byte of data. This is because all general-purpose micro- processor CPUs are
what is called byte addressable. As another example, the IBM PC AT uses a CPU with 24
address lines and 16 data lines. Thus, the total acces- sible memory is 16 megabytes (224 = 16
megabytes). In this example there would be 224 locations, and because each location is one
byte, there would be 16 megabytes of memory. The address bus is a unidirectional bus, which
means that the CPU uses the address bus only to send out addresses. To summarize: The total
number of memory locations addressable by a given CPU is always equal to 2x, where x is the
number of address bits, regardless of the size of the data bus. CPU and its relation to RAM and
ROM
For the CPU to process information, the data must be stored in RAM or ROM. The function of
ROM in computers is to provide information that is fixed and permanent. This is information
such as tables for character patterns to be displayed on the video monitor, or programs that are
essential to the working of the computer, such as programs for testing and finding the total
amount of RAM installed on the system, or for displaying information on the video monitor.
In contrast, RAM stores temporary information that can change with time, such as vari- ous
versions of the operating system and application packages such as word pro- cessing or tax
calculation packages. These programs are loaded from the hard drive into RAM to be processed
by the CPU. The CPU cannot get the information from the disk directly because the disk is too
slow. In other words, the CPU first seeks the information to be processed from RAM (or ROM).
Only if the data is not there does the CPU seek it from a mass storage device such as a disk,
and then it transfers the information to RAM. For this reason, RAM and ROM are sometimes
referred to as primary memory and disks are called secondary memory. Next, we discuss
various types of semiconductor memories and their characteristics such as capacity,
organization, and access time.
Difference between microprocessors and microcontrollers:

Microcontroller Microprocessor

A microcontroller is a specialized The microprocessor is designed to be general-

form of a microprocessor purpose.

It is cost-effective. It is a silicon chip

It is self-sufficient. It is a dependent unit

The microcontroller is used to The Microprocessor is

perform a particular tasks. used to perform a certain task.

Its power consumption is low. Its power consumption is high.

It contains CPU, RAM, ROM, It requires a combination of timers, controllers

Registers, Timer and input/output memory chips.
ports.

Its size is smaller. Its size is larger.

It is a chip which is called single It is a general purpose device which is called a

chip computer. CPU.

Microcontroller have no advantage It have advantages of versatility such that

of designing RAM, ROM, I/O port. designer can decide the aount of RAM, ROM,
I/O port as needed.
 Its processing power is lower than Its processing power is higher.
microprocessor.

It uses Harvard Architecture. It uses Von Neumann Architecture.

It’s system cost is low. It’s system cost is high.

Each instruction needs an internal Each instruction needs an external operation.

operation.

For Example- Television. For Example- Personal Computers.

Embedded systems and general-purpose computers

General Purpose Computer Embedded Systems

It is designed using a microprocessor as It is mostly designed using a microcontroller as

the main processing unit. the main processing unit.

It contains a large memory semiconductor It uses semiconductor memories, but does not
memories like cache and RAM. it also require secondary memories like hard disk, CD.
contains secondary storage like hard disks It sometimes has special memory called flash
etc. memory.

It is designed such that it can cater to It is designed such that it can cater to a particular
multiple tasks as per requirement. predefined task.

It is mostly costlier compared to the It is cheaper compared to a computer.

embedded systems

It requires huge number of peripheral It is cheaper as it requires less no of peripheral

devices and their controllers devices and their controllers are microcontroller
chip itself.

The Operating system and other software The operating system(mostly RTOS i.e Real
for the general-purpose computers, are Time Operating System) and other software
normally complicated and occupy more occupy less memory space.
memory space
Brief description of evolution of x86, ARM, and AVR computer families
Microcontroller versus general-purpose microprocessor
What is the difference between a microprocessor and a microcontroller? By microprocessor is
meant the general-purpose microprocessors such as Intel's x86 family (8086, 80286, 80386,
80486, and the Pentium) or Motorola's PowerPC family. These microprocessors contain no
RAM, no ROM, and no I/O ports on the chip itself. For this reason, they are commonly referred
to as general-purpose microprocessors.
A system designer using a general-purpose microprocessor such as the Pentium or the PowerPC
must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the
addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more
expensive, they have the advantage of versatility, enabling the designer to decide on the amount
of RAM, ROM, and I/O ports needed to fit the task at hand. This is not the case with
microcontrollers. A microcontroller has a CPU (a microprocessor) in addition to a fixed amount
of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, RAM,
ROM, I/O ports, and timer are all embedded together on one chip; therefore, the designer
cannot add any external memory, I/O, or timer to it. The fixed amount of on-chip ROM, RAM,
and number of I/O ports in microcontrollers makes them ideal for many applications in which
cost and space are critical.
In many applications, for example, a TV remote control, there is no need for the
computing power of a 486 or even an 8086 microprocessor.
In many applications, the space used, the power consumed, and the price per unit are
much more critical considerations than the computing power. These applications most often
require some I/O operations to read signals and turn on and off certain bits. For this reason,
some call these processors IBP, "itty- bitty processors."
It is interesting to note that many microcontroller manufacturers have gone as far as integrating
an ADC (analog-to-digital converter) and other peripherals into the microcontroller.
Microcontrollers for embedded systems
In the literature discussing microprocessors, we often see the term embedded system.
Microprocessors and microcontrollers are widely used in embedded system products. An
embedded system is controlled by its own internal microprocessor (or micro- controller) as
opposed to an external controller. Typically, in an embedded system, the microcontroller's
ROM is burned with a purpose for specific functions needed for the system. A printer is an
example of an embedded system because the processor inside it performs one task only;
namely, getting the data and printing it. Contrast this with a Pentium-based PC (or any x86
PC), which can be used for any number of applications such as word processor, print server,
bank teller terminal, video game player, network server, or Internet terminal. A PC can also
load and run software for a variety of applications. Of course, the reason a PC can per- form
myriad tasks is that it has RAM memory and an operating system that loads the application
software into RAM and lets the CPU run it. In an embedded system, typically only one
application software is burned into ROM. An x86 PC contains or is connected to various
embedded products such as the keyboard, print- er, modem, disk controller, sound card, CD-
ROM driver, mouse, and so on. Each one of these peripherals has a microcontroller inside it
that performs only one task. For example, inside every mouse a microcontroller performs the
task of finding the mouse's position and sending it to the PC. Some embedded products like
Garage door openers, Answering machines, Fax machines, Home computers, TV, Cable TV
tuner, Camcorder, Remote controls, Lighting control, Paging, Toys, Exercise equipment, Fax
machine, Colour printer, Air bag, Instrumentation Security system, Transmission control use
Microcontrollers.
Brief description of evolution of x86, ARM, and AVR computer families
Three popular instruction set architectures (ISAs): x86, ARM and AVR. The x86 architecture
is found in nearly all personal computers (including Windows and Linux PCs and Macs) and
server systems. Personal computers are of interest because every reader has undoubtedly used
one. Servers are of interest because they run all the services on the Internet. The ARM
architecture dominates the mobile market. For example, most smartphones and tablet
computers are based on ARM processors. Finally, the AVR architecture is found in very low-
cost microcontrollers found in many embedded computing applications. Embedded computers
are invisible to their users but control cars, televisions, microwave ovens, washing machines,
and practically every other electrical device.

Introduction to the x86 Architecture:

In 1968, Robert Noyce, inventor of the silicon integrated circuit; Gordon Moore, of Moore’s
law fame; and Arthur Rock, a San Francisco venture capitalist, formed the Intel Corporation to
make memory chips.

In its first year of operation, Intel sold only $3000 worth of chips, but business has picked up
since then (Intel is now the world’s largest CPU chip manufacturer). In the late 1960s,
calculators were large electromechanical machines the size of a modern laser printer and
weighing 20 kg. In Sept. 1969, a Japanese company, Busicom, approached Intel with a request
that it manufacture 12 custom chips for a proposed electronic calculator. The Intel engineer
assigned to this project, Ted Hoff, looked at the plan and realized that he could put a 4-bit
general-purpose CPU on a single chip that would do the same thing and be simpler and cheaper
as well. Thus, in 1970, the first single-chip CPU, the 2300-transistor 4004, was born. It is worth
noting that neither Intel nor Busicom had any idea what they had just done. When Intel decided
that it might be worth a try to use the 4004 in other projects, it offered to buy back all the rights
to the new chip from Busicom by returning the $60,000 Busicom had paid Intel to develop it.
Intel’s offer was quickly accepted, at which point it began working on an 8-bit version of the
chip, the 8008, introduced in 1972. The Intel family, starting with the 4004 and 8008, is shown
in Fig. 1-11, giving the introduction date, clock rate, transistor count, and memory.

All the Intel chips are backward compatible with their predecessors as far back as the 8086. In
other words, a Pentium 4 or Core can run old 8086 programs without modification. This
compatibility has always been a design requirement for Intel, to allow users to maintain their
existing investment in software. Of course, the Core is four orders of magnitude more complex
than the 8086, so it can do quite a few things that the 8086 could not do. These piecemeal
extensions have resulted in an architecture that is not as elegant as it might have been had
someone given the Pentium 4 architects 42 million transistors and instructions to start all over
again. It is interesting to note that although Moore’s law has long been associated with the
number of bits in a memory, it applies equally well to CPU chips. By plotting the transistor
counts against the date of introduction of each chip on a semilog scale, we see that Moore’s
law holds here too.

While Moore’s law will probably continue to hold for some years to come, another problem is
starting to overshadow it: heat dissipation. Smaller transistors make it possible to run at higher
clock frequencies, which requires using a higher voltage. Power consumed and heat dissipated
is proportional to the square of the voltage, so going faster means having more heat to get rid
of. At 3.6 GHz, the Pentium 4 consumes 115 watts of power. That means it gets about as hot as
a 100-watt light bulb. Speeding up the clock makes the problem worse.
In November 2004, Intel cancelled the 4-GHz Pentium 4 due to problems dissipating the heat.
Large fans can help but the noise they make is not popular with users, and water cooling, while
used on large mainframes, is not an option for desktop machines (and even less so for notebook
computers). As a consequence, the once-relentless march of the clock may have ended, at least
until Intel’s engineers figure out an efficient way to get rid of all the heat generated. Instead,
Intel CPU designs now put two or more CPUs on a single chip, along with large shared cache.
Because of the way power consumption is related to voltage and clock speed, two CPUs on a
chip consume far less power than one CPU at twice the speed. As a consequence, the gain
offered by Moore’s law may be increasingly exploited in the future to include more cores and
larger on-chip caches, rather than higher and higher clock speeds. Taking advantage of these
multiprocessors poses great challenges to programmers, because unlike the sophisticated
uniprocessor microarchitectures of the past that could extract more performance from existing
programs, multiprocessors require the programmer to explicitly orchestrate parallel execution,
using threads, semaphores, shared memory and other headache- and bug-inducing
technologies.
Introduction to the ARM Architecture
In the early 80s, the U.K.-based company Acorn Computer, flush with the success of their 8-
bit BBC Micro personal computer, began working on a second machine with the hope of
competing with the recently released IBM PC. The BBC Micro was based on the 8-bit 6502
processor, and Steve Furber and his colleagues at Acorn felt that the 6502 did not have the
muscle to compete with the IBM PC’s 16-bit 8086 processor. They began looking at the options
in the marketplace, and decided that they were too limited. Inspired by the Berkeley RISC
project, in which a small team designed a remarkably fast processor (which eventually led to
the SPARC architecture), they decided to build their own CPU for the project. They called their
design the Acorn RISC Machine (or ARM, which would later be rechristened the Advanced
RISC machine when ARM eventually split from Acorn). The design was completed in 1985.
It included 32-bit instructions and data, and a 26-bit address space, and it was manufactured
by VLSI Technology. The first ARM architecture (called the ARM2) appeared in the Acorn
Archimedes personal computer. The Archimedes was a very fast and inexpensive machine for
its day, running up to 2 MIPS (millions of instructions per second) and costing only 899 British
pounds at launch. The machine became very popular in the UK, Ireland, Australia and New
Zealand, especially in schools.
Based on the success of the Archimedes, Apple approached Acorn to develop an ARM
processor for their upcoming Apple Newton project, the first palmtop computer. To better
focus on the project, the ARM architecture team left Acorn to create a new company called
Advanced RISC Machines (ARM). Their new processor was called the ARM 610, which
powered the Apple Newton when it was release in 1993. Unlike the original ARM design, this
new ARM processor incorporated a 4-KB cache that significantly improved the design’s
performance. Although the Apple Newton was not a great success, the ARM 610 did see other
successful applications including Acorn’s RISC PC computer. In the mid-1990s, ARM
collaborated with Digital Equipment Corporation to develop a high-speed, low-power
version of the ARM, intended for energy-frugal mobile applications such as PDAs. They
produced the StrongARM design, which from its first appearance sent waves through the
industry due to its high speed (233 MHz) and ultralow power demands (1 watt). It gained
efficiency through a simple, clean design that included two 16-KB caches for instructions and
data. The StrongARM and its successors at DEC were moderately successful in the
marketplace, finding their way into a number of PDAs, set-top boxes, media devices, and
routers.
Perhaps the most venerable of the ARM architectures is the ARM7 design, first released by
ARM in 1994 and still in wide use today. The design included separate instruction and data
caches, and it also incorporated the 16-bit Thumb instruction set. The Thumb instruction set is
a shorthand version of the full 32-bit ARM instruction set, allowing programmers to encode
many of the most common operations into smaller 16-bit instructions, significantly reducing
the amount of program memory needed. The processor has worked well for a wide range of
low to middle-end embedded applications such as toasters, engine control, and even the
Nintendo Gameboy Advance hand-held gaming console.
Unlike many computer companies, ARM does not manufacture any microprocessors. Instead,
it creates designs and ARM-based developer tools and libraries, and licenses them to system
designers and chip manufacturers. For example, the CPU used in the Samsung Galaxy Tab
Android-based tablet computer is an ARM based processor. The Galaxy Tab contains the Tegra
2 system-on-chip processor, which includes two ARM Cortex-A9 processors and an Nvidia
GeForce graphics processing unit. The Tegra 2 cores were designed by ARM, integrated into a
system-on-a-chip design by Nvidia, and manufactured by Taiwan Semiconductor
Manufacturing Company (TSMC). It’s an impressive collaboration by companies in different
countries in which all of the companies contributed value to the final design. The design
contains three ARM processors: two 1.2-GHz ARM Cortex-A9 cores plus an ARM7 core. The
Cortex-A9 cores are dual-issue out-of-order cores with a 1-MB L2 cache and support for
shared-memory multiprocessing. (That’s a lot of buzzwords that we will get into in later
chapters. For now, just know that these features make the design very fast!)
The ARM7 core is an older and smaller ARM core used for system configuration and
power management. The graphics core is a 333-MHz GeForce graphics processing unit
(GPU) design optimized for low-power operation. Also included on the Tegra 2 are a video
encoder/decoder, an audio processor and an HDMI video output interface. The ARM
architecture has found great success in the low-power, mobile and embedded markets. In
January 2011, ARM announced that it had sold 15 billion ARM processors since its inception,
and indicated that sales were continuing to grow. While tailored for lower-end markets, the
ARM architecture does have the computational capability to perform in any market, and there
are hints that it may be expanding its horizons.

Introduction to the AVR Architecture

Our third example is very different from our first (the x86 architecture, used in personal
computers and servers) and second (the ARM architecture, used in PDAs and smartphones). It
is the AVR architecture, which is used in very low-end embedded systems.
The AVR story starts in 1996 at the Norwegian Institute of Technology, where students AlfEgil
Bogen and Vegard Wollan designed an 8-bit RISC CPU called the AVR. It was reportedly given
this name because it was ‘‘(A)lf and (V)egard’s (R)ISC processor.’’ Shortly after the design
was completed, Atmel bought the design and started Atmel Norway, where the two architects
continued to refine the AVR processor design. Atmel released their first AVR microcontroller,
the AT90S1200, in 1997.
To ease its adoption by system designers, they implemented the pinout to be exactly the same
as that of the Intel 8051, which was one of the most popular microcontrollers at the time. Today
there is much interest in the AVR architecture because it is at the heart of the very popular
open-source Arduino embedded controller platform. The AVR architecture is implemented
in three classes of microcontrollers, listed in Fig. 1-15.
The lowest class, the tinyAVR is designed for the most area-, power- and cost-constrained
applications. It includes an 8-bit CPU, basic digital I/O support, and analog input support (for
example, reading temperature values off a thermistor). The tinyAVR is so small that its pins
work double duty, such that they can be reprogrammed at run time to any of the digital or
analog functions supported by the microcontroller.
The megaAVR, which is found in the popular Arduino open-source embedded system,
also adds serial I/O support, internal clocks, and programmable analog outputs.
The top end of the bottom end is the AVR XMEGA microcontroller, which also incorporates
an accelerator for cryptographic operations plus built-in support for USB interfaces.

Along with various additional peripherals, each AVR processor class includes some additional
memory resources. Microcontrollers typically have three types of memory on board: flash,
EEPROM, and RAM.
Brief history of the AVR microcontroller
The basic architecture of AVR was designed by two students of Norwegian Institute of
Technology (NTH), Alf-Egil Bogen and Vegard Wollan, and then was bought and developed
by Atmel in 1996. You may ask what AVR stands for, AVR can have different meanings for
different people! Atmel says that it is nothing more than a product name, but it might stand for
Advanced Virtual RISC, or Alf and Vegard RISC (the names of the AVR designers).
There are many kinds of AVR microcontroller with different properties. Except for AVR32,
which is a 32-bit microcontroller, AVRs are all 8-bit micro- processors, meaning that the
CPU can work on only 8 bits of data at a time. Data larger than 8 bits has to be broken into 8-
bit pieces to be processed by the CPU. One of the problems with the AVR microcontrollers is
that they are not all 100% compatible in terms of software when going from one family to
another family. To run programs written for the ATtiny25 on a ATmega64, we must recompile
the program and possibly change some register locations before loading it into the ATmega64.
AVRs are generally classified into four broad groups: Mega, Tiny, Special purpose, and
Classic. ATmega32 is powerful, widely available, and comes in DIP packages, which makes it
ideal for educational purposes. For those who have mastered the Mega family, understanding
the other families is very easy and straightforward. The following is a brief description of the
AVR microcontroller.

AVR features
The AVR is an 8-bit RISC single-chip microcontroller with Harvard architecture that comes
with some standard features such as on-chip program (code) ROM, data RAM, data EEPROM,
timers and I/O ports. See Figure 2. Most AVRs have some additional features like ADC, PWM,
and different kinds of serial interface such as USART, SPI, 12C (TWI), CAN, USB, and so on.

AVR microcontroller program ROM

In microcontrollers, the ROM is used to store programs and for that reason it is called program
or code ROM. Although the AVR has 8M (megabytes) of program (code) ROM space, not all
family members come with that much ROM installed. The program ROM size can vary from
1K to 256K at the time of this writing, depending on the family member. The AVR was one of
the first microcontrollers to use on-chip Flash memory for program storage.
The Flash memory is ideal for fast development because Flash memory can be erased in
seconds com- pared to the 20 minutes or more needed for the UV-EPROM.

AVR microcontroller data RAM and EEPROM.

While ROM is used to store program (code), the RAM space is for data storage. The AVR has
a maximum of 64K bytes of data RAM space. Not all of the family members come with that
much RAM. The data RAM space has three com- ponents general-purpose registers, I/O
memory, and internal SRAM. There are 32 general-purpose registers in all of the AVRs, but
the SRAM's size and the I/O memory k size varies from chip to chip. On the Atmel website,
whenever the size of RAM is mentioned the internal SRAM size is meant. The internal SRAM
space is used for a read write scratch pad. In AVR, we also have a small amount of EEPROM
to store critical data that does not need to be changed very often.

AVR microcontroller I/O pins

The AVR can have from 3 to 86 pins for I/O. The number of I/O pins depends on the number
of pins in the package itself. The number of pins for the we can use AVR package goes from 8
to 100 at this time. In the case of the 8-pin AT90S2323, we have 3 pins for I/O, while in the
case of the 100-pin ATmega1280, up to 86 pins for I/O.

AVR microcontroller peripherals

Most of the AVRs come with ADC (analog-to-digital converter), timers, and USART
(Universal Synchronous Asynchronous Receiver Transmitter) as standard peripherals. The
ADC is 10-bit and the number of ADC channels in AVR chips varies and can be up to 16,
depending on the number of pins in the package. The AVR can have up to 6 timers besides the
watchdog timer. The USART peripheral allows us to connect the AVR-based system to serial
ports such as the COM port of the x86 IBM PC. Most of the AVR family members come with
the IC and SPI buses and some of them have USB or CAN bus as well.
AVR family overview
AVR can be classified into four groups: Classic, Mega, Tiny, and special purpose.
Classic AVR (AT90Sxxxx)
This is the original AVR chip, which has been replaced by newer AVR chips. Table 2 shows
some members of the Classic AVR that are not recommended for new designs.

Mega AVR (ATmegaxxxx)

These are powerful microcontrollers with more than 120 instructions and lots of different
peripheral capabilities, which can be used in different designs. Some of their characteristics are
as follows:
• Program memory: 4K to 256K bytes
• Package: 28 to 100 pins
• Extensive peripheral set
• Extended instruction set: They have rich instruction sets.

Tiny AVR (ATtinyxxxxx)

As its name indicates, the microcontrollers in this group have less instructions and smaller
packages in comparison to mega family. You can design systems with low costs and power
consumptions using the Tiny AVRS. Some of their characteristics are as follows:
• Program memory: IK to 8K bytes
• Package: 8 to 28 pins
• Limited peripheral set
 • Limited instruction set: The instruction sets are limited. For example, some of them do
not have the multiply instruction.

Special purpose AVR

The ICs of this group can be considered as a subset of other groups, but their special capabilities
are made for designing specific applications. Some of the special capabilities are: USB
controller, CAN controller, LCD controller, Zigbee, Ethernet controller, FPGA, and advanced
PWM.

AVR product number scheme

All of the product numbers start with AT, which stands for Atmel. Now, look at the number
located at the end of the product number, from left to right, and find the biggest number that is
a power of 2. This number most probably shows the amount of the microcontroller's ROM. For
example, in ATmega1280 the biggest power of 2 that we can find is 128; so it has 128K bytes
of ROM. In ATtiny44, the amount of memory is 4K, and so on. Although this rule has a few
exceptions such as AT90PWM216, which has 16K of ROM instead of 2K, it works in most of
the cases.
Other microcontrollers
There are many other popular 8-bit microcontrollers besides the AVR chip. Among them are
the 8051, HCS08, PIC, and Z8. The AVR is made by Atmel Corp, as seen in Table 6 Microchip
produces the PIC family. Freescale (formerly Motorola) makes the HCS08 and many of its
variations. Zilog produces the Z8 microcontroller. The 8051 family is made by Intel and a
number of other compa- nies. To contrast the ATmega32 with the 8052 chip and PIC, examine
Table 7.
For a comprehensive treatment of the 8051, HCS12, and PIC microcon- trollers, see "The 8051
Microcontroller and Embedded Systems," "HCS12 Microcontroller and Embedded Systems,"
and "PIC Microcontroller and Embedded Systems" by Mazidi, et al.
Comparison between Von-Neumann and Harvard Architecture

Every microprocessor must have memory space to store program (code) and data. While code
provides instructions to the CPU, the data provides the information to be processed. The CPU
uses buses (wire traces) to access the code ROM and data RAM memory spaces. The early
computers used the same bus for accessing both the code and data. Such an architecture is
commonly referred to as von Neumann (Princeton) architecture. That means for von Neumann
computers, the process of accessing the code or data could cause them to get in each other's
way and slow down the processing speed of the CPU, because each had to wait for the other
to finish fetching. To speed up the process of program execution, some CPUs use what is
called Harvard architecture. In Harvard architecture, we have separate buses for the code and
data memory. See Figure 0-20. That means that we need four sets of buses: (1) a set of data
buses for carrying data into and out of the CPU, (2) a set of address buses for accessing the
data, (3) a set of data buses for carrying code into the CPU, and (4) an address bus for accessing
the code. See Figure 0-20. This is easy to implement inside an IC chip such as a microcontroller
where both ROM code and data RAM are internal (on-chip) and distances are on the micron
and millimeter scale. But implementing Harvard architecture for systems such as x86 IBM
PC-type computers is very expensive because the RAM and ROM that hold code and data are
external to the CPU. Separate wire traces for data and code on the motherboard will make the
board large and expensive. For example, for a Pentium microprocessor with a 64-bit data bus
and a 32-bit address bus we will need about 100 wire traces on the motherboard if it is von
Neumann architecture (96 for address and data, plus a few others for control signals of read
and write and so on). But the number of wire traces will double to 200 if we use Harvard
architecture. Harvard architecture will also necessitate a large number of pins coming out of
the microprocessor itself. For this reason, you do not see Harvard architecture implemented in
the world of PCs and workstations. This is also the reason that microcontrollers such as AVR
use Harvard architecture internally, but they still use von Neumann architecture if they need
external memory for code and data space. The von Neumann architecture was developed at
Princeton University, while the Harvard architecture was the work of Harvard University.
 The following table highlights the major differences between Von Neumann and Harvard
Architecture –

Basis of Von Neumann Harvard Architecture

Comparison

The Von Neumann architecture is a The Harvard Architecture is the current

style of computer architecture that is design standard, and it features RAM and
Definition
straightforward and makes use of a ROM that are kept completely independent.
single memory connection.

The layout is straightforward and When compared to the Von Neumann

makes use of the same path to both architecture, this design is more complicated
Design
store data and take instructions. because it utilises separate connections for
RAM and ROM.

When compared to Harvard When compared to the Von Neumann

Architecture, the hardware Architecture, the Harvard Architecture
Hardware
requirements are significantly lower. places a greater emphasis on the use of
hardware.

In comparison to the Harvard Harvard Architecture is faster than the

Architecture, the speeds of the others. A computer modelled are
Speed processors are significantly lower. significantly lower. after the Harvard
Architecture calls for an increase in the
available space.

When compared to the Harvard In Harvard Architecture, the requirement for

Architecture computers, the Von the actual space is increased.
Physical
Neumann computers have a smaller
space
footprint in terms of the required
amount of physical space.

Because the memory and the Because the instruction memory and the
Internal programmes share the same space, data memory cannot share the same space,
memory there is no unused space in the internal some of Harvard's internal memory is going
memory. to waste somewhere.

The instructions for running can either Due to the fact that the input and the
be taken from the programme that has programme instructions that are stored in
Running
been stored or they can be given the programme are taken simultaneously,
Instructions
explicitly. As a result, the two cannot the running instructions are somewhat
be considered together. complicated and somewhat slow.

Steps followed by CPU in instruction execution.

Instruction Execution
The CPU executes each instruction in a series of small steps. Roughly speaking, the steps are
as follows:
1. Fetch the next instruction from memory into the instruction register.
2. Change the program counter to point to the following instruction.
3. Determine the type of instruction just fetched.
4. If the instruction uses a word in memory, determine where it is.
5. Fetch the word, if needed, into a CPU register.
6. Execute the instruction.
7. Go to step 1 to begin executing the following instruction.
This sequence of steps is frequently referred to as the fetch-decode-execute cycle. It is central
to the operation of all computers.

Pipelining
It has been known for years that the actual fetching of instructions from memory is a major
bottleneck in instruction execution speed. To alleviate this problem, computers going back
at least as far as the IBM Stretch (1959) have had the ability to fetch instructions from memory
in advance, so they would be there when they were needed. These instructions were stored in
a special set of registers called the prefetch buffer. This way, when an instruction was needed,
it could usually be taken from the prefetch buffer rather than waiting for a memory read to
complete.
In effect, prefetching divides instruction execution into two parts: fetching and actual
execution.

The concept of a pipeline carries this strategy much further. Instead of being divided into only
two parts, instruction execution is often divided into many (often a dozen or more) parts, each
one handled by a dedicated piece of hardware, all of which can run in parallel. Figure 2-4(a)
illustrates a pipeline with five units, also called stages.
Stage 1 fetches the instruction from memory and places it in a buffer until it is needed. Stage
2 decodes the instruction, determining its type and what operands it needs. Stage 3 locates and
fetches the operands, either from registers or from memory. Stage 4 actually does the work of
carrying out the instruction, typically by running the operands through the data path of Fig. 2-
2. Finally, stage 5 writes the result back to the proper register.

In Fig. 2-4(b) we see how the pipeline operates as a function of time. During clock cycle 1,
stage S1 is working on instruction 1, fetching it from memory. During cycle 2, stage S2 decodes
instruction 1, while stage S1 fetches instruction 2. During cycle 3, stage S3 fetches the operands
for instruction 1, stage S2 decodes instruction 2, and stage S1 fetches the third instruction.
During cycle 4, stage S4 executes instruction 1, S3 fetches the operands for instruction 2, S2
decodes instruction 3, and S1 fetches instruction 4. Finally, in cycle 5, S5 writes the result of
instruction 1 back, while the other stages work on the following instructions.
Let us consider an analogy to clarify the concept of pipelining. Imagine a cake factory in which
the baking of the cakes and the packaging of the cakes for shipment are separated. Suppose
that the shipping department has a long conveyor belt with five workers (processing units) lined
up along it. Every 10 sec (the clock cycle), worker 1 places an empty cake box on the belt. The
box is carried down to worker 2, who places a cake in it. A little later, the box arrives at worker
3’s station, where it is closed and sealed. Then it continues to worker 4, who puts a label on the
box. Finally, worker 5 removes the box from the belt and puts it in a large container for later
shipment to a supermarket. Basically, this is the way computer pipelining works, too: each
instruction (cake) goes through several processing steps before emerging completed at the far
end.
Getting back to our pipeline of Fig. 2-4, suppose that the cycle time of this machine is 2 ns.
Then it takes 10 ns for an instruction to progress all the way through the five-stage pipeline. At
first glance, with an instruction taking 10 ns, it might appear that the machine can run at 100
MIPS, but in fact it does much better than this. At every clock cycle (2 ns), one new instruction
is completed, so the actual rate of processing is 500 MIPS, not 100 MIPS.
Pipelining allows a trade-off between latency (how long it takes to execute an instruction), and
processor bandwidth (how many MIPS the CPU has). With a cycle time of T nsec, and n stages
in the pipeline, the latency is nT ns because each instruction passes through n stages, each of
which takes T ns. Since one instruction completes every clock cycle and there are 109 /T clock
cycles/second, the number of instructions executed per second is 109 /T. For example, if T = 2
ns, 500 million instructions are executed each second. To get the number of MIPS, we have to
divide the instruction execution rate by 1 million to get (109 /T)/106 = 1000/T MIPS.
Theoretically, we could measure instruction execution rate in BIPS instead of MIPS, but
nobody does that, so we will not either.
PRIMARY MEMORY
The memory is that part of the computer where programs and data are stored. Some computer
scientists (especially British ones) use the term store or storage rather than memory, although
more and more, the term ‘‘storage’’ is used to refer to disk storage. Without a memory from
which the processors can read and write information, there would be no stored-program digital
computers.
Primary storage is a key component of a computer system that enables it to function. Primary
storage includes random access memory (RAM), read only memory (ROM), cache and flash
memory. Each of these have different uses within the computer.
Primary storage (also known as main memory) is the component of the computer that holds
data, programs and instructions that are currently in use.

Primary storage is located on the motherboard. As a result, data can be read from and written
to primary storage extremely quickly. This gives the processor fast access to the data and
instructions that the primary storage holds.
There are four types of primary storage:
• Read Only Memory (ROM)
• Random Access Memory (RAM)
• Flash Memory
• Cache Memory
The two main types of primary storage are ROM, which is non-volatile, and RAM, which is
volatile. Non-volatile memory keeps its contents even when the computer is switched off.
Volatile memory loses its contents when power is lost.
Primary storage is comparatively limited in size, especially when compared with secondary
storage. In a modern personal computer, primary storage is often around 4 GB in size.
Cache Memory
Cache Memory is a special very high-speed memory. It is used to speed up and synchronize
with high-speed CPU. Cache memory is costlier than main memory or disk memory but more
economical than CPU registers. Cache memory is an extremely fast memory type that acts as
a buffer between RAM and the CPU. It holds frequently requested data and instructions so that
they are immediately available to the CPU when needed. Cache memory is used to reduce the
average time to access data from the Main memory. The cache is a smaller and faster memory
that stores copies of the data from frequently used main memory locations. There are various
different independent caches in a CPU, which store instructions and data.

Levels of memory:
Level 1 or Register – It is a type of memory in which data is stored and accepted that are
immediately stored in CPU. Most commonly used register is accumulator, Program counter,
address register etc.
Level 2 or Cache memory – It is the fastest memory which has faster access time where data
is temporarily stored for faster access.
Level 3 or Main Memory – It is memory on which computer works currently. It is small in size
and once power is off data no longer stays in this memory.
Level 4 or Secondary Memory – It is external memory which is not as fast as main memory
but data stays permanently in this memory.
The performance of cache memory is frequently measured in terms of a quantity called Hit
ratio.
Hit ratio(H) = hit / (hit + miss) = no. of hits/total accesses
Miss ratio = miss / (hit + miss) = no. of miss/total accesses = 1 - hit ratio(H)
We can improve Cache performance using higher cache block size, and higher associativity,
reduce miss rate, reduce miss penalty, and reduce the time to hit in the cache.
Secondary memory
Secondary memory consists of all permanent or persistent storage devices, such as read-only
memory (ROM), flash drives, hard disk drives (HDD), magnetic tapes and other types of
internal/external storage media.
ROM (read-only memory)
ROM is a type of memory that does not lose its contents when the power is turned off. For this
reason, ROM is also called non- volatile memory. There are different types of read-only
memory, such as PROM, EPROM, EEPROM, Flash EPROM, and mask ROM. Each is
explained next.

PROM (programmable ROM) and OTP

PROM refers to the kind of ROM that the user can burn information into. In other words,
PROM is a user-programmable memory. For every bit of the PROM, there exists a fuse. PROM
is programmed by blowing the fuses. If the information burned into PROM is wrong, that
PROM must be discarded since its internal fuses are blown permanently. For this reason,
PROM is also referred to as OTP (one-time programmable). Programming ROM, also called
burning ROM, requires special equipment called a ROM burner or ROM programmer.

EPROM (erasable programmable ROM) and UV-EPROM

EPROM was invented to allow making changes in the contents of PROM after it is burned. In
EPROM, one can program the memory chip and erase it thou- sands of times. This is especially
necessary during development of the prototype of a microprocessor-based project. A widely
used EPROM is called UV-EPROM, where UV stands for ultraviolet. The only problem with
UV-EPROM is that erasing its contents can take up to 20 minutes. All UV-EPROM chips have
a window through which the programmer can shine ultraviolet (UV) radiation to erase the
chip's contents. For this reason, EPROM is also referred to as UV-erasable EPROM or simply
UV-EPROM.

To program a UV-EPROM chip, the following steps must be taken:

1. Its contents must be erased. To erase a chip, remove it from its socket on the system board
and place it in EPROM erasure equipment to expose it to UV radiation for 15-20 minutes.
2. Program the chip. To program a UV-EPROM chip, place it in the ROM burner (programmer).
To burn code or data into EPROM, the ROM burner uses12.5 volts or higher, depending on the
EPROM type. This voltage is referred to as Vpp in the UV-EPROM data sheet.
3. Place the chip back into its socket on the system board. As can be seen from the above steps,
not only is there an EPROM programmer (burner), but there is also separate EPROM erasure
equipment. The main problem, and indeed the major disadvantage of UV-EPROM, is that it
cannot be erased and programmed while it is in the system board. To provide a solution to this
problem, EEPROM was invented.

EEPROM (electrically erasable programmable ROM)

EEPROM has several advantages over EPROM, such as the fact that its method of erasure is
electrical and therefore instant, as opposed to the 20-minute erasure time required for UV-
EPROM. In addition, in EEPROM one can select which byte to be erased, in contrast to UV-
EPROM, in which the entire contents of ROM are erased. However, the main advantage of
EEPROM is that one can program and erase its contents while it is still in the system board.
It does not require physical removal of the memory chip from its socket. In other words, unlike
UV- EPROM, EEPROM does not require an external erasure and programming device. To
utilize EEPROM fully, the designer must incorporate the circuitry to program the EEPROM
into the system board. In general, the cost per bit for EEPROM is much higher than for UV-
EPROM.

Flash memory EPROM

Since the early 1990s, Flash EPROM has become a popular user-programmable memory chip,
and for good reasons. First, the erasure of the entire contents takes less than a second, or
one might say in a flash, hence its name, Flash memory. In addition, the erasure method is
electrical, and for this reason it is sometimes referred to as Flash EEPROM. To avoid confusion,
it is commonly called Flash memory. The major difference between EEPROM and Flash
memory is that when Flash memory's contents are erased, the entire device is erased, in contrast
to EEPROM, where one can erase a desired byte. Although in many Flash memories recently
made available the contents are divided into blocks and the erasure can be done block by block,
unlike EEPROM, Flash memory has no byte erasure option. Because Flash memory can be
programmed while it is in its socket on the system board, it is widely used to upgrade the BIOS
ROM of the PC. Some designers believe that Flash memory will replace the hard disk as a mass
storage medium.
This would increase the performance of the computer tremendously, since Flash memory is
semiconductor memory with access time in the range of 100 ns com- pared with disk access
time in the range of tens of milliseconds. For this to hap- pen, Flash memory's program/erase
cycles must become infinite, just like hard disks. Program/erase cycle refers to the number of
times that a chip can be erased and reprogrammed before it becomes unusable. At this time, the
program/erase cycle is 100,000 for Flash and EEPROM, 1000 for UV-EPROM, and infinite
for RAM and disks.

Mask ROM
Mask ROM refers to a kind of ROM in which the contents are programmed by the IC
manufacturer. In other words, it is not a user-programmable ROM. The term mask is used in
IC fabrication. Since the process is costly, mask ROM is used when the needed volume is high
(hundreds of thousands) and it is absolutely certain that the contents will not change. It is
common practice to use UV-EPROM or Flash for the development phase of a project, and only
after the code/data have been finalized is the mask version of the product ordered. The main
advantage of mask ROM is its cost, since it is significantly cheaper than other kinds of
ROM, but if an error is found in the data/code, the entire batch must be thrown away. It
must be noted that all ROM memories have 8 bits for data pins; therefore, the organization is
x8.
RAM (random access memory)
RAM memory is called volatile memory since cutting off the power to the IC results in the loss
of data. Sometimes RAM is also referred to as RAWM (read and write memory), in contrast to
ROM, which cannot be written to.
There are three types of RAM:
• static RAM (SRAM).
• NV-RAM (non-volatile RAM), and
• dynamic RAM (DRAM).
SRAM (static RAM)
Storage cells in static RAM memory are made of flip-flops and therefore do not require
refreshing in order to keep their data. This is in contrast to DRAM, discussed below

The problem with the use of flip-flops for storage cells is that each cell requires at least 6
transistors to build, and the cell holds only 1 bit of data. In recent years, the cells have been
made of 4 transistors, which still is too many. The use of 4-transistor cells plus the use of CMOS
technology has given birth to a high-capacity SRAM, but its capacity is far below DRAM.
Figure 0-11 shows the pin diagram for an SRAM chip.
NV-RAM (nonvolatile RAM)
Whereas SRAM is volatile, there is a new type of non-volatile RAM called NV-RAM. Like
other RAMS, it allows the CPU to read and write to it, but when the power is turned off the
contents are not lost. NV-RAM combines the best of RAM and ROM: the read and write ability
of RAM, plus the nonvolatility of ROM.
To retain its contents, every NV-RAM chip internally is made of the following components:
1. It uses extremely power-efficient (very low-power consumption) SRAM cells built out of
CMOS.
2. It uses an internal lithium battery as a backup energy source.
3. It uses an intelligent control circuitry. The main job of this control circuitry is to monitor the
Voc pin constantly to detect loss of the external power supply. If the power to the Vcc pin falls
below out-of-tolerance conditions, the control circuitry switches automatically to its internal
power source, the lithium battery. The internal lithium power source is used to retain the NV-
RAM contents only when the external power source is off.
It must be emphasized that all three of the components above are incorporated into a single IC
chip, and for this reason non-volatile RAM is a very expensive type of RAM as far as cost per
bit is concerned. Offsetting the cost, however, is the fact that it can retain its contents up to ten
years after the power has been turned off and allows one to read and write in exactly the same
way as SRAM. Table 0-7 shows some examples of SRAM and NV-RAM parts.

DRAM (dynamic RAM)

Since the early days of the computer, the need for huge, inexpensive read/write memory has
been a major preoccupation of computer designers. In 1970, Intel Corporation introduced the
first dynamic RAM (random access memory). Its density (capacity) was 1024 bits and it used
a capacitor to store each bit. Using a capacitor to store data cuts down the number of transistors
needed to build the cell; however, it requires constant refreshing due to leakage. This is in
contrast to SRAM (static RAM), whose individual cells are made of flip-flops. Since each bit
in SRAM uses a single flip-flop, and each flip-flop requires six transistors, SRAM has much
larger memory cells and consequently lower density. The use of capacitors as storage cells
in DRAM results in much smaller net memory cell size.
The advantages and disadvantages of DRAM memory can be summarized as follows. The
major advantages are high density (capacity), cheaper cost per bit, and lower power
consumption per bit.
The disadvantage is that it must be refreshed periodically because the capacitor cell loses its
charge; furthermore, while DRAM is being refreshed, the data cannot be accessed. This is in
contrast to SRAM's flip- flops, which retain data as long as the power is on, do not need to be
refreshed, and whose contents can be accessed at any time. Since 1970, the capacity of DRAM
has exploded. After the IK-bit (1024) chip came the 4K-bit in 1973, and then the 16K chip in
1976. The 1980s saw the introduction of 64K, 256K, and finally IM and 4M memory chips.
The 1990s saw 16M, 64M, 256M, and the beginning of 1G-bit DRAM chips. In the 2000s, 2G-
bit chips are standard, and as the fabrication process gets smaller, larger memory chips will be
rolling off the manufacturing line. Keep in mind that when talking about IC memory chips, the
capacity is always assumed to be in bits. Therefore, a IM chip means a 1-megabit chip and a
256K chip means a 256K-bit memory chip. However, when talking about the memory of a
computer system, it is always assumed to be in bytes.

Criteria for choosing a microcontroller

1. The first and foremost criterion in choosing a microcontroller is that it must meet the task at
hand efficiently and cost effectively. In analyzing the needs of a microcontroller-based project,
we must first see whether an 8-bit, 16-bit, or 32-bit microcontroller can best handle the
computing needs of the task most effectively. Among other considerations in this category are:
(a) Speed. What is the highest speed that the microcontroller supports?
(b) Packaging. Does it come in a DIP (dual inline package) or a QFP (quad flat package), or
some other packaging format? This is important in terms of space, assembling, and prototyping
the end product.
(c) Power consumption. This is especially critical for battery-powered products.
(d) The amount of RAM and ROM on the chip.
(e) The number of 1/O pins and the timer on the chip.
(f) Ease of upgrade to higher-performance or lower-power-consumption versions.
(g) Cost per unit. This is important in terms of the final cost of the product in which a
microcontroller is used. For example, some microcontrollers cost50 cents per unit when
purchased 100,000 units at a time.
2 The second criterion in choosing a microcontroller is how easy it is to develop products
around it. Key considerations include the availability of an assembler, a debugger, a code-
efficient C language compiler, an emulator, technical support, and both in house and outside
expertise. In many cases, third-party vendor (ie, a supplier other than the chip manufacturer)
support for the chip is as good as, if not better than, support from the chip manufacturer.
3. The third criterion in choosing a microcontroller is its ready availability in needed quantities
both now and in the future. For some designers this is even more important than the first two
criteria. Currently, of the leading 8-bit micro- controllers, the 8051 family has the largest
number of diversified (multiple source) suppliers. (Supplier means a producer besides the
originator of the microcontroller.) In the case of the 8051, which was originated by Intel, many
companies also currently produce the 8051.
Notice that Freescale Semiconductor (Motorola). Atmel. Zilog, and Microchip Technology
have all dedicated massive resources to ensure wide and timely availability of their products
because their products are stable, mature, and single sourced. In recent years, companies have
begun to sell Field-Programmable Gate Array (FPGA) and Application-Specific Integrated
Circuit (ASIC) libraries for the different microcontrollers.