EXPERIMENT-2
MUX AND DEMUX
REG.NO:211FA05142
NAME: BUSARAPU AKSHAY KUMAR
AIM: To implement the Verilog code and test bench in gate level modelling for the designing
and verifying mux and demux.
APPARATUS: Desktop with Xilinx Vivado software
THEORY:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output.
CODE FOR MUX 2:1 IN DATA LEVEL:
module mux2_1(output out,input i0,i1,s);
assign out=(~s&i0)|(s&i1);
endmodule
TEST BENCH:
module mux2_1_tb;
reg s,i0,i1;
wire out;
mux2_1 uut(out,i0,i1,s);
initial
begin
i0=0;i1=1;
s=0;
#5 s=1;
end
endmodule
THEORY:
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output
Y. The block diagram of 4x1 Multiplexer is shown in the following figure. One of these 4
inputs will be connected to the output based on the combination of inputs present at these two
selection lines.
CODE FOR MUX 4:1 IN DATA FLOW:
module mux4_1(output out,input i0,i1,i2,i3,s1,s0);
assign out=(~s1&~s0&i0)|(~s1&s0&i1)|(s1&~s0&i2)|(s1&s0&i3);
endmodule
TEST BENCH:
module mux4_1_tb;
wire out;
reg i0,i1,i2,i3,s1,s0;
mux4_1 uut(out,i0,i1,i2,i3,s1,s0);
initial
begin
i0=0;i1=1;i2=0;i3=1;
s1=0;s0=0;
#5 s1=0;s0=1;
#5 s1=1;s0=0;
#5 s1=1;s0=1;
end
endmodule
STIMULATION OUTPUT:
THEORY:
4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure. One of
these 4 inputs will be connected to the output based on the combination of inputs present at
these two selection lines.
CODE FOR MUX 8:1 USING 4:1 MUX AND 2:1 MUX :
module mux8_1r(output out,input i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2);
wire w1,w2;
mux4_1 (w1,i0,i1,i2,i3,s1,s2);
mux4_1 (w2,i4,i5,i6,i7,s1,s2);
mux2_1 (out,w1,w2,s0);
endmodule
TEST BENCH:
module mux8_1_tb;
reg i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;
wire out;
mux8_1r uut(out,i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2);
initial
begin
i0=0;i1=1;i2=0;i3=1;i4=0;i5=1;i6=0;i7=1;
s0=0;s1=0;s2=0;
#5 s0=0;s1=0;s2=1;
#5 s0=0;s1=1;s2=0;
#5 s0=0;s1=1;s2=1;
#5 s0=1;s1=0;s2=0;
#5 s0=1;s1=0;s2=1;
#5 s0=1;s1=1;s2=0;
#5 s0=1;s1=1;s2=1;
end
endmodule
STIMULATION OUTPUT:
1:4 Demultiplexer
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S0 and S1, the input be connected to one of the outputs.
module demux1to4(
input s0,s1,
input i,
output y0,y1,y2,y3
);
wire w1,w2;
and a1(y0,i,w1,w2);
and a2(y1,i,w1,s1);
and a3(y2,i,s0,w2);
and a4(y3,i,s0,s1);
not a5(w2,s1);
not a6(w1,s0);
endmodule
TESTBENCH:
module demux1to4tb(
);
reg i;
reg s0,s1;
wire y0,y1,y2,y3;
demux1to4 h1(.i(i),.s0(s0),.s1(s1),.y0(y0),.y1(y1),.y2(y2),.y3(y3));
initial
begin
i=1; s0=0; s1=0;
#100 i=1; s0=0; s1=1;
#100 i=1; s0=1; s1=0;
#100 i=1; s0=1; s1=1;
end
endmodule
STIMULATION OUTPUT:
1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S0, S1 and S2, the input will be
connected to one of these outputs. The block diagram of the 1×8 de-multiplexer are given
below.
DATA FLOW
module demux1to8data(
input i,s0,s1,s2,
output [0:7] y
);
assign y[0]=(~s0)&(~s1)&(~s2);
assign y[1]=(~s0)&(~s1)&(s2);
assign y[2]=(~s0)&(s1)&(~s2);
assign y[3]=(~s0)&(s1)&(s2);
assign y[4]=(s0)&(~s1)&(~s2);
assign y[5]=(s0)&(~s1)&(s2);
assign y[6]=(s0)&(s1)&(~s2);
assign y[7]=(s0)&(s1)&(s2);
endmodule
TEST BENCH
module demux1to8datatb(
);
reg i,s0,s1,s2;
wire [0:7]y;
demux1to8data h1(.i(i),.s0(s0),.s1(s1),.s2(s2),.y(y));
initial
begin
i=1; s0=0; s1=0; s2=0;
#100 i=1; s0=0; s1=0; s2=1;
#100 i=1; s0=0; s1=1; s2=0;
#100 i=1; s0=0; s1=1; s2=1;
#100 i=1; s0=1; s1=0; s2=0;
#100 i=1; s0=1; s1=0; s2=1;
#100 i=1; s0=1; s1=1; s2=0;
#100 i=1; s0=1; s1=1; s2=1;
$monitor($time,"i=%b,s0=%b,s1=%b,s2=%b,y=%b",i,s0,s1,s2,y);
end
endmodule
STIMULATION OUTPUT:
CONCLUSION:
output wave forms are checked with the help of their truth tables
