23CI301– COMPUTER ARCHITECTURE
Lecture : 4 hrs. / Week Internal Assessment: 40 Marks
Tutorial : - Final Examination: 60 Marks
Practical : - Credits: 3
Course Objective (s):
The purpose of learning this course is to
Understand the basic structure and operation of a digital computer.
Learn the operation of the arithmetic unit.
Gain knowledge on the operation of the memory systems and I/O interfaces.
Know in detail, the different types of components and design of control unit.
Assess the operations of various I/O devices, interfaces, and communication mechanisms.
Course Outcomes:
At the end of this course, learners will be able to:
CO1: Explain the organizational and architectural issues of a digital computer.
CO2: Illustrate the operation and design of Arithmetic and Logic Unit.
CO3: Infer the operations of various types of memory and different mechanisms to interface I/O devices.
CO4: Examine the basic components and design of the control unit and analyze the different types of
hazards in pipelined execution.
CO5: Analyze the working of I/O systems including interrupt handling, serial communication and DMA.
UNIT l FUNDAMENTALS OF COMPUTER SYSTEMS 9
Functional Units of a Digital Computer - Operation and Operands of Computer Hardware - Software Interface -
Translation from a High Level Language to Machine Language - Instruction Set Architecture - RISC and
CISCArchitectures - Addressing Modes - Performance Metrics - Power Wall - Amdahl's Law - Moore's Law-
Content Beyond the Syllabus:General System Architecture
UNIT ll ARITHMETIC OPERATIONS 9
Arithmetic Operations - Addition and subtraction of signed numbers - Design of fast adders -Multiplication of
positive numbers - Signed operand multiplication and fast multiplication - Integer division- Floating point and fixed
point operations-Content Beyond the Syllabus: Computer networks
UNIT lll MEMORYAND I/O 9
Types of Memories - Need for a hierarchical memory system - Cache memories - Memory Mapping –
ImprovingCache Performance - Virtual Memory - Memory Management Techniques - Accessing I/O devices –
ProgrammedInput/output - Interrupts - Direct Memory Access.
Content Beyond the Syllabus:Combinational circuit
UNIT lV BASIC PROCESSING AND ILP 9
Design Convention of a Processor - Building a Datapath and designing a Control Unit - Execution of a
CompleteInstruction - Hardwired and Micro programmed Control - Instruction Level Parallelism - Basic Concepts
ofPipelining - Pipelined Implementation of Datapath and Control Unit - Hazards - Structural, Data and
ControlHazards- Content Beyond the Syllabus: Digital logical circuit
UNIT V I/O ORGANIZATION 9
Input / Output devices – Peripheral Devices – IO Interfaces- Modes of Interrupts - Programmed Input/output
Interrupts – Interrupt Priorities – Serial Communication - Direct Memory Access- Buses - Interface circuits -
Standard I/O Interfaces (PCI, SCSI, and USB), IOP - CPU Communication.
Content Beyond the Syllabus: Map simplification
Learning Resources:
TEXT BOOK
1. William Stallings, ―Computer Organization and Architecture – Designing for Performance, 10th Edition,
Pearson Education,2016.
2. David A. Patterson and John L. Hennessy, ―Computer Organization and Design: The Hardware/Software
interface‖, 3rd Edition, Elsevier, 2005.
REFERENCES
1. Carl Hamacher, ZvonkoVranesic and SafwatZaky, ―Computer Organization and Embedded Systems, 6th
Edition, Tata McGraw Hill, 2017
2. John L. Hennessey, David A. Patterson, "Computer Architecture - A Quantitative Approach",Morgan
Kaufmann / Elsevier Publishers, 4th Edition, 2007.
Web Resources:
1. https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/
2. https://www.javatpoint.com/computer-organization-and-architecture-tutorial
POs
COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1 3 3 3 - - - - - - 2 1 3 3 3 -
CO2 3 3 3 - - - - - - 1 1 2 3 3 -
CO3 3 3 3 - - - - - - 1 1 2 3 3 -
CO4 3 3 3 - - - - - - 1 1 2 3 3 -
CO5 3 3 3 - - - - - - 2 1 3 3 3 -
CO 3 3 3 - - - - - - 1.00 1.00 2.00 3 3 -
Correlation levels: 1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High)
COURSE COORDINATOR HOD
