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Sequential Logic - Unit 3

The document covers various digital circuit concepts, including conversions between binary and Gray code, BCD to Excess-3, and flip-flops such as SR, J-K, D, and T types. It also discusses sequential circuits, registers, and counters, detailing their functions and differences. Additionally, it addresses state assignment and reduction techniques in digital design.

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18 views36 pages

Sequential Logic - Unit 3

The document covers various digital circuit concepts, including conversions between binary and Gray code, BCD to Excess-3, and flip-flops such as SR, J-K, D, and T types. It also discusses sequential circuits, registers, and counters, detailing their functions and differences. Additionally, it addresses state assignment and reduction techniques in digital design.

Uploaded by

ym9348
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 36

Binary to Gray Code Converter

1
G2

G3

G4

2
Gray to Binary

3
BCD(8421) to Excess-3

4
Problems
Prob. 1 Prob 2.

• If (a,b,c,d)= 1101, find f

Prob. 3.

5
BCD to 7-Sigment Display

6
Unit-3: Sequential Circuits

SR-LATCH with NOR gate

7
SR-LATCH with NAND gate

8
FLIP-FLOPs
Clocks Signals

9
SR-Flip FLOP

Characteristic Table
Excitation Table

Invalid

Invalid
10
J-K Flip Flop

Excitation Table
Characteristic Table

11
D-Flip Flop

Characteristic Table Characteristic Equation

Excitation Table

12
T-Flip Flop

Characteristic Table Characteristic Equation Q(t+1) = T Xor Q

Excitation Table

13
Race Around Condition
• In J-K Flip Flop, if J=K=1 and flip flop delay
tpdff<tpw
• Out-put changes multiple time
• Can be avoided by
tpw<tpdff<Tclk

14
Master-Slave Flip Flop

• At a time only one flip flop will work.

15
Problem
Prob. For the given circuit diagram, find state table and
State diagram

16
Clock Triggering

17
Difference Between Latch and Flip-
Flop
Flip-Flop Latch
Clock Signal is present Enable Signal is Present

Output depends on clock and In-put is monitored always


input Any input change-output
changes immediately
Designed using latches Designed using logic gates

18
Registers and Counters
• A register is a group of flip‐flops, each one of which shares a common clock and is
capable of storing one bit of information
• SISO, SIPO, PISO, PIPO
• A counter is essentially a register that goes through a predetermined sequence of
binary states.

Four‐bit shift register

19
Serial in parallel out
(SIPO)

• In put 1010
• Output after 3 clock pulses ( Ans-1111)

20
Parallel in serial out
(PISO)

A2 A1 A0

A3

Control Signal

21
Parallel in Parallel
out (PIPO)

IN OUT
SISO n n-1
SIPO n 0 Number of clock pulses
PISO 1 n-1
PIPO 1 0

22
Counters
• Asynchronous or Ripple
Counters
• Synchronous Counters

23
Toggle Modes

24
Binary Ripple Counters
3-Bit ripple up-counter
MOD-8 Counter

25
3-Bit ripple down-counter
Present State Next State
111 110
110 101
101 100
100 011
011 010
010 001
001 000
000 111

26
Up-Down Counter

• Up=1, Circuit will work as up counter


• Down =1, Circuit will work as down counter

27
MOD-10 or BCD Counter

28
29
Synchronous Counter
• All the flip-flops are applied with same clock pulse
• Faster
• Special counters-Ring Counter and Johnson counter

30
Ring Counter

ORI = Overriding Input

31
Johnson Counter

32
State Assignment and Reduction

Input Sequence

33
• States having same next state, and output for same input can be eliminated with
only on
• States of e and g are equivalent

34
35
36

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