KNOW
as
LISATA
NORT
SoUT UNINS
North South University
Departmentof Electrical &Computer Engineering
LAB REPORT- 05
Course Code: CSE 231L
Course Title: Digital Logic Lab
Section: 08
Lab Number: 05
Experimernt Name: Binary Adder, Subtractor and BCD Adder.
Binary Arithmetic
Experiment Date: 10 April, 2023
Date of Submission: 08 May, 2023
|Submittedby Group Number: 05
|Group members:
Name ID Obtained Mark Obtained Mark
Simulation (5] Lab Report [15]
1. Md. Rafawat Islam 2122343642
2. Sazid Hasan 2211513642
3. Joy Kumar Ghosh 22114244642
4. Syed Tashriful Alam 2212623042
5. Md. Nifat Hossain 2212923042
Course Instructor: Dr. Md. Abdur Razzak (Azz)
Submitted To: Pritthika Dhar
Experfments Name. Bnary Adder, Subtractor
and BCD Adder
onjetie concept of bínary Additon
-Undorstavnd the
and subtaction
- Loarm about Half and Full binary Adders.
tion and subtractfon
-Penfortm binary addi
usg IC 7433.
f BD addto
Undenstavd the concept
- dond fsmplerment a BCD
BCD adder using
IC 7483
Aparstus. 41t binary Adden.
2X IC 7493 2-input XOR gates.
- Quadruple
-|x IC 74z4 86 2-mput aND gates.
z408 Guadruple oR gates.
-lxIC adrple 2nput OR
7432 Qu
-Jxte
Trainer Boand.
-Wines .
alme Shot by Legend T.JOY
me GT NEO 2 2023 05 08 12:18
2
Theorty.
Dipftal computers peztortm a vanety of
ing tasks. Amang the
-proc ess
mzormatiomencoun tened ane the varrious
tered
functons encoun
anthynetic perrations. The most addftonbasie
o
operraton fs the
anithmetie manages
binarty dgits. Atderr
two
openation s . There ane
thes e additong? Adden and
of Alders Half
knds
tvo
AJer. ombfmfn g two Hals abers
Full buft
one fu 4dder fs
1s
Half Adden: coymbfnatfonal logfe
Half Adder fs a single -bit biary
Cincit that ad two mput bts?
reduces two
mumbers and Tt is aled
carty .
the sLm and the
Pt can only
half?adder becanse Pt
cannot handle ay
ary
bits and
add two
previeus stag es.
mput srom
Cary
The truth table for ha H-adderr is as
follows'
Inpt Qut put
A B Sum
Thenefo n, the logtea! espressfon fort the su
and canry outputs ae:
Suim AB
Canry= AB
The hafadder cincutt can bebo mplemevted using
two logie gates' an XOR gate fn the sum
output ard an AND gate fon the carny outpub.
The two fnptin bits ae connected to both ane
g4tes and the outputs of the two gates
the and carry bfts,tespectively.
A -Sum
B
Camy
4
Ful Addert:
Afull Adden fs comtiatonal logt
bgt cineuÍ t
that adds thneo singlb -bit bnary nmberts
Ci. e. three bits) and rod uces two output
bits: the sum and the canry. Vn Jike
a half adden, a fal odden Can
handle an
input carny from previous
stages
The thuth table fon a full -adderz fs
as follows:
Inpat eOutput
A B tanr Sum
Canryout
)
|
There fore, the logim! expresslon ton the
sum and catry output are.
Swn= A BO Carry n
Cattyut = AB+ Canyg (A B)
be fon plemented
he full adder cinuit can
usg thne loglc gates: two XoR OR getes
for the Swm output on
nd One
gate and oe AND gate for tte cany
output. he three ?nput bits etput
Connected o to
XoR gates,
the and the
connected to
o the XoR gates
produce
the OR and AND ga te to
Sum bits
bfs
(atiy arnd
the cary
A A9B
Sum
AB
alme Shot by Legend T.JOY
Cire uft Diagnar.
S
A
6
)2
13
ec B3
Catrght 2
A B B B B
3 8
K
Ic 7483
-GND
a 26699
C
7402N
7432 N 432N
AA3A A)
B4 B, BB)
1 38 6
(E=O
Canry IC 7483
tyrined GND
Figahe D.2-1: BiD AJder Cneutt
Experfmental Proced ure'
Bhary Adder Subtractor'.
1. Fírst, we select fowe Switches to represen
the bfts of nput A and another
four moe binary w itehes to represent
the bits of fnpat B.
2. They we select another switch tor
the mode chosen (Carny;n)
3- Then We
we construet the cincults
Accond ng tota the pfn details n the
eíncuft diagnan sectôn.
we choose foun LEDs to view
4.
‘.Then ED
the output sum andanother
fon the eutput cary.
5. Then test the cireu?t with
we
the data on table F.I.1.
gc) Adder:
covrplete Table F2 dnd
Table
1. First, we complete
F.2.2 for the BCD sUm
construct the cincuft
2. Then, we
shown In Fizute D.2-)
3 We use the rst adden output as
adder.
the Inpat o the secend
4.We buit the incut accondng o
to
the pm detfs showm fn cfreut D2
test to oreuft wpth
5 Then we F2 2.
the data fn Table
Stom laton
Atached
Experfmetal Data Table:
Pata (4-8t Bimary Adder-Subtac):
F.l.Eperfnenta!
Operatfen M B SeSs S S)
4+6
|001
|10
O||)
4-6 O|00
10)
15 45 0000
Table F-1:1
F2 Exper fnental ata (8cD Adder):
Ded'mal Binary Sun BcD Sum
Value K S, So
3
4
5
6
(2
13
14
16
18
19
Ta blo F.2J
oven flow Sum
Opena tfon A
Canny
9+0 O000 |001
9+1 O00) 0000
1001 O0[0 0001
9 +2
9t3 lo1 O0||
|00| O|00 001)
9+5 |00] Ol00
9t6 |00| Ollo O)01
9+7 00| Otlo
9+8 |00) |000
1001 |O00
Table E2-2
Resu/oi
Afer fmple mentaton of our cipcuits,
we test ft with the data table
F}1, F:2-); and we aet the exact
otput as the table.
Questfoys amd Answers (Q/A):
01- I, thfs exp enl ymertt we use XOR
gates forr the fnput of B to convent
fn the nst comy lementss and ther e
use the Mbit as carnyn to
convert the B to the se cond
coynpe ments
Tnuth Ta ble of xoR Grates:
Input Output
A
Accondimg to the truth table, when
the MÞft is?s 0, the fnputs of BB
wf) not change . And when the
wt)
is bputs
1,nputs of B
Invent. We kmo know that for the
sub triactot, we meed to tonvent
the negative numten to second
|2
tompl fment then We add and get
the eubtractor nes w/t. We USe Mbt
0od choice, 1ke O0for add
as a Mhho8d
and 1 fon subtractor When M
the fnput of B will mot chonge,
and the adder wil/ dd the
ninber. Whem M sis 1, the input
mes B
efB f) vernt, which
con vert into a first covplemed
And then, M b7t w{l! enter as cr
So that wi con vert into seo nd
And adden wl) then
complymen ts
add the MUn ber and show out
the ubta cto f es wlt .
02 SPyoulatfon a ttached
BO a dder cineui ts
03In out
Top Adder 1C wi)l take nput
ef A and B, add them , amd
give the tput wit
utput with a cary.
13
And the bottom Adder TIC wI) ta te
tHhe top adders output input,
amd avoth er fnput wi]/ be ollo
0000 In th's case, OR and AN D
gates w?)l buf ld loaic to decide
when to add
qdd oIlo. and oo00. Here
Wecan see that ?t the cany
output of the top Adder Ic
fs 1, ft wll add aio as fnput
fon the botton addert
dnother Ca se,ff Sa and Sg ane
C1? or S4 and S are 13 ft wil
add ol[lo as input fen the bottom
adder Tc he In othen cases, it
the nput for
will add 0000 as the
the bottom addep IC. hen the
bo ttom Adder Ic will gfve the
exact otput of BD Sum.
The principles beh nd BcD Sum
Sum and
From Oto 9,, Bna y
14
BCD Sum are the
to 19, the tho sayne
the Binarty Stm of 0-9; just
a carey bit 1 will be added betore
the Bcp Sum. BD f's Bfnary (oded
De' mal. Every bit of a Decimal
Dee'mal.
numten will re present a 4-bft
Froym |0 to l2,
Biaary nunber.
MSB is and SB ?sc O-9.
Sum fs the
That's why BCp
Cane as
the tront.
Discussion:
th's expenfment we undenstand
Thrangh of bimony addiiem
the con cept Half
and subtraction. We can
Bhnarty dders. We cam do
dnd Full
addtfon and subtractfoy by usng
thfs adder. We also learm the concept
of BD Sum n the fírst parts our
ire it Was
was unable
unable to do a subtrater
Later we fden tfed that the
Adder c was daaged 7hen we
teplace the Ic and get the
acCNate restt. In the second
parrt, we dont face any problemc
coyple te within the tfne.
In short we leaned atout the
adder and sudtractor eíncuits.
A0 @
BO
Cin O
TD Cout
A=40100 A3 A2 A1 A0
B7=0111 =B3 B2 B1 BO
Sum =4 +7= 11=1011
Carry =0
A1O
B1 @
Cin
DL -1011) Sum
A2 C
D @Cout
B2 G
Cin
Narne: Joy Kumar Ghosh
A3 O
D ID: 2211424642
Lab: 05
Group: 05
B3 O
Cin
D Cout
Apartmen ofElectrical &Computer Engineering, NSU DigitalLogic Design Lab
E. DataSheet:
Instructor's Signature:
Group: O5 Section: D8 Date: 03/04/2023
F.IExperimental data (4-bit Binary Adder-Subtractor):
- o S4
lS3 S2 S1
Operation M B C4
7+5
|00
4+6 0)00 0||0
0)00
9+11 001
15 + 15
7-5 00
4-6 0 )00
0010
11-2
1515
Table F.1.1
EEE211L/ETE211L Lab-5 Page 5 of6
FElectrical &Computer Engineering, NSU Digital Logle Design Lab
IExperinmental Data (BCD Adder):
Bìnary Sum BCD Sum
Decimal S
Value K Z Zo S S
0 0
1 0 0 0 0
0 0 1
3 0 0
0 0 1 0 0
0 0 1 0
0 0 1 0
6
1 1
7
0 0 0
9 0
10 0 0
0 0 1
11
12 0
0 1 1
13 o-o
1 1
14 0
1 1
15 0 1
16
1
1 0
17
0 0 1
18 1
1 1
0 0 1
19 1
Table F.2.1
Overflow Carry Sum
A B
Operation )00)
0000
9+0 0000/
9+1 |00|
0010
9+2 L00
9+3
9+4 100) O00
9+5
9+6
9+7 l00)
9+8
|006
l001
9+9
Table F.2.2
EEE21|LUETE21|L Lab-5 to/4/29 Page 6 of 6
Porus->1
