21EC63 VLSI DESIGN AND TESTING
Module 4 Part 1
Faults in digital circuits: Failures and faults, Modelling of faults, Temporary faults
FAILURE AND FAULTS
INTRODUCTION:
A failure is said to have occurred in a circuit or system if it deviates from its specified
behavior.A fault, on the other hand, is a physical defect that may or may not cause a failure.
A fault is characterized by its nature, value, extent, and duration. The nature of a fault can
be classified as logical or non logical. A logical fault causes the logic value at a point in a
circuit to become opposite to the specified value.Non logical faults include the rest of the
faults, such as the malfunction of the clock signal, power failure, and so forth.
The value of a logical fault at a point in the circuit indicates whether the fault creates fixed
or varying erroneous logical values.The extent of a fault specifies whether the effect of the
fault is localized or distributed.
A local fault affects only a single variable, whereas a distributed fault affects more than
on
When testing digital circuits, two distinct philosophies are commonly used:
1.Functional Testing: This approach involves performing a series of functional tests to
check whether the circuit produces the correct (fault-free) 0 or 1 output responses. It
doesn’t consider the circuit’s design details but focuses solely on correct outputs during
testing.
2.Fault Modelling: Here, we consider possible faults that may occur during the
manufacture of integrated circuits (ICs). We compute the circuit’s output with and without
each fault present. Specific tests are then designed to detect or rule out the presence of
particular faults. If none of the chosen faults is detected, the IC is considered fault-free
Terminology:
Fault: A physical defect in the circuit.
Error: The manifestation of a fault causing incorrect outputs.
Failure: Occurs when a circuit deviates from its specified behavior due to an error
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21EC63 VLSI DESIGN AND TESTING
MODELING OF FAULTS
Faults in a circuit may occur due to defective components, breaks in signal lines, lines
shortened to ground or power supply, short-circuiting of signal lines, excessive delays, and so
forth.Besides errors or ambiguities in design specifications, design rule violations, among
other things, also result in faults.
Faults in Digital Circuits:
The total faults encountered during the commissioning of subsystems of a mid-range
mainframe computer implemented using MSI (Medium Scale Integration); however, during
the system validation such faults constituted 44% of the total.
Poor designs may also result in hazards, races, or metastable flip-flop behavior in a circuit;
such faults manifest themselves as "intermittents" through- out the life of the circuit.
In general, the effect of a fault is represented by means of a model, which represents the change
the fault produces in circuit signals.
The fault models in use today are
Stuck-at fault
Bridging fault
Stuck-on and Stuck-open fault
Delay fault
Temporary fault
For the above fault models are explained in detailed:
1. STUCK AT FAULTS:
Stuck-at Fault (SAF) is a type of fault analysis in which a node/pin in a digital circuit is
assumed to be fixed at logic 0 or logic 1.
Stuck-at fault model is also called a permanent fault model because the faulty effect is
assumed to be permanent.
Stuck-at fault occurs in logic gates which results in one of the inputs or the output being
fixed to either a logic 0 (stuck-at 0) or logic 1 (stuck-at 1).
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21EC63 VLSI DESIGN AND TESTING
LOGIC 1 ( STUCK AT 1)
A-> Logic 0 , B-> Logic 1
NAND Logic Table
A B Y Y’
0 0 1 1
0 1 1 0
1 0 1 1
1 1 0 0
EXPLAINATION:
The most common model used for logical faults is the single stuck-at fault. It assumes that
a fault in a logic gate results in one of its inputs or the output being fixed to either a logic
0 (stuck-at-0) or a logic 1 (stuck-at-1).
Stuck-at-0 and stuck- at-1 faults are often abbreviated to s-a-0 and s-a-1, respectively, and
these abbreviations will be adopted here.
Let us consider a NAND gate with input A s-a-1. The NAND gate perceives the input A
as a 1 irrespective of the logic value placed on the input.
The output of the NAND gate in is 0 for the input pattern shown above, when the s-a-1
fault is present. The fault-free gate has an output of 1. Therefore, the pattern shown in can
be used as a test for the A input s-a-1, because there is a difference between the output of
the fault-free and the faulty gate.
The stuck-at model, often referred to as classical fault model, offers good representation
for the most common types of failures, for example, short-circuits (shorts) and open
circuits (opens) in many technologies.
Illustrates the CMOS (Complementary Metal Oxide Semiconductor) realization of a
NAND gate, the numbers 1, 2, 3, and 4 indicating places where opens have occurred.
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21EC63 VLSI DESIGN AND TESTING
2.BRIDGING FAULTS:
With the increase in the number or devices on the VLSI chips, the probability of shorts
between two or more signal lines has been significantly increased.
Unintended shorts between the lines form a class of permanent faults, known as bridging
faults.
It has been observed that physical defects in MOS (Metal Oxide Semiconductor) circuits
are manifested as bridging faults more than as any other type of fault.
Bridging faults can be categorized into three groups:
Input bridging, Feedback bridging, Non feedback bridging.
An input bridging fault corresponds to the shorting of a certain number of primary input
lines.
Feedback bridging fault occurs if there is a short between an output line to an input line.
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21EC63 VLSI DESIGN AND TESTING
A non feedback bridging fault identifies a bridging fault that does not belong to either of
the two previous categories.
From these definitions, it will be clear that the probability of two lines getting bridged is
higher if they are physically close to each other.
In general, a bridging fault in positive logic is assumed to behave as a wired-AND (where
0 is the dominant logic value), and a bridging fault in negative logic behaves as a wired-
OR (where I is the dominant logic value).
The presence of a feedback bridging fault can cause a circuit to oscillate or convert it into
a sequential circuit.
The probable bridging fault in this circuit (or in any other CMOS circuit) can be grouped
into four categories:
1.Metal polysilicon short (a in Figs. 1.8(a) and (b))
2. Polysilicon n-diffusion short (c.d in Figs. 1.8(a) and (b))
3. Polysilicon p-diffusion short (e,f in Figs. 1.8(a) and (b))
4. Metal polysilicon short (g in Figs. 1.8(a) and (b))
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21EC63 VLSI DESIGN AND TESTING
On the position of a break, that the gates of both transistors may float, in which case one
transistor may conduct and the other remain in a nonconducting state , this type of break
can be modeled as a stuck-at fault.
On the other hand, if two transistors with floating gates are permanently conducting, one
of them can be considered as stuck on.
If a transistor with a floating gate remains in a nonconducting state due to a signal line
break, the circuit will behave in a similar fashion as it does in the presence of the
integrate break b₂.
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21EC63 VLSI DESIGN AND TESTING
3.STUCK-ON AND STUCK-OPEN FAULTS
STUCK-ON FAULTS:
A stuck-on fault occurs when a transistor remains permanently turned on (conducting)
regardless of its input.
The faulty gate output is difficult to predict because the stuck-on transistor competes with
its complementary transistors for control of the output.
Sometimes this competition doesn’t lead to catastrophic failure, but it can disrupt normal
circuit behavior.
STUCK-OPEN FAULTS
A stuck-open fault creates an unintended high-impedance state on the output node of a
gate.
The faulty gate output remains open (disconnected) even when it should be driving a logic
value.
Stuck-open faults are modeled as additional non-classical faults alongside the standard
stuck-at faults.
4.DELAY FAULTS
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21EC63 VLSI DESIGN AND TESTING
Delay faults occur when a circuit is too slow to propagate signals through certain paths or
gates.
Even if the logic operations within the circuit are correct, the output may not be reached within
the allotted time due to delays.
Types:
Gate Delay Faults (GDF)
Path Delay Faults (PDF)
Transition Delay Faults
1.Gate Delay Faults (GDF):
GDFs occur due to variations in gate delays within a circuit.
When a gate’s delay is significantly different from the expected value, it can lead to
incorrect timing behavior.
These faults impact the propagation delay of signals through gates, affecting overall circuit
performance.
2.Path Delay Faults (PDF):
PDF involve delays along specific signal paths within a circuit.
A path may have longer or shorter delays than anticipated, leading to timing violations.
Detecting PDF is crucial for ensuring reliable operation, especially in high-speed designs.
3.Transition Delay Faults:
Transition delay faults occur during signal transitions (rising or falling edges).
These faults affect the timing between input and output transitions.
Detecting and mitigating transition delay faults is essential for maintaining correct circuit
behavior.
5.TEMPORARY FAULTS:
● Temporary faults are the faults or errors that occur unpredictably and temporarily affect
the VLSI or electronic circuits.
● Temporary faults are often referred to as intermittent or transient faults with the same
meaning.
● Transient faults are non-recurring temporary faults.
● They are not repairable because there is no physical damage to the hardware.
CAUSES OF TRANSIENT FAULTS:
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21EC63 VLSI DESIGN AND TESTING
● They are the major source of failures in semiconductor memory chips.
● They are usually caused by alpha-particle radiation or power supply fluctuation.
INTERMITTENT FAULT:
● Intermittent faults are recurring faults that reappear regularly.
● An intermittent fault in a circuit causes a circuit malfunction only if it is active; if it is
inactive, the circuit operates correctly.
● A circuit is said to be in a fault-active state if a fault present in the circuit is active.
● It is said to be in the fault-not-active state if a fault is present but inactive.
CAUSES OF THE INTERMITTENT FAULT:
● Due to loose connections, partially defective components, or poor designs.
● Faults also occur due to environmental conditions such as temperature, humidity, and
vibration.
● Intermittent depend on how well the system is protected from its physical environment
through shielding, filtering, and cooling.
VTU QUESTIONS
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