Embedded System Design
EC62
What is an Embedded System?
• An embedded system is an electronic/ electromechanical system
designed to perform a specific task.
• A typical embedded system contains a chip controller which is the
master brain.
• The controller can be a microprocessor, microcontroller, FPGA, DSP,
ASIC /ASSP.
Core of the Embedded System
Core of the embedded system falls into any one of the following
categories:
➢ General Purpose and Domain Specific Processors
•Microprocessors
•Microcontrollers
•DSPs
➢ Application Specific Integrated Circuits
➢ Commercial off-the shelf Components (COTS)
GENERAL PURPOSE AND DOMAIN SPECIFIC
PROCESSOR
• Almost 80% of the embedded systems are processor/ controller based.
• The processor may be microprocessor or a microcontroller or digital
signal processor, depending on the domain and application.
Microprocessor
• is a silicon chip representing a Central Processing Unit (CPU),
• which is capable of performing arithmetic as well as logical operations
• according to a pre-defined set of Instructions,
• which is specific to the manufacturer In general the CPU contains the
Arithmetic and Logic Unit (ALU), Control Unit and Working registers
• Microprocessor is a dependent unit and it requires the combination of
other hardware like Memory, Timer Unit, and Interrupt Controller etc
for proper functioning.
• Intel developed the first Microprocessor unit Intel 4004, a 4 bit
processor which was released in Nov 1971 ·
Developers of microprocessors.
• Intel – Intel 4004
• Intel – Intel 4040.
• Intel – Intel 8008
• Intel – Intel 8080
• Motorola – Motorola 6800.
• Intel – Intel 8085
• Zilog - Z80
GPP vs ASIP
• General Purpose Processor or GPP is a processor designed for general
computational tasks
• GPPs are produced in large volumes and targeting the general market.
Due to the high volume production, the per unit cost for a chip is low
compared to ASIC or other specific ICs
• A typical general purpose processor contains an Arithmetic and Logic
Unit (ALU) and Control Unit (CU)
• Application Specific Instruction Set processors (ASIPs) are processors
with architecture and instruction set optimized to specific
domain/application requirements like Network processing,
Automotive, Telecom, media applications, digital signal processing,
control applications etc.
• ASIPs fill the architectural spectrum between General Purpose
Processors and Application Specific Integrated Circuits (ASICs)
• The need for an ASIP arises when the traditional general purpose
processor are unable to meet the increasing application needs
• ASIPs incorporate a processor and on-chip peripherals, demanded by
the application requirement, program and data memory
Microcontroller:
A highly integrated silicon chip containing
• a CPU,
• Scratch pad RAM,
• Special and General purpose Register Arrays,
• On Chip ROM/FLASH memory for program storage,
• Timer and Interrupt control units and
• Dedicated I/O ports
Microcontrollers can be considered as a super set of Microprocessors
• Microcontroller can be general purpose (designed for generic
applications and domains) or application specific (Automotive AVR
from Atmel Corporation. Designed specifically for automotive
applications)
• Since a microcontroller contains all the necessary functional blocks for
independent working, they found greater place in the embedded
domain in place of microprocessors
• Microcontrollers are cheap, cost effective and are readily available in
the market
Digital Signal Processors (DSPs)
• Powerful special purpose 8/16/32 bit microprocessors designed
specifically to meet the computational demands and power constraints
of today's embedded audio, video, and communications applications
• Digital Signal Processors are 2 to 3 times faster than the general
purpose microprocessors in signal processing applications
• DSPs implement algorithms in hardware which speeds up the
execution whereas general purpose processors implement the
algorithm in firmware and the speed of execution depends primarily
on the clock for the processors
• DSP can be viewed as a microchip designed for performing high speed
A typical Digital Signal Processor incorporates the following key units
Program Memory
Data Memory
Computational Engine
I/O Unit
Audio video signal processing, telecommunication and multimedia
applications are typical examples where DSP is employed
• The terms Harvard and Von-Neumann refers to the processor
architecture design.
• Microprocessors/controllers based on the common bus for fetching
both instructions stored in a common main memory Von-Neumann
architecture shares a single and data.
• Program instructions and data are Microprocessors/controllers based
on the Harvard architecture will have separate data bus and instruction
bus. This allows the data transfer and program fetching to occur
simultaneously on both buses
• With Harvard architecture, the data memory can be read and written
while the program memory is being accessed. These separated data
memory and code memory buses allow one instruction to execute
while the next instruction is fetched (“Pre-fetching”)
Big-endian V/s Little-endian processors
• Endianness specifies the order in which the data is stored in the
memory by processor operations in a multi byte system (Processors
whose word size is greater than one byte).
• Suppose the word length is two byte then data can be stored in
memory in two different ways Higher order of data byte at the higher
memory and lower order of data byte at location just below the higher
memory Lower order of data byte at the higher memory and higher
order of data byte at location just below the higher memory
• Little-endian means the lower-order byte of the data is stored in
memory at the lowest address, and the higher-order byte at the highest
address. (The little end comes first)
• Big-endian means the higher-order byte of the data is stored in
memory at the lowest address, and the lower-order byte at the highest
address. (The big end comes first.)
Load Store Operation & Instruction Pipelining
• The RISC processor instruction set is orthogonal and it operates on registers.
• The memory access related operations are performed by the special instructions
load and store.
• If the operand is specified as memory location, the content of it is loaded to a
register using the load instruction.
• The instruction store stores data from a specified register to a specified memory
location
The conventional instruction execution by the processor follows the fetch-decode-execute sequence
•The “fetch” part fetches the instruction from program memory or code memory and
•the decode part decodes the instruction to generate the necessary control signals
•The execute stage reads the operands, perform ALU operations and stores the result.
• In conventional program execution, the fetch and decode operations are performed in sequence
During the decode operation the memory address bus is available and if it possible to effectively utilize it for
an instruction fetch, the processing speed can be increased
In its simplest form instruction pipelining refers to the overlapped execution of instructions
Application Specific Integrated Circuit (ASIC)
• A microchip designed to perform a specific or unique application.
• It is used as replacement to conventional general purpose logic chips.
• ASIC integrates several functions into a single chip and thereby reduces the system
development cost
• Most of the ASICs are proprietary products.
• As a single chip, ASIC consumes very small area in the total system and thereby
helps in the design of smaller systems with high capabilities/functionalities.
• ASICs can be pre-fabricated for a special application or it can be custom fabricated
by using the components from a re-usable “building block” library of components for
a particular customer application
• Fabrication of ASICs requires a non-refundable initial investment (Non Recurring
Engineering (NRE) charges) for the process technology and configuration expenses
• If the Non-Recurring Engineering Charges (NRE) is born by a third party and the
Application Specific Integrated Circuit (ASIC) is made openly available in the
market, the ASIC is referred as Application Specific Standard Product (ASSP)
• The ASSP is marketed to multiple customers just as a general-purpose product , but
to a smaller number of customers since it is for a specific application.
• Some ASICs are proprietary products , the developers are not interested in
revealing the internal details.
Commercial off the Shelf Component (COTS)
• Commercial off-the-shelf (COTS) product is one which is used “as-is”
• COTS products are designed in such a way to provide easy integration and
interoperability with existing system components
Typical examples for the COTS hardware unit are
• High performance, high frequency microwave electronics (2 to 200 GHz),
• High bandwidth analog-to-digital converters,
• Devices and components for operation at very high temperatures,
• Electro-optic IR imaging arrays,
• UV/IR Detectors etc
A COTS component in turn contains a General Purpose Processor (GPP) or
Application Specific Instruction Set Processor (ASIP) or Application Specific
Integrated Chip (ASIC)/Application Specific Standard Product (ASSP) or
Programmable Logic Device (PLD)
PRO
S
• Everything will be readily supplied by the COTs manufacturer.
• The major advantage of using COTS is that they are readily available in the
market, cheap and a developer can cut down his/her development time to a great
extend.
• There is no need to design the module yourself and write the firmware .
CON
S
• The major problem faced by the end-user is that there are no operational and
manufacturing standards.
• The major drawback of using COTs component in embedded design is that the
manufacturer may withdraw the product or discontinue the production of the COTs
at any time if rapid change in technology
• This problem adversely affect a commercial manufacturer of the embedded
system which makes use of the specific COTs
Memory
• Memory is an important part of an embedded system.
• The memory used in embedded system can be either Program Storage Memory
(ROM) or Data memory (RAM) Certain Embedded processors/controllers contain
built in program memory and data memory and this memory is known as on-chip
memory
• Certain Embedded processors/controllers do not contain sufficient memory
inside the chip and requires external memory called off-chip memory or external
memory.
Masked ROM (MROM):
• One-time programmable memory. Uses hardwired technology for storing data.
• The device is factory programmed by masking and metallization process according to
the data provided by the end user.
• The primary advantage of MROM is low cost for high volume production.
• MROM is the least expensive type of solid state memory.
• Different mechanisms are used for the masking process of the ROM, like
•Creation of an enhancement or depletion mode transistor through channel
implant
•By creating the memory cell either using a standard transistor or a high
threshold transistor.
•The limitation with MROM based firmware storage is the inability to modify
the device firmware against firmware upgrades. The MROM is permanent in bit
storage, it is not possible to alter the bit information
Programmable Read Only Memory (PROM) / (OTP) :
• It is not pre-programmed by the manufacturer
• The end user is responsible for Programming these devices.
• PROM/OTP has nichrome or polysilicon wires arranged in a matrix, these
wires can be functionally viewed as fuses.
• It is programmed by a PROM programmer which selectively burns the fuses
according to the bit pattern to be stored.
• Fuses which are not blown/burned represents a logic “1” where as fuses which are
blown/burned represents a logic “0”.
• The default state is logic “1”. OTP is widely used for commercial production of
embedded systems whose proto-typed versions are proven and the code is
finalized.
• It is a low cost solution for commercial production. OTPs cannot be
reprogrammed.
Erasable Programmable Read Only Memory (EPROM):
• Erasable Programmable Read Only (EPROM) memory gives the flexibility to
re-program the same chip.
• During development phase , code is subject to continuous changes and using an
OTP is not economical.
• EPROM stores the bit information by charging the floating gate of an FET. Bit
information is stored by using an EPROM Programmer, which applies high
voltage to charge the floating gate.
• EPROM contains a quartz crystal window for erasing the stored information.
• If the window is exposed to Ultra violet rays for a fixed duration, the entire
memory will be erased Even though the EPROM chip is flexible in terms of re-
programmability, it needs to be taken out of the circuit board and needs to be
put in a UV eraser device for 20 to 30 minutes
Electrically Erasable Programmable Read Only Memory (EEPROM):
• Erasable Programmable Read Only (EPROM) memory gives the flexibility to re-
program the same chip using electrical signals
• The information contained in the EEPROM memory can be altered by using
electrical signals at the register/Byte level
• They can be erased and reprogrammed within the circuit
• These chips include a chip erase mode and in this mode they can be erased in a
few milliseconds It provides greater flexibility for system design
• The only limitation is their capacity is limited when compared with the standard
ROM (A few kilobytes).
Program Storage Memory –
• FLASH FLASH memory is a variation of EEPROM technology.
• FLASH is the latest ROM technology and is the most popular ROM technology
used in today’s embedded designs
• It combines the re-programmability of EEPROM and the high capacity of standard
ROMs
• FLASH memory is organized as sectors (blocks) or pages FLASH memory stores
information in an array of floating gate MOSFET transistors
The erasing of memory can be done at sector level or page level without
affecting the other sectors or pages
Each sector/page should be erased before re-programming
The typical erasable capacity of FLASH is of the order of a few 1000 cycles.
Read-Write Memory/Random Access Memory (RAM)
• RAM is the data memory or working memory of the controller/processor
• RAM is volatile, meaning when the power is turned off, all the contents are
destroyed
• RAM is a direct access memory, meaning we can access the desired memory
location directly without the need for traversing through the entire memory
locations to reach the desired memory position (i.e. Random Access of memory
location)
Static RAM (SRAM):
• Static RAM stores data in the form of Voltage.
• They are made up of flip-flops
• In typical implementation, an SRAM cell (bit) is realized using 6 transistors (or 6
MOSFETs).
• Four of the transistors are used for building the latch (flip-flop) part of the memory
cell and 2 for controlling the access.
• Static RAM is the fastest form of RAM available.
• SRAM is fast in operation due to its resistive networking and switching capabilities
Non Volatile RAM (NVRAM):
•Random access memory with battery backup
•It contains Static RAM based memory and a minute battery for providing supply
to the memory in the absence of external power supply
•The memory and battery are packed together in a single package
•NVRAM is used for the non volatile storage of results of operations or for setting
up of flags etc
•The life span of NVRAM is expected to be around 10 years
Memory Shadowing
Generally the execution of a program or a configuration from a Read Only Memory
(ROM) is very slow
(120 to 200 ns) compared to the execution from a random access memory (40 to 70 ns).
From the timing parameters it is obvious that RAM access is about three times as fast as
ROM access.
Shadowing of memory is a technique adopted to solve the execution speed problem in
processor-based systems.
In personal computer systems BIOS stores the hardware configuration information like
the address assigned for various serial ports and other non-plug ‘n’ play devices, etc.
Usually it is read and the system is configured according to it during system boot up and
it is time consuming.
The manufactures included a RAM behind the logical layer of BIOS at its
same address as a shadow to the BIOS and the first step that happens during
the boot up is copying the BIOS to the shadowed RAM and write protecting
the RAM then disabling the BIOS reading.
RAM is volatile and it cannot hold the configuration data which is copied
from the BIOS when the power supply is switched off. Only a ROM can hold
it permanently. But for high system performance it should be accessed from a
RAM instead of accessing from a ROM.
Sensors & Actuators:
• Embedded system is in constant interaction with the real world
• Controlling/monitoring functions executed by the embedded system is achieved in
accordance with the changes happening to the Real World.
• The changes in the system environment or variables are detected by the sensors
connected to the input port of the embedded system.
• If the embedded system is designed for any controlling purpose, the system will
produce some changes in controlling variable to bring the controlled variable to the
desired value.
• It is achieved through an actuator connected to the out port of the embedded system.
Sensor:
A transducer device which converts energy from one form to another
for any measurement or control purpose. Sensors acts as input device
Actuator:
A form of transducer device (mechanical or electrical) which converts signals
to corresponding physical action (motion). Actuator acts as an output device
Light Emitting Diode (LED):
• Light Emitting Diode (LED) is an output device for visual indication in any
embedded system
• LED can be used as an indicator for the status of various signals or situations.
• Typical examples are indicating the presence of power conditions
like Device ON, Battery low or Charging of battery for a battery operated handheld
embedded devices
• LED is a p-n junction diode and it contains an anode and a cathode.
• For proper functioning of the LED, the anode of it should be connected to +ve terminal
of the supply voltage and cathode to the –ve terminal of supply voltage
• The current flowing through the LED must limited to a value below the maximum
current that it can conduct.
• A resister is used in series between the power supply and the resistor to limit the
current through the LED
7-Segment LED Display
• The 7 – segment LED display is an output device for displaying alpha numeric
characters
• It contains 8 light-emitting diode (LED) segments arranged in a special form.
• Out of the 8 LED segments, 7 are used for displaying alpha numeric characters
• The LED segments are named a to g and the decimal point LED segment is named
as DP
• The LED Segments A to G and DP should be lit accordingly to display numbers
and characters
• The 7 – segment LED displays are available in two different configurations,
namely; Common anode and Common cathode
In the Common anode configuration, the anodes of the 8 segments are connected
commonly whereas in the Common cathode configuration, the 8 LED segments share
a common cathode line
Based on the configuration of the 7 – segment LED unit, the LED segment anode or
cathode is connected to the Port of the processor/controller in the order a segment to
the Least significant port Pin and DP segment to the most significant Port Pin.
The current flow through each of the LED segments should be limited to the
maximum value supported by the LED display unit
The typical value for the current falls within the range of 20mA
The current through each segment can be limited by connecting a current limiting
resistor to the anode or cathode of each segment
Communication Interface
• Communication interface is essential for communicating with various subsystems of
the embedded system and with the external world
• The communication interface can be viewed in two different perspectives; namely;
1. Device/board level communication interface (Onboard Communication Interface)
2. Product level communication interface (External Communication Interface)
• Embedded system is a combination of different types of components on a PCB.
• The communication channel that interconnects the various components within an
embedded system is called Device/board level communication interface (Onboard
Communication Interface)
Serial interfaces like I2C, SPI, UART, 1-Wire, etc and parallel bus interface are
examples of ‘Onboard Communication Interface’.
Some embedded systems are self-contained units and they don’t require any
interaction and data transfer with other sub-systems or external world.
On the other hand, certain embedded systems may be a part of a large distributed
system and they require interaction and data transfer between various devices and
sub-modules.
The ‘Product level communication interface’ (External Communication Interface) is
responsible for data transfer between the embedded system and other devices or
modules.
The external communication interface can be either a wired media or a wireless
media and it can be a serial or a parallel interface. Infrared (IR), Bluetooth (BT),
Wireless LAN (Wi-Fi), Radio Frequency waves (RF), GPRS/3G/4GLTE, etc. are
examples for wireless communication interface.
Serial Peripheral Interface
• The serial peripheral interface was introduced by Motorola and is the
simplest synchronous communication protocol in general use.
• The only problem is that it is not a fixed standard like I²C. There are
plenty of options within “standard” SPI and innumerable variations that
go beyond this.
• You must always read the data sheet closely for a device that uses SPI and
ensure that you understand the details of the protocol precisely.
• One device is the master and the other the slave. The master provides the clock for both
devices and a signal to select (enable) the slave
The concept of SPI is based on
• two shift registers, one in each device, which are connected to form a loop.
• The registers usually hold 8 bits.
• Each device places a new bit on its output from the most significant bit (msb) of the shift
register when the clock has a negative edge and reads its input into the lsb of the shift register
on a positive edge of the clock.
• Thus a bit is transferred in each direction during each clock cycle.
• After eight cycles the contents of the shift registers have been exchanged and the transfer is
complete.
Inter-integrated Circuit Bus
The I²C bus was introduced by Philips (now NXP) Semiconductors.
The I²C bus uses only two, bidirectional lines:
• Serial data (SDA).
• Serial clock (SCL).
• It is often called the two-wire interface.
• Thus I²C provides the full functionality of a bus while using fewer lines than SPI.
• Inevitably there are penalties.
• The first is that it is slow, only 100 kbit/sec in standard mode.
• Second, a protocol must be observed: You cannot merely transmit the data and nothing more,
as in SPI. More hardware is needed than a simple shift register and transmissions must be
controlled by logic such as a state machine.
I²C Protocol
• Transfers consist of a sequence of 8-bit bytes, which are sent with the msb first and must be
acknowledged to confirm successful reception.
• The recipient does this by writing a further acknowledgment (A) bit of 0 to SDA.
• The timing relationship between the data on the SDA line and the clock on SCL is
• Data on SDA must be stable while SCL is high.
• The state of SDA may change only while SCL is low.
This means that data should be read after a rising edge of SCL and new values should be written
after a falling edge of SCL.
1. The master sends a start condition (S) by pulling SDA low while SCL is
high.
2. The master starts the clock and puts the first bit of the address on SDA
after SCL has gone low.
3. The value on SDA is valid after SCL has gone high and is read by all
slaves on the bus.
4. The last two steps are repeated until all 7 bits of the address have been
sent.
5. The final bit of the first byte specifies the direction for the rest of the
transfer. Here it is R/W*= 1, which shows that the master wishes to read
data from the slave.
6. The ninth bit is the acknowledgment (A or Ack), which is low and is sent
by the slave that recognizes its address.
7. The master must check that a slave acknowledges the address and abort the transfer if the low bit
is missing.
8. The next 8 clock cycles are used to transmit 1 byte of data from the slave to the master. The
master continues to provide the clock.
9. The ninth bit would normally be an acknowledgment. The master does not acknowledge the final
byte that it wishes to read in a transfer. This signals to the slave that the master has received
sufficient data. Here the master expects only a single byte so it does not pull SDA low. This is a
“not acknowledgment” signal (A or Nack).
10. There is a final cycle of the clock to set up the stop signal. The master pulls SDA low after the
falling edge of the clock, which is the normal time for changing SDA. It releases it again after the
final rising edge of the clock to give a rising edge on SDA while SCL is high, which provides the
stop signal (P).
UART
• Universal Asynchronous Receiver Transmitter (UART) based data transmission is an
asynchronous form of serial data transmission.
• UART based serial data transmission doesn’t require a clock signal to synchronise the transmitting
end and receiving end for transmission.
• It relies upon the pre-defined agreement between the transmitting device and receiving device.
• The serial communication settings (Baud rate, number of bits per byte, parity, number of start bits
and stop bit and flow control) for both transmitter and receiver should be set as identical.
• The start and stop of communication is indicated through inserting special bits in the data stream.
While sending a byte of data, a start bit is added first and a stop bit is added at the end of the bit
stream. The least significant bit of the data byte follows the ‘start’ bit. The ‘start’ bit informs the
receiver that a data byte is about to arrive. The receiver device starts polling its ‘receive line’ as per
the baud rate settings.
• If parity is enabled for communication, the UART of the transmitting device adds a parity bit (bit value
is 1 for odd number of 1s in the transmitted bit stream and 0 for even number of 1s).
•The UART of the receiving device calculates the parity of the bits received and compares it with the
received parity bit for error checking.
• The UART of the receiving device discards the ‘Start’, ‘Stop’ and ‘Parity’ bit from the received bit
stream and converts the received serial bit data to a word.
External Communication Interfaces
The External Communication Interface refers to the different communication channels/buses used by the
embedded system to communicate with the external world.
RS-232 is a point-to-point communication interface and the devices involved in RS-232 communication
are called ‘Data Terminal Equipment (DTE)’ and ‘Data Communication Equipment (DCE)’.
If no data flow control is required, only TXD and RXD signal lines and ground line (GND) are required for data
transmission and reception.
The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper data transmission.
If hardware data flow control is required for serial transmission, various control signal lines of the RS-232
connection are used appropriately.
The Request To Send (RTS) and Clear To Send (CTS) signals co-ordinate the communication between DTE
and DCE.
Whenever the DTE has a data to send, it activates the RTS line and if the DCE is ready to accept the data, it
activates the CTS line.
The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data.
The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a communication link.
DTR should be in the activated state before the activation of DSR.
The Data Carrier Detect (DCD) control signal is used by the DCE to indicate the DTE that a good signal
is being received.
Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the telephone line.
The commonly used baudrates by devices are 300bps, 1200bps, 2400bps, 9600bps, 11.52Kbps and
19.2Kbps.
9600 is the popular baudrate setting used for PC communication.
The maximum operating distance supported by RS-232 is 50 feet at the highest supported baudrate.
Real-Time Clock (RTC)
• Real-Time Clock ( RTC) is a system component responsible for keeping track of time.
• RTC holds information like current time (In hours, minutes and seconds) in 12 hour/24 hour format, date,
month, year, day of the week, etc. and supplies timing reference to the system.
• RTC is intended to function even in the absence of power.
• The RTC chip contains a microchip for holding the time and date related information and backup battery cell
for functioning in the absence of power, in a single IC package.
• The RTC chip is interfaced to the processor or controller of the embedded system.
• For Operating System based embedded devices, a timing reference is essential for synchronising the
operations of the OS kernel.
• The RTC can interrupt the OS kernel by asserting the interrupt line of the processor/controller to which
the RTC interrupt line is connected.
• The OS kernel identifies the interrupt in terms of the Interrupt Request (IRQ) number generated by an
interrupt controller. One IRQ can be assigned to the RTC interrupt and the kernel can perform necessary
operations like system date time updation, managing software timers etc when an RTC timer tick interrupt
occurs.
•The RTC can be configured to interrupt the processor at predefined intervals or to
interrupt the processor when the RTC register reaches a specified value (used as alarm interrupt).
A watchdog timer, or simply a watchdog, is a hardware timer for monitoring the firmware
execution.
Depending on the internal implementation, the watchdog timer increments or decrements a
free running counter with each clock pulse and generates a reset signal to reset the processor
if the count reaches zero for a down counting watchdog, or the highest count value for an
upcounting watchdog.
If the watchdog counter is in the enabled state, the firmware can write a zero (for upcounting
watchdog implementation) to it before starting the execution of a piece of code (subroutine
or portion of code which is susceptible to execution hang up) and the watchdog will start
counting. If the firmware execution doesn’t complete due to malfunctioning,
within the time required by the watchdog to reach the maximum count, the counter will
generate a reset pulse and this will reset the processor (if it is connected to the reset line of
the processor).
If the firmware execution completes before the expiration of the watchdog timer you can reset the count by
writing a 0 (for an upcounting watchdog timer) to the watchdog timer register.
Most of the processors implement watchdog as a built-in component and provides status register to control the
watchdog timer (like enabling and disabling watchdog functioning) and watchdog timer register for writing the
count value.
If the processor/controller doesn’t contain a built in watchdog timer, the same can be implemented using an external
watchdog timer IC circuit.
The external watchdog timer uses hardware logic for enabling/disabling, resetting the watchdog count,
etc instead of the firmware based ‘writing’ to the status and watchdog timer register.
7. Single-functioned
8. Complex functionality
9. Tightly-constrained
10. Safety-critical
7. Single-functioned:- Dedicated to perform a single function
8. Complex functionality: - sophisticated algorithms or multiple algorithms must be
run in some applications.
9. Tightly-constrained:- Low cost, low power, small, fast, etc
10. Safety-critical:- Must not endanger human life and the environment
• Multiple players in the same field. So if it takes more time to develop and market,
competitor may overtake.
• Also embedded system technology is changing rapidly. If we start with a new
technology and it takes time to develop, by the time product reaches market, new
technology might have come in.
