FPGA ARCHITECTURE
A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a customer or a designer after manufacturing—hence "field-programmable". The
FPGA configuration is generally specified using a hardware description language (HDL), similar
to that used for an application-specific integrated circuit (ASIC). FPGAs can be used to
implement any logical function that an ASIC could perform. The ability to update the
functionality after shipping, partial re-configuration of a portion of the design and the low non-
recurring engineering costs relative to an ASIC design, offer advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of
reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many
(changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks
can be configured to perform complex combinational functions, or merely simple logic gates like
AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be
simple flip-flops or more complete blocks of memory.
Applications
Applications of FPGAs include digital signal processing, software-defined radio,
aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech
recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal
detection and a growing range of other areas.
FPGAs originally began as competitors to CPLDs and competed in a similar space, that of glue
logic for PCBs. As their size, capabilities, and speed increased, they began to take over larger
and larger functions to the state where some are now marketed as full systems on chips (SoC).
Particularly with the introduction of dedicated multipliers into FPGA architectures in the late
1990s, applications which had traditionally been the sole reserve of DSPs began to incorporate
FPGAs instead.
Architecture
The most common FPGA architecture consists of an array of logic blocks , I/O pads, and
routing channels. Generally, all the routing channels have the same width (number of wires).
Multiple I/O pads may fit into the height of one row or the width of one column in the array. An
application circuit must be mapped into an FPGA with adequate resources. While the number of
CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks
needed may vary considerably even among designs with the same amount of logic. For example,
a crossbar switch requires much more routing than a systolic array with the same gate count.
Since unused routing tracks increase the cost (and decrease the performance) of the part without
providing any benefit, FPGA manufacturers try to provide just enough tracks so that most
designs that will fit in terms of Lookup tables (LUTs) and IOs can be routed. This is determined
by estimates such as those derived from Rent's rule or by experiments with existing designs.
In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE,
Slice etc.). A typical cell consists of a 4-input LUT, a Full adder (FA) and a D-type flip-flop, as
shown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are
combined into a 4-input LUT through the left mux. In arithmetic mode, their outputs are fed to
the FA. The selection of mode is programmed into the middle multiplexer. The output can be
either synchronous or asynchronous, depending on the programming of the mux to the right, in
the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in
order to save space.
FPGA design and programming
To define the behavior of the FPGA, the user provides a hardware description language
(HDL) or a schematic design. The HDL form is more suited to work with large structures
because it's possible to just specify them numerically rather than having to draw every piece by
hand. However, schematic entry can allow for easier visualisation of a design.
Then, using an electronic design automation tool, a technology-mapped netlist is generated. The
netlist can then be fitted to the actual FPGA architecture using a process called place-and-route,
usually performed by the FPGA company's proprietary place-and-route software. The user will
validate the map, place and route results via timing analysis, simulation, and other verification
methodologies. Once the design and validation process is complete, the binary file generated
(also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This
file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory
device like an EEPROM.
The most common HDLs are VHDL and Verilog, although in an attempt to reduce the
complexity of designing in HDLs, which have been compared to the equivalent of assembly
languages, there are moves to raise the abstraction level through the introduction of alternative
languages.
Basic process technology types
SRAM - based on static memory technology. In-system programmable and re-programmable.
Requires external boot devices. CMOS. Currently in use.
Antifuse - One-time programmable. CMOS.
PROM - Programmable Read-Only Memory technology. One-time programmable because of
plastic packaging. Obsolete.
EPROM - Erasable Programmable Read-Only Memory technology. One-time programmable
but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.
EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can be
erased, even in plastic packages. Some but not all EEPROM devices can be in-system
programmed. CMOS.
