BCS402
Time: 3 hrs. Max. Marks: 100
Note: 1. Al1swer any FIVE full questions, choosing ONE full question from eack module.
2. ill: Marks , L: Bloom's level, C: Course outcomes.
Module-l M L C
Q.l a. Explain the purpose of various fields of current program status register with 05 L2 COl
a neat diagram. /
b. Explain the ARM design philosophy. 06 L2 COl
c. Explain the core extensions ..ofARM processor with neat block diagram. 09 L2 COl
OR
Q.2 a. Explain Embedded systems hardware with a neat block diagram. 06 L2 COl
b. What is pipelines in ~M? Illustrate with an example the pipeline stage of 09 L2 COl
ARM 9 and ARM 10.
c. Describe the RIse design philosophy with 4 design rules. 05 L2 COl
Module- 2
Q.3 a. Explain [Link] with examples: "10 L2 CO2
(i) RSe (ii) MLA (iii) STRH (iv) SWP
b. Explain the different data processing instruction in ARM. 10 L2 CO2
OR
QA a. Explain Barrel shifter instruction in ARM with suitable examples. 10 L2 CO2
b. Explain the different branch instruction of ARM processor. 05 L2 CO2
c. Explain eo-processor instruction of ARM processor. 05 L2 CO2
Module- 3
Q.5 a. Explain the differeitfbasic data types [Link] examples of how each 08 L2 C03
data type can be used in a e program.
b. Discuss the concept of register allocation III compiler optimization. 07 L2 C03
Illustrate its significance with an example.
c. Describe the process of a function call in e. 05 L2 C03
OR
Q.6 a. Discuss the common port ability Issues faced when writing C programs. 07 L2 C03
How can these issues be mitigated.
b. Explain the concept of pointer aliasing with example. 07, L2 C03
,
c. How are function callshandlcd efficiently in calling function in C? 06 L2 C03
Module- 4
Q.7 a. What are interrupts? Discuss interrupt vector table with diagram for ARM 06 L2 C04
processor.
b. Describe the sequence of operations that occurs when an ARM processor 06 L2 C04
handles an IRQ exceptions.
c. Discuss the priority system for exception in ARM processor. 08 L2 C04
Q.8 a. Explain the role of the link register
OR
in ARM exception handling. 08 L2 C04
-
b. Explain the design and implementation of an interrupt stack in a ARM- 08 L2 C04
based system. Explain the steps involved.
c. What arc the key differences between a boot loader and firmware? 04 L2 C04
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BCS402
Module - S
Q.9 a. Explain the basic operation of a cache controller. 06 L2 COS
b. With a neat diagram, explain the basic architecture of a cache memory. 10 L2 COS
c. Mention any 4 relationship between cache and main memory. 04 L2 COS
OR
Q.I0 a. Write a note on cache write policy both write back or write through. 10 L2 COS
b. Describe the allocation policy on a cache miss. 04 L2 COS
c. Write a note on following: 06 L2 COS
(i) Write buffers
(ii) Cache efficiency
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