Digital Electronics and Communication Engineering

21CMRE42 - UNIT 1

Operational Amplifier (Op-amp)

An operational amplifier is an integrated
circuit that can amplify weak electric signals.
An operational amplifier has two input pins
and one output pin. Its basic role is to amplify
and output the voltage difference between the
two input pins.

The term Op Amp is used to denote an

amplifier which can be configured to perform various operations like amplification,
subtraction, differentiation, addition, integration etc. An example is the very popular IC 741.

Working Principle of Op-Amp

Open Loop Operation of an Operational Amplifier
An op-amp has a differential input and single ended output. So, if we apply two signals
one at the inverting and another at the non-inverting terminal, an ideal op-amp will amplify the
difference between the two applied input signals. We call this difference between two input
signals as the differential input voltage.
The equation below gives the output of an operational amplifier.

Where,
VOUT is the voltage at the output terminal of the op-amp.
AOL is the open-loop gain for the given op-amp and is constant (ideally).
For the IC 741 AOL is 2 x 105.
V1 is the voltage at the non-inverting terminal.
V2 is the voltage at the inverting terminal.
(V1 – V2) is the differential input voltage.

The output will be non-zero if and only if the differential input voltage is non-zero
(V1 and V2 are not equal), and will be zero if both V1 and V2 are equal.
If we apply small differential input voltage, the operational amplifier amplifies it to a
considerable value but this significant value at the output cannot go beyond the supply
voltage of the op-amp.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Closed Loop Operation

This feedback path feeds the output signal to the input. At the inputs, two signals are
simultaneously present. One of them is the original applied signal, and the other is the feedback
signal.
The equation below shows the output of a closed loop op-amp.

Where
VOUT is the voltage at the output terminal of the op-amp.
ACL is the closed loop gain.
The feedback circuit connected to the op-amp determines the closed loop gain ACL.
VD = (V1 – V2) is the differential input voltage.

The feedback is positive if the feedback path feeds the signal from the output terminal
back to the non-inverting (+) terminal. Positive feedback is used in oscillators. The feedback is
negative if the feedback path feeds the part of the signal from the output terminal back to the
inverting (-) terminal. We use negative feedback to the op-amps used as amplifiers.

Ideal Op-Amp Characteristics

• Infinite voltage gain (So that maximum output is obtained)
• Infinite input resistance (Due to this almost any source can drive it)
• Zero output resistance (So that there is no change in output due to change in
load current)
• Infinite bandwidth
• Zero noise
• Zero power supply rejection ratio (PSSR = 0)
• Infinite common mode rejection ratio (CMMR = ∞)
Applications of Operational Amplifier
The integrated op-amps offer all the advantages of ICs such as high reliability, small
size, cheap, less power consumption. They are used in variety of applications such as
inverting amplifier and non-inverting amplifiers, unity gain buffer, summing amplifier,
differentiator, integrator, adder, instrumentation amplifier, Wien bridge oscillator, Filters
etc.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Inverting Op-Amp Solved Problems

1). For the following inverting amplifier circuit, calculate the input impedance and output
voltage.

The input impedance is set through input resistance Ri which is 4kΩ. So Zin=4kΩ.
Vout=Vin Av
Av = −Rf/Ri
Av=−20k/4k
Av=−5
Vout=100mV * (−5)
Vout = −500mV
2). An inverting amplifier including a gain = 8 & 10 k Ω of an input impedance. The input
impedance (Zi) tells us what ‘Ri’ must be?
Zin = Ri
Ri=10k
So Rf =?
We know that, Av =−Rf/Ri
Rf = 10 (−8)
Rf= 80k
3). For the following inverting amplifier circuit, please calculate the closed-loop gain.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

The gain formula for the above circuit is

Gain (Av) = Vout / Vin
= -Rf / Rin
Rin = 20kΩ and
Rƒ = 80kΩ
The circuit gain can be measured as Av = -Rƒ/Rin = -80k/20k = -4
So, for inverting amplifier circuit, the closed-loop gain is -4.

Non-Inverting Op-Amp :
In this circuit configuration, the output voltage signal is given to the inverting terminal
(-) of the operational amplifier like feedback through a resistor where another resistor is given
to the ground. Here, a voltage divider with two types of resistors will provide a small fraction
of the output toward the inverting pin of the operational amplifier circuit.

Non-Inverting Op-Amp Circuit

These two resistors will provide necessary
feedback to the operational amplifier. In perfect
condition, the op-amp’s input pin will provide maximum
input impedance whereas the output pin will provide low
output impedance.

Advantages
• The voltage gain is changeable.
• The voltage gain is positive.
• Better matching of impedance can be obtained with the non-inverting amplifiers.
• The impedance value of i/p is high as compared to the inverting amplifier.

Disadvantages
• As compared to inverting op-amps, non-inverting op-amps don’t provide more stability
to the system.
• The number of stages is used depending on the necessity of attaining the required gain.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

• Based on the particular amplifier, the input & the output resistance will be changed.
• The amplifying circuit has no virtual ground, so it has a large common-mode voltage,
and the anti-interference ability is relatively poor. So that the op-amp requires a higher
common-mode rejection ratio, and another disadvantage is that the amplification factor
can only be greater than one.

Non-Inverting Op-Amp Solved Problems

1. For the following non-inverting amplifier circuit, calculate the following.

The flow of current throughout

the load resistor
• Amplifier gain
• Output voltage
• The o/p current

Solution:
The values are Vin = 2V, R1 = 6 Ohms, Fr = 10 Ohms, RL = 3K Ohms.
1). The flow of current I1 = Vin/R1
= 2/6 = 0.33 mA
2). Non-inverting op-amp gain can be calculated as
Gain = 1 + (Rf/R1)
= 1+ (10/6) = 2.66
3). The o/p voltage (VO) = ACL * VIN = 2.66 * 2V = 5.32V
VO = 5.32V
4). The flow of current supply throughout the load resistor,
IL = VO / RL = 5.32/3 = 1.773 mA
5). The o/p current can be calculated by applying KCL (Kirchhoff’s Current Law) to the
above circuit then,
IO = I1 + IL

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

IO = 0.33mA + 1.773 mA
IO = 1.28 mA = 2.103

2). In the non-inverting amplifier, if the values of R1 = 50 kilo ohms, R2 = 1000 kilo ohms &
Vin = 2v, then calculate the gain and output voltage.

Gain (AV) = 1 + (R2 / R1)

= 1+ (1000/50)
= 1 + 20
= 21
If the input voltage (Vin) is 2v then the output voltage would be: 2 X 21 = 42v

Op-amp Integrator Circuit

As its name implies, the Op-amp Integrator is an operational amplifier circuit that
performs the mathematical operation of Integration, that is we can cause the output to respond
to changes in the input voltage over time as the op-amp integrator produces an output voltage
which is proportional to the integral of the input voltage.

When a step voltage, Vin is firstly applied to the input of an integrating amplifier, the
uncharged capacitor C has very little resistance and acts a bit like a short circuit allowing
maximum current to flow via the input resistor, Rin as potential difference exists between the
two plates.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

No current flows into the amplifiers input and point X is a virtual earth resulting in zero
output. As the impedance of the capacitor at this point is very low, the gain ratio of XC/RIN is
also very small giving an overall voltage gain of less than one, ( voltage follower circuit ).

As the feedback capacitor, C begins to charge up due to the influence of the input
voltage, its impedance Xc slowly increase in proportion to its rate of charge. The capacitor
charges up at a rate determined by the RC time constant, ( τ ) of the series RC network.
Negative feedback forces the op-amp to produce an output voltage that maintains a virtual
earth at the op-amp’s inverting input.

Since the capacitor is connected between the op-amp’s inverting input (which is at
virtual ground potential) and the op-amp’s output (which is now negative), the potential
voltage, Vc developed across the capacitor slowly increases causing the charging current to
decrease as the impedance of the capacitor increases. This results in the ratio
of Xc/Rin increasing producing a linearly increasing ramp output voltage that continues to
increase until the capacitor is fully charged.

At this point the capacitor acts as an open circuit, blocking any more flow of DC current.
The ratio of feedback capacitor to input resistor ( XC/RIN ) is now infinite resulting in infinite
gain. The result of this high gain (similar to the op-amps open-loop gain), is that the output of
the amplifier goes into saturation as shown below. (Saturation occurs when the output voltage
of the amplifier swings heavily to one voltage supply rail or the other with little or no control
in between).

The rate at which the output voltage increases (the rate of change) is determined by the value
of the resistor and the capacitor, “RC time constant“.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

If the capacitor is charging and discharging, the rate of charge of voltage across the capacitor
is given as:

But dQ/dt is electric current and since the node voltage of the integrating op-amp at its
inverting input terminal is zero, X = 0, the input current I(in) flowing through the input
resistor, Rin is given as:

The current flowing through the feedback capacitor C is given as:

Assuming that the input impedance of the op-amp is infinite (ideal op-amp), no current flows
into the op-amp terminal. Therefore, the nodal equation at the inverting input terminal is
given as:

From which we derive an ideal voltage output for the Op-amp Integrator as:

To simplify the math’s a little, this can also be re-written as:

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Where: ω = 2πƒ and the output voltage Vout is a constant 1/RC times the integral of the input
voltage VIN with respect to time.

Thus the circuit has the transfer function of an inverting integrator with the gain
constant of -1/RC. The minus sign ( – ) indicates a 180o phase shift because the input signal is
connected directly to the inverting input terminal of the operational amplifier.

Op-amp Differentiator Circuit

The input signal to the differentiator is applied to the capacitor. The capacitor blocks
any DC content so there is no current flow to the amplifier summing point, X resulting in zero
output voltage. The capacitor only allows AC type input voltage changes to pass through and
whose frequency is dependent on the rate of change of the input signal.

At low frequencies the reactance of the capacitor is “High” resulting in a low gain
( Rƒ/Xc ) and low output voltage from the op-amp. At higher frequencies the reactance of the
capacitor is much lower resulting in a higher gain and higher output voltage from the
differentiator amplifier.

However, at high frequencies an op-amp differentiator circuit becomes unstable and

will start to oscillate. This is due mainly to the first-order effect, which determines the
frequency response of the op-amp circuit causing a second-order response which, at high
frequencies gives an output voltage far higher than what would be expected. To avoid this the
high frequency gain of the circuit needs to be reduced by adding an additional small value
capacitor across the feedback resistor Rƒ.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Current flowing through the capacitor will be given as:

The charge on the capacitor equals Capacitance times Voltage across the capacitor

Thus the rate of change of this charge is:

but dQ/dt is the capacitor current, i

from which we have an ideal voltage output for the op-amp differentiator is given as:

Therefore, the output voltage Vout is a constant –Rƒ*C times the derivative of the input
voltage Vin with respect to time. The minus sign (–) indicates a 180o phase shift because the
input signal is connected to the inverting input terminal of the operational amplifier.

Op-amp Differentiator Waveforms

If we apply a constantly changing signal
such as a Square-wave, Triangular or Sine-wave
type signal to the input of a differentiator amplifier
circuit the resultant output signal will be changed
and whose final shape is dependant upon
the RC time constant of the Resistor/Capacitor
combination.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Operation of Clocked SR Flip-Flop

The operation of this circuit of clocked SR flip-flop is as described as follows −

• When the clock signal is not applied, the SR flip-flop circuit remains inactive, and there is
no change in the outputs of the flip-flop.
• When the clock signal is applied, the flip-flop circuit becomes active and operates
• When S = 0 and R = 0, the output of NAND gates C and D are S' = 1 and R' = 1. Hence,
the outputs of the NAND gates A and B remains unchanged. This is called Hold State of
the SR flip-flop.
• When S = 0 and R = 1, the output of the NAND gates C and D are S' = 1 and R' = 0, the
output of the NAND gate A is 0 and that of NAND gate B is 1. This is called Reset State of
the SR flip-flop.
• When S = 1 and R = 0, the output of the NAND gates C and D are S' = 0 and R' = 1, the
output of the NAND gate A is 1 and that of the NAND gate B is 0. This is called Set
State of the SR flip-flop.
• When S = 1 and R = 1, the output of the NAND gates C and D are S' = 0 and R' = 0, the
outputs of the both NAND gates A and B try to become 1, which is not possible. This is
called Forbidden State of the SR flip-flop.

Inputs Output Comment

S R Qn Qn+1

0 0 0 0 No Change / Hold

0 0 1 1 No Change / Hold

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

1 0 1 1 Set

1 1 0 X Forbidden

1 1 1 X Forbidden

Applications of Clocked SR Flip-Flop

• Digital counters
• Storage and shift registers
• Data storage elements
• Data transfer systems
• Frequency divider circuits, etc.

JK flip – flop

A JK flip – flop is the modification of SR flip – flop with no illegal state. In this the J
input is similar to the SET input of SR flip – flop and the K input is similar to the RESET input
of SR flip – flop. The symbol of JK flip – flop is shown below.

JK flip flop Logic Diagram

Logic diagram consists of three input NAND gates replacing the two input NAND gates
in SR flip – flop and the inputs are replaced with J and K from S and R.
The design of the JK flip – flop is such that the three inputs to one NAND gate are J,
clock signal along with a feedback signal from Q’ and the three inputs to the other NAND are
K, clock signal along with a feedback signal from Q. This arrangement eliminates the
indeterminate state in SR flip – flop.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Truth Table

Operation
• Case 1 : When both the inputs J and K are LOW, then Q returns its previous state value i.e.
it holds the previous data.
When we apply a clock pulse to the J K flip flop and the J input is low then irrespective of
the other NAND gates, the NAND gate-1 output becomes HIGH. In the same manner, if
the K input is low then output of NAND gate-2 is also HIGH. So thus the output remains
in the same state i.e. no change in the state of flip flop.
• Case 2 : When J is LOW and K is HIGH, then flip flop will be in Reset state i.e. Q = 0, Q’
= 1.
When we apply a clock pulse to the J K flip flop and the inputs are J is low and K is high
the output of the NAND gate connected to J input becomes 1. Then Q becomes 0. This will
reset the flip flop again to its previous state. So the Flip flop will be in RESET state.
• Case 3 : When J is HIGH and K is LOW, then flip – flop will be in Set state i.e. Q = 1, Q’
=0
• When we apply a clock pulse to the J K flip flop and the inputs are J is high and K is low
the output of the NAND gate connected to K input becomes 1. Then Q’ becomes 0. This
will set the flip flop with the high clock input. So the Flip flop will be in SET state.
• Case 4 : When both the inputs J and K are HIGH, then flip – flop is in Toggle state. This
means that the output will complement of the previous state.

The truth table of JK flip – flop is shown below.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Limitations
• Complexity
• Power consumption
• Propagation delay
• Limited scalability

D Flip flops
D Flip flops or data flip flops or delay flip flops can be designed using SR flip flops by
connecting a not gate in between S and R inputs and tying them together. D flip flops can be
used in place of SR flip flops where you need only SET and RESET state.

D Flip-Flop Circuit
D Flip-Flop Working:

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

• Case 1: D = 0
Gate 1 = 1, Gate 2 = 0, Gate 4 / Q(n+1)’ = 1, Gate 3 / Q(n+1) = 0
• Case 2: D = 1
Gate 1 = 0, Gate 2 = 1, Gate 3 / Q(n+1) = 1, Gate 4 / Q(n+1)’ = 0

D Flip-Flop Truth Table

CLK D Q(n+1) State

– 0 0 RESET

– 1 1 SET

Advantages
• Single input:
• No feedback loop:
• No invalid states:
• Reduced power consumption:
• Bi-stable operation

Limitations
• No feedback
• No toggling
• Propagation delay
• Limited scalability

Applications
• Shift registers
• State machines
• Counters
• Data storage

T flip flop
T flip flop is similar to JK flip flop. Just tie both J and K inputs together to get a T Flip
flop. Just like the D flip flop, it has only one external input along with a clock.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

T Flip Flop Circuit

T Flip-Flop Working
Case 1: T=0
Gate1 = 0, Gate2 = 0, Gate3/Q(n+1) = Q, Gate4/Q(n+1)’ = Q’
Gate3 = (0+Q’)’ = (Q’)’ = Q
Gate4 = (0+Q)’ = (Q)’ = Q’
Case 2: T=1
Gate1 = Q, Gate2 = Q’, Gate4/Q(n+1)’ = 0, Gate3/Q(n+1) = Q’
Gate4 = (Q’+Q)’ = 1’ = 0
Gate3 = (Q+0)’ = Q’

T Flip-Flop Truth Table

CLK T Q(n+1) State

0 Q NO CHANGE
1 Q’ TOGGLE

Advantages
• Single input
• No invalid states
• Reduced power consumption
• Bi-stable operation

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

• Easy to implement

Limitations
• Inverted output
• Limited functionality
• Glitches
• Propagation delay

Applications
• Frequency division
• Frequency multiplication
• Data storage

Counters
• Asynchronous or ripple counters.
• Synchronous counters.

Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-
flop are being used. But we can use the JK flip-flop also with J and K connected permanently
to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied
to the clock input of the next flip-flop i.e. FF-B.

Logical Diagram

SCHOOL OF MARITIME STUDIES

Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

S.N. Condition Operation

Initially let both

1 the FFs be in the QBQA = 00 initially
reset state

As soon as the first negative clock edge is applied, FF-A

will toggle and QA will be equal to 1.
After 1st QA is connected to clock input of FF-B. Since QA has
2 negative clock changed from 0 to 1, it is treated as the positive clock edge
edge by FF-B. There is no change in QB because FF-B is a
negative edge triggered FF.
QBQA = 01 after the first clock pulse.

On the arrival of second negative clock edge, FF-A toggles

again and QA = 0.
After 2nd
3 negative clock The change in QA acts as a negative clock edge for FF-B.
edge So it will also toggle, and QB will be 1.
QBQA = 10 after the second clock pulse.

On the arrival of 3rd negative clock edge, FF-A toggles

again and QA become 1 from 0.
After 3rd
Since this is a positive going change, FF-B does not
4 negative clock
respond to it and remains inactive. So QB does not change
edge
and continues to be equal to 1.
QBQA = 11 after the third clock pulse.

On the arrival of 4th negative clock edge, FF-A toggles

again and QA becomes 1 from 0.
After 4th
5 negative clock This negative change in QA acts as clock pulse for FF-B.
edge Hence it toggles to change QB from 1 to 0.
QBQA = 00 after the fourth clock pulse.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Truth Table

Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such
a counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The
JB and KB inputs are connected to QA.

Logical Diagram

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Operation

S.N. Condition Operation

Initially let both

1 the FFs be in the QBQA = 00 initially.
reset state

As soon as the first negative clock edge is applied, FF-A will

toggle and QA will change from 0 to 1.
After 1st
But at the instant of application of negative clock edge, QA ,
2 negative clock
JB = KB = 0. Hence FF-B will not change its state. So QB will
edge
remain 0.
QBQA = 01 after the first clock pulse.

On the arrival of second negative clock edge, FF-A toggles

again and QA changes from 1 to 0.
After 2nd
3 negative clock But at this instant QA was 1. So JB = KB= 1 and FF-B will
edge toggle. Hence QB changes from 0 to 1.
QBQA = 10 after the second clock pulse.

After 3rd On application of the third falling clock edge, FF-A will toggle
4 negative clock from 0 to 1 but there is no change of state for FF-B.
edge QBQA = 11 after the third clock pulse.

After 4th On application of the next clock pulse, QA will change from 1
5 negative clock to 0 as QB will also change from 1 to 0.
edge QBQA = 00 after the fourth clock pulse.

Shift Register
The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers. There are four
mode of operations of a shift register.

• Serial Input Serial Output

• Serial Input Parallel Output

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

• Parallel Input Serial Output

• Parallel Input Parallel Output
• Serial Input Serial Output

Serial Input Serial Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an

entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data
input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on.

Block Diagram

Operation
• Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number
to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the
FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.
• Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits,
FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.
• Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 =
1110.
• Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in
the register is Q3 Q2 Q1 Q0 = 1111.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Truth Table

Waveforms

Serial Input Parallel Output

• In such types of operations, the data is entered serially and taken out in parallel fashion.
• Data is loaded bit by bit. The outputs are disabled as long as the data is loading.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

• As soon as the data loading gets completed, all the flip-flops contain their required data,
the outputs are enabled so that all the loaded data is made available over all the output lines
at the same time.
• 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO
mode is same as that of SISO mode.

Block Diagram

Parallel Input Serial Output (PISO)

• Data bits are entered in parallel fashion.
• The circuit shown below is a four bit parallel input serial output register.
• Output of previous Flip Flop is connected to the input of the next one via a combinational
circuit.
• The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.

There are two modes in which this circuit can work namely - shift mode or load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will
pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary
input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel loading
takes place.

Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence
the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active.
Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus
the parallel in serial out operation takes place.

Block Diagram

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1,
D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.

Block Diagram

Multiplexer
A multiplexer is a combinational circuit that has 2n input lines and a single output line.
Simply, the multiplexer is a multi-input and single-output combinational circuit. The binary
information is received from the input lines and directed to the output line. On the basis of the
values of the selection lines, one of these data inputs will be connected to the output.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:

In 2×1 multiplexer, there are only two inputs, i.e.,

A0 and A1, 1 selection line, i.e., S0 and single outputs,
i.e., Y. On the basis of the combination of inputs which
are present at the selection line S0, one of these 2 inputs
will be connected to the output.

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1
Logical circuit of the above expression is given below:

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0,
A1, A2, and A3, 2 selection lines, i.e., S0 and S1 and single output,
i.e., Y. On the basis of the combination of inputs that are present at
the selection lines S0 and S1, one of these 4 inputs are connected to
the output. The block diagram and the truth table of the 4×1
multiplexer are given below.

Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

8 to 1 Multiplexer:
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and
A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination
of inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are connected
to the output. The block diagram and the truth table of the 8×1 multiplexer are given below.

SCHOOL OF MARITIME STUDIES

 Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .
A6+S0.S1.S3.A7

Logical circuit of the above expression is given below:

SCHOOL OF MARITIME STUDIES

Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

Laws and Theorems of Boolean Algebra

1a. X • 0 = 0 1b. X + 1 = 1 Annulment Law

2a. X • 1 = X 2b. X + 0 = X Identity Law

3a. X • X = X 3b. X + X = X Idempotent Law

4a. X • X = 0 4b. X + X = 1 Complement Law

Double Negation
5. X =X
Law

6a. X • Y = Y • X 6b. X + Y = Y + X Commutative Law

7a. X (Y Z) = (X Y) Z = (X Z) Y = X Y Z Associative Law

7b. X + (Y + Z) = (X + Y) + Z = (X + Z) + Y = X + Y + Z Associative Law

X + Y Z = (X + Y) • (X
8a. X • (Y + Z) = X Y + X Z 8b. Distributive Law
+ Z)
de Morgan's
9a. X • Y = X + Y 9b. X + Y = X • Y
Theorem

10a. X • (X + Y) = X 10b. X + X Y = X Absorption Law

11a. (X + Y) • (X + Y) = X 11b. X Y + X Y = X Redundancy Law

12a. (X + Y) • Y = XY 12b. X Y + Y = X + Y Redundancy Law

13a. (X + Y) • (X + Z) • (Y + Z) = (X + Y) • (X + Z) Consensus Law

13b. X Y + X Z + Y Z = X Y + X Z Consensus Law

X ⊕ Y = (X + Y) • (X +
14a. 14b. X ⊕ Y = X Y + X Y XOR Gate
Y)
X ⊙ Y = (X + Y) • (X •
15a. 15b. X ⊙ Y = X Y + X Y XNOR Gate
Y)

15c. X ⊙ Y = (X + Y) • (X + Y) XNOR Gate

Gates Standard DeMorgan's

NAND X = A • B X=A+B

SCHOOL OF MARITIME STUDIES

Digital Electronics and Communication Engineering
21CMRE42 - UNIT 1

AND X=A•B
X=A+B

NOR X=A+B X=A•B

OR X=A+B
X=A•B

Part A Questions
S.No Questions
1. What is a Multiplexer?
2. What are the characteristics of Ideal op-amp?
3. What are the applications of op-amp?
4. What is meant by synchronous counter?
5. What is the purpose of shift register?
6. Convert the following (110101)2 into Octal number.
7. What is the purpose of Counter?
8. What is a Zero Drift Amplifier?
9. What is a Voltage Follower?
10. Convert 0100011011002 to Decimal Number
11. Convert (41)8 into binary number.
12. Find two’s complement of 10101010
13. Find two’s complement of 01010101
For the following inverting amplifier circuit, calculate the output voltage.

14.

An inverting amplifier including a gain = 10

15.
& 12 k Ω of an input impedance. Calculate the value of feedback resistance.

SCHOOL OF MARITIME STUDIES