COMSATS UNIVERSITY
ISLAMABAD
DIGITAL LOGIC DESIGN
LAB REPORT
Name: Muhammad Mamoon Akber
Registration No.FA17-BEE-084
Section: BEE-2B
LAB # 11
Dated: 23 May, 2018
Submitted to: Maam Asma Ramay
LAB # 11 : Implementation of up/down
Counter withTerminal Count and Reset
on FPGA
Objective:
In this lab we implement up/down counter with terminal count and reset on
FPGA. We also learn how to use internal clock of FPGA and implement
clock divisor. The counter value will be displayed on 7-segment displays
of Nexys2 board so we implement scanning display controller to control
multiple 7-segment displays because they have common data bus (CA – DP).
Pre-Lab:
Up/down counter with terminal count and reset:
A counter is essentially a register that goes through a predetermined
sequence of binary states. The gates in the counter are connected in such a
way as to produce the prescribed sequence of states. Although counters are
a special type of register, it is common to differentiate them by giving them
a different name.
Up/Down Counting:
When up_down signal is low: counter will count in ascending order
When up_down signal is high: counter will count in descending order
Reset: (Active High reset)
When reset signal is low: counter will count normally
When reset signal is high: counter will be clear
Enable: (Active High)
When enable signal is low: counter will stop counting
When enable signal is high: counter starts counting
Terminal count:
Terminal count is an output signal which actives under any desired
condition or counter will reach to a specific value.
Clock:
Counter will count up or down on active transition of the clock.
Segment Displays Controller:
A scanning display controller circuit can be used to show a four-digit
number on Nexys2 board 7- segment display section. This circuit drives the
anode signals and corresponding cathode patterns of each digit in a
repeating, continuous succession, at an update rate that is faster than the
human eye can detect. Each digit is illuminated just one-quarter of the time,
but because the eye cannot perceive the darkening of a digit before it is
illuminated again, the digit appears continuously illuminated. If the update
or “refresh” rate is slowed to around 45 hertz, most people will begin to
seethedisplayflicker.Inorder
foreachofthefourdigitstoappearbrightandcontinuously
illuminated,allfourdigitsshouldbedrivenonceevery1to16ms,fora refresh
frequencyof1KHz to60Hz.Forexample,ina60Hzrefreshscheme,theentire
displaywouldberefreshedonceevery16ms,andeachdigitwouldbeilluminatedfo
r¼oftherefreshcycle,or4ms.Thecontrollermustdrivethecathodeswiththecorr
ectpatternwhenthecorrespondinganodesignal isdriven.To illustrate
theprocess, if AN0 is asserted while CB and CC are asserted, then a “1”
will be
displayedindigitposition1.Then,ifAN1isassertedwhileCA,CBandCCareassert
ed,thena “7”willbe displayed
indigitposition2.IfAN0andCB,CCaredrivenfor4ms,andthenA1and CA,CB,CC
aredrivenfor4msinanendless succession,thedisplaywillshow“17”inthefirst
two digits. An example timing diagram for a four-digit controller is
provided.
Figure10.1: Refresh period trimming diagram for4 digit7-segment
display
Pre-lab Task #1:
InLab Task #1:
InLab Task #2:
Up and Down Counter:
Module:
Test Bench:
Wave forms:
DEVICE UTALIZATION SUMMARY:
Time Report:
Path Delay:
CRITICAL ANALYSIS:
In the above experiment we analyzed the working of
up and down counter with terminal count and rest and also implemented it
on FPGA. We also observed the result of this implementation on seven-
segment of Nexys2 on board. We noticed that Nexys2 board has a 50 MHz
clock divisor will generate 1 MHz clock. It is used for output verification
purposes. We also analyzed the up and down counter with their waveforms
using behavioral modeling with the help of Xilinx software. We observed
that a counter is essentially a register that goes through a predetermined
sequence of binary states. A synchronized counter counts from 0 to 2n -1.
