1. A 128 KB cache has a 256 byte block size and is 4-way set-associative.

If the physical
is 48-bits long, what is the size of the tag directory(in bytes)?

2. Explain with reasoning, which of the following statements is/are true in the context of
associative mapped cache memory ? [MSQ]

[A] Fully associative cache needs more number of comparators to match tag bits
compared to direct mapped cache.

[B] k-way set associative mapped cache needs less number of comparators to
match tag bits compared to fully associative mapped cache with n blocks, where k and
n are integers and k<n.

[C]. Fully associative cache needs less number of comparators to match tag bits
compared to direct mapped cache.

[D]. k-way set associative mapped cache needs more number of comparators to
match tag bits compared to fully associative mapped cache with n blocks, where k and
n are integers and k<n.

3. A certain processor uses a fully associative cache of size 16 KB. The cache block size
is 32 bytes. Assume that the main memory is byte addressable and uses a 32-bit
address. How many bits are required for the Tag and the offset fields respectively in the
addresses generated by the processor?

A. 24, 8 B. 27, 5 C. 28, 4 D. 30, 2

4. Consider 64 KB 2-way set associative cache with 128-byte block size. CPU generates
32 bits physical address. What is the number of comparators and size of each
comparator required for tag matching, respectively?

a). (2, 17) b). (2, 18) c). (17, 2) d). (18, 2)

5. Consider a direct mapped cache (initially empty) with a total 16 cache blocks. The
main memory consists of 256 blocks and the request for memory blocks is in the
following order:

0, 255, 1, 5, 3, 8, 132, 159, 216, 129, 63, 8, 48, 32, 73, 92.

Which one of the following memory blocks will be in cache at the end of accessing the
given blocks?
(A) 0

(B) 255

(C) 129

(D) 216

6. A computer system which has a 256 MB byte-addressable main memory and a 128
KB, direct mapped cache memory with a block size of 2KB. Consider the following four
physical addresses represented in hexadecimal notation.

P1 = 0x34248B4,

P2 = 0x3548AB8,

P3 = 0x36A49BC,

P4 = 0x35E56B0

Which of the following statement/s is/are TRUE ?

A. P1, P2 are mapped to the same cache line

B. P2, P3 are mapped to the same cache line

C. P1, P3 are mapped to the same cache line

D. P2, P4 are mapped to the same cache line

7. A computer has 256KB , k-way set associative write back data cache with block size
of 64 B. The address sent to the cache controller by the processor is of 32 bits. In
addition to the address tag , each cache directory contains 2 valid bits and 1 modified
bit. If 18 bits are used to address tag then what is the min value of k.

8. Explain different hazards in a pipeline and how to avoid each of those hazards.

9. The instruction pipeline of a RISC processor has the following stages: Instruction
Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and
Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every
instruction. Consider a sequence of 100 instructions. In the PO stage, 30 instructions
take 4 clock cycles each, 25 instructions take 3 clock cycles each, and the remaining 45
instructions take 2 clock cycles each. Assume that there are no data hazards and no
control hazards.
The number of clock cycles required for completion of execution of the sequence of
instructions is _____

10. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID),
Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID,
OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1
clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction and 4
clock cycles for DIV instruction respectively.

I0: DIV R2, R0,R1 (The operation is R2←R0/R1)

I1: MUL R5, R3,R4 (The operation is R5←R3∗R4)

I2: SUB R2, R5,R2 ( The operation is R2←R5−R2)

I3: ADD R5, R2,R6 (The operation is R5←R2+R6 )

If there is no operand forwarding in the pipeline, what is the number of clock cycles
needed to execute the above sequence of instructions?

11. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID),
Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID,
OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1
clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction and 4
clock cycles for DIV instruction respectively.

I0: DIV R2, R0,R1 (The operation is R2←R0/R1)

I1: MUL R5, R3,R4 (The operation is R5←R3∗R4)

I2: SUB R2, R5,R2 ( The operation is R2←R5−R2)

I3: ADD R5, R2,R6 (The operation is R5←R2+R6 )

If operand forwarding is used in the pipeline then what is the number of clock cycles
needed to execute the sequence of instructions given above?

12. Consider an instruction pipeline with four stages with the stage delays 4 nsec, 6
nsec, 11 nsec, and 9 nsec respectively. The delay of an inter-stage register stage of the
pipeline is 1 nsec. What is the approximate speedup of the pipeline in the steady state
under ideal conditions as compared to the corresponding non-pipelined
implementation?
13. Consider the following processors (ns stands for nanoseconds). Assume that the
pipeline registers have zero latency.

P1: Four-stage pipeline with stage latencies 1ns, 3ns, 2ns, 1ns.

P2: Four-stage pipeline with stage latencies 1ns, 2ns, 1ns, 1.5ns.

P3: Five-stage pipeline with stage latencies 0.5ns, 1.5ns, 1ns, 0.6ns, 1ns.

P4: Five-stage pipeline with stage latencies 0.5ns, 1ns, 1.2ns, 1ns, 1.4ns.

Which processor has the highest peak clock frequency?