Digital Design and Computer Architecture RISC-V Edition jie é us 2 : ‘I , } \ 4 Sarah L Harris Span David Money Harris‘Table B.4 Register names and numbers |: em] CR-Type "ero ‘Constant value 0 se _| ChType a v2 [om | c5-1yp0 sp 2 |e |¢8:type 9 _| CB-Type ©. 3 Boy 9 _|c3-type slip _|x8____Saved register / Frame pointer op | ctype st fo op | C88-Type a1__[x10-11 Function arguments / Return values [op | cw-type {32-7 _|x12-17 [Function arguments 7 con s2-11_[xt8-27 ne 15-6 [328-31 [Temporary reyiters Figure B.2 RISC-V compressed (16-bit) instruction formats ‘Table B.S AVM: RISC-V multiply and dvide instructions a funct3 funct7 [Type [Instruction Om (0110011 (51) |000 R Td. tsi, 152 rd = CFS)" Sau (ortoo1 (St) [001 K Td, rs1,_ 152 muliply high signed signed ra TS) (OL101 (51) [10 K 14,11, Fs? |muhiply high signed unsigned ra Tee (ortoo1t (51) [O11 k Td. esi. vse ra TS2)er ‘oL10011 (51) |100 K rd. rst. rs? ra 32 ‘orto011 (Si) [101 R rivet. rs? ra 52 (ot100 (51) [110 R ids rst vse ra 52 (ortoort (Si) 11 K Ta. rst 1s? remainder unsigned ra 752 ‘Table 8.6 RVC: RISC-V compressed (16-bit instructions CT Pca 32-84 Equal 0000) ee close dep reps pe ferorat yt 0) Ee ene ta Ceratatciam0) (509 000) Eat fein na CeratsaGiam 01061) 00 Ea fer CeratsaCiam 21021) ni E18 fen erate iam FET roma eee er arabs aa) 1) 0 ——e— eee arabs) ET) ort Eig en orth Ee esi, digs my ott Eg facia tater fale ort) Eg ein a, Sige Tmy ot Ea fear: (tatiana or) > “fa —fesaarets Te Son aT om Eg fesse ram oh Eas ne arta ori =e fesandt SETS ov joey fess nnn ov te feseor ame orth fae ame ott eee rare" O14 Egy fess tat {aber ott Eee fecaeae rat ie Ti oth become oS 10; Eat esti, rés—tan 10. Eg feria te erate aa) en Eg fee feratstCian) (55) rat = erin te erat iaa CES tat eae eet att 10ah ee oar 10h >it estore Toh Eee er aI 0) Et fea, FWP Toh Pas fectaue ne, (carota Cima 79) 101 ess fess rae GerauatCian"a9) mh sda 2, GeratniCian "9 09) rat's rs bit register designator for registers 8-15: 000 8 or f8,0013= 39 oF F9, eeTable B.7 RISC-V pseudoinstructions Pscudoinstruction Ey = Pe om nop add 30, xD. 0 no operation Ved, lama addi rd. xD, imi load 12-ic immediate rd = Signkxtendtiam3) Teds a. Twi rd, tami” load 32-bit immediate r= FB, 260i rd) rd mas mya, rst addi rd. si. 0 move alo called “register copy”) [7S = rd not d, rst yori rd, rst. -1 one's complement rd = =rst negra, est sub rd, xD, esT wos complement r= rst seqz rd, rst slefu rd, est 7 setit=0 rd = (rst snez ra, est sTtu_rd, xD, esl setit=0 rd= (rst = 0) sitz ed, rst sit rd, esl x0 setif<0 rd = (rst < 0) satz rd, est sit rd, x0, rst setit> 0 rd = (rs > 0) beqz rst. label eqs, x0, label branch f= 0 if (sl = 0) PC = label fez rst, Tate] ne rst, xD, Tabel branch i= 0 if-trsi = 0) C= label lez esl. label bge x0, sl label branch if< 0 if (sis 0) PC = label byez rst Tabel hoe Fst, xD, label branch if 20 if (rst = 0) PC = Tabel Bitz est. label bit__Fsi, x0, label ranch if< 0 if (rs < 0) PC = label bate rsi. Tate] It x0, sl, Tabel branch if> 0 if (rs > 0) PC = Tate] ble rsl. rs2, label [Boe rs2, esl. label branch ifs if (rss Fs2) PC = label bgt_rsl rs2, latel [lt rs2. rs, latel branch if if (rst > es2) PC = label leu esl. rs2, label [Boeu_rs2, esl, label ranch if ¢ (unsigned) if (rs s_Fs2) PC = label bgt rsl, rs2, label [piturs2, esl, offset branch i> (unsigned) if (esi > rs2) °C = label i__label jel x0, label jump Pe = label jal abe jal_ra, label jump and lnk FC = Tabel mena ie est jelr x0, rst. 0 jump register Fe = rs alr est jelr_ra, sl. 0 jump and link register PC rst mensa ret gain 30, ra 0 return from function r= ra alt Tabet jal__ra, Tabet call neathy function PC = Tabet mena call Taber? auipe Fa, offsetuar ‘all faraway function P= Po + offset, ra = PC +a alr ray_ra, offset, Te rd symbol Jauipe rd, symbotn a." Toad address of global variable [r= 0 + sumboT addi rd. rd. symbols Vibihiwl rd, symbol Javipe rd, symbols” (load global variable r= [Pt + symbol) Vibjhiwi rd. symbol nstrd) SHB[nIWI r52, symbol, FSI [auipe si, synboloiaz" |store global variable (PE + smmboll - 2 SUb[h[w)_r52_ symbol y.s¢rs1) carr rd, est jesrrs rd, cor, x read GSR rd = er esrw csr, rst esrrw x0. csr, rsh ‘write CSR [esr = esi “Ibe 1 of the niece oe / symbol 1, the upper immed s incemened by 1. symbol and offset ae the 32-bit Crave addresses of label snd global waa especie o Paso mz THOTT (115)|000- Teal 1110011 (115)|000__|I_ebreak transfer control to debugger —_(imm=1) 1110011 (115}/000__|T_[uret retuen from use exception _(rs'=0,d=Ojmm=2) _/PE=vebe 1110011 (113) 000__|I_[sret etuen from supervisor exception (r1=0,rd=0,imm=258) PC = sene THTO00HT (115) 000 [I [nret return from machine exception _(rs1=0,rd=0,imm=770) [Pc neve 1110011 (115}]001_|T|esrew Fd.c5r.731 [COR readlwrite {imm=CSR number) [FE csr SP =FsT 1110011 (115) 010 [I [estes re.csrst_| CSR readset {imm=CSR number) _|ré=es",esr=esr | rat 1110011 (115}]O11 [1 |esrrcrd.csr.rs1_ [CSR readlear fimm=CSR number) |rd=csr,csr= csr &=rs1 1110011 (115) 101_|1_csrrvi rd,cSr.uinm| COR readiweite immediate _(imm=CSR number) [r= csr.csr=Zeroext(uith) THHDOTE (115) [110 I Jesresi-rd.csr catwn CSR read/ser immediate fimm=CSK number scat cum) THVOOTT (1S) 141 fF __[csrrcT rd.cor.alam (CSR readiclear immediate (immaCSR number) rd=esr, esta 66 &-Zerofxt(utnm For pevilged/ CSR instueton, he S-bit unsigned immediate, umm, encoded in the 1 felIn Praise of Digital Design and Computer Architecture RISC-V Edition Harris and Harris have shown how to design a RISC-V processor from the gates all the way up through the microarchitecture. Their clear explanations combined with their comprehensive approach give a full picture of both digital design and the RISC-V architecture. With the exciting opportunity that students have to run large digital designs on modern FPGAs, this approach is both informative and enlightening. David A. Patterson University of California, Berkeley What broad fields Harris and Harris have distilled into one book! As semiconductor manufacturing matures, the importance of digital design and computer architecture will only inerease. Readers will find an approachable and comprehensive treatment of both topics and will walk away with a clear understanding of the RISC-V instruction set architecture, ‘Andrew Waterman siFive ‘There are excellent texts for teaching digital design and there are excellent texts for teaching computer hardware organization - and this textbook does both! Iris also unique in its ability to connect the dots. The writing makes the RISC-V architecture understandable by building on the basics, and I have found the exercises to be a great resource across multiple courses. Roy Kravitz Portland State University When I first read Harris and Harris's MIPS textbook back in 2008, I thought that it was one of the best books I had ever read for teaching computer architecture. I started using it in my courses immediately. Thirteen years later, I have had the honor of reviewing this new RISC-V edition, and my opinion of their books has not changed: Digital Design and Computer Architecture: RISC-V Edition is an excellent book, very clear, thorough, with a high educational value, and in line with the courses that we teach in the areas of digital design and computer archi- tecture. I look forward to using this RISC-V textbook in my courses. Daniel Chaver Martinez University Complutense of MadridDigital Design and Computer Architecture RISC-V EditionDigital Design and Computer Architecture RISC-V Edition ‘Sarah L. Harris David Harris AMSTERDAM + BOSTON * HEIDELBERG * LONDON, ‘NEW YORK * OXFORD « PARIS SAN DIEGO ¥ SAN FRANCISCO ® SINGAPORE « SYDNEY TOKYO ELSEVIER Morgan Kaufmann sa imprint of Elsevier‘Morgan Kaufmann is an imprint of Elsevier 50 Hampshire Street, sth Floor, Cambridge, MA 02136, United States Copyright © 2022 Elsevier Inc. All rights reserved. [No part ofthis publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval sytem, without permission in waiting from the publisher. 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In using such information or methods they should be mindful oftheir own safety and the safety of others, including parties for whom they have a professional responsibility. ‘To the fullest extent ofthe law, neither the Publisher nor the authors, contributors, oF ‘editors, assume any liability for any injury and/or damage to persons or property as a matter ‘of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. ‘A catalogue record for this book is available from the British Library. Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress. ISBN: 978-0-12-820064-3 For Information on all Morgan Kaufmann publications visit our website at https:/wivwcelsevier.com/books-and-journals Publisher: Katey Birtcher Senior Acquisitions Editor: Steve Merken Editorial Project Manager: Ruby Gammell/Andrae Akeh Senior Project Manager: Manikandan Chandrasekaran Cover Designer: Victoria Pearson Esser ‘Typeset by MPS Limited, Chennai, India Printed in the United States of America Pilg Working together Al to grow libraries in Beok.Ald developing countries Last digits the print number. 9 8.7 6 5 43.2.2Contents Preface..... About the Authors . . Chapter 1 From Zero to One .. id 12 1s 16 cesses ceeeeeeees xix Features ...seeeeeee : wees cee Online Supplements . sees cee XX How to Use the Software Tools ina Course. cea Labs . RVfpga. Bugs . Acknowledgments. The Game Plan . The Art of Managing Complexity. 1.2.1 Abstraction Discipline. 2.3. The Three - The Digital Abstraction. ‘Number Systems .. 1 Decimal Numbers 2 Binary Numbers. 3 Hexadecimal Numbers 4 Bytes, Nibbles, and All That Jazz. S Binary Addition... 6 Signed Binary Numbers. ic Gates. . 1 NOT Gate 2 Buffer. 3 4 s 6 1 2 3 Deessos Other Twwo-Input Gates . Muttiple-Input Gates . ath the Digital Abstraction. Supply Voltage . Logic Levels . Noise Margins . RRRPEDEDEEE17 18 19 1.6.4 DC Transfer Characteristics .. 1.6.5 The Static Discipline. CMOS Transistors ...... 1.7.1 Semiconductors . 1.7.2 Diodes 1.7.3 Capacitors .. 1.74 nMOS and pMOS Transistors . 1.7.5 CMOS NOT Gate... 1.7.6 Other CMOS Logic Gates . 1.7.7 Transmission Gates. 1.7.8 Pseudo-nMOS Logic. Power Consumption. Summary and a Look Ahead Exercises . Interview ‘Questions Chapter 2 Combinational Logic Design ... 24 22 2.3 24 2.5 2.6 27 2.8 Introduction Boolean Equations . 2.2.1 Terminology . 2.2.2 Sum-of-Products Form 2.2.3 Product-of- Sums Form. Boolean Algebra . 23.1 Axioms. 2.3.2 Theorems of One Variable . 23.3 Theorems of Several Variables 23.4 The Truth Bebind It All 23.5 Simplifying Equations From Logic to Gates. . Mattilevel Combinational Logic 25.1 Hardware Reduction . 2.5.2 Bubble Pushing . X's and Z’s, Oh My . 2.6.1 Mlegal Value: X.. 2.6.2 Floating Value: Z Karnaugh Maps........-.-+ 27.1 Circular Thinking .. 2.7.2 Logic Minimization with K-Maps. 273 Don't Cares. : 7.4 The Big Picture. . Combinational Building Blocks. 28.1 Multiplexers 28.2 Decoders2.9 Timing... . 2.9.1 Propagation and Contamination Delay’ 86 2.9.2. Glitches 2.10 Summary... Exercises .. Interview Questions 2104 Chapter 3 Sequential Logic Design - 107 3.1 Introduction . 107 3.2 Latches and Flip-1 - 107 SR Latch . = 109 D Latch - il D Flip-Flop = 112 Register - 112 Enabled Flip-Flop - 113 Resettable Flip-Flop - 114 Transistor Level Latch and Flip-Flop Designs. - 114 3.2.8 Putting It All Together - 116 3.3 Synchronous Logic Design - 17 3.3.1 Some Problematic Circuits - 17 3.3.2. Synchronous Sequential Circuits . - 118 3.3.3. Synchronous and Asynchronous Circuits = 120 3.4 Finite State Machines. - 121 3.4.1 FSM Design Example. = 121 3.4.2 State Encodings .. - 127 3.4.3 Moore and Mealy Machines . = 130 3.4.4 Factoring State Machines. . - 132 3.4.5. Deriving an FSM from a Schematic - 135 3.4.6 FSM Review .. voces 138 3.5 Timing of Sequential Logic....... 139 3.5.1 The Dynamic Discipline . 140 3.5.2 System Timing 140 3.5.3 Clock Skew 146 3.5.4 Metastability.. 149 3.5.5 Synchronizers . 150 3.5.6 Derivation of Resolution Time 152 3.6 Parallelism......... 15s 3.7 Summary. 159 Exercises . : 160 Interview Questions 169 xixii Chapter 4 Hardware Description Languag. 4.1 Introduction . 411 Modules........... 4.1.2 Language Origins .. 4.1.3 Simulation and Synthesis. 42 Combinational Logic 42.1. Bitwise Operators... 4.2.2 Comments and White Space. 42.3 Reduction Operators . 424 Conditional Assignment. 4.2.5 Internal Variables .. : 426 Precedence...ssssscsvseseverserererees 42.7 Numbers 42.8 Zsand X’ 42.9 Bit Swicaling. 4.2.10 Delays. 4.3 Structural Modeling 44 Sequential Logie . 4.4.1 Registers. 4.4.2 Resetiable Registers. 4.4.3, Enabled Registers 444 Multiple Registers 445 Latches 4.5 More Combinational Logie . 4.5.1 Case Statements 45.2 If Statements. 4.5.3. Truth Tables with Don't Care 4.5.4 Blocking and Nonblocking Assignments. 4.6 Finite State Machines. 4.7 Data Types .. 4.7.1 SystemVerilog 472 VHDL 4.8 Parameterized Modules. 49 Testbenches 4.10 Summary Exercises Interview Questions Chapter 5 Digital Building Blocks. . 5.1 Introduction . : 5.2. Arithmetic Circuits... 5.2.1 Addition. 5.2.2 Subtraction . 171 wi wi 172, 173 17s 17s 178 178 179 180 - 182 - 183 - 184 - 186 - 186 - 188 - 191 - 191 - 192 - 194 - 195 = 196 = 196 - 199 = 200 = 203 = 203 - 207 2 = 212 - 213 . 215 = 218 - 222 - 224 - 235 237 237 237 237 244Comparators... ALU vee eeeeceees Shifters and Rotators Multiplication. Division «2.20... 2.8 Further Reading. 5.3. Number Systems .....-.-sceeceseeeee 5.3.1. Fixed-Point Number Systems . 5.3.2. Floating-Point Number Systems. . 5.4 Sequential Building Blocks ........2.+.++ S41 Counters.......0. S42 Shift Registers. 5.5 Memory Arrays. 5.5.1 Overview . 2 Dynamic Randoms Access Memory (DRAM). 3 Static Random Access Memory (SRAM) . 4 Area and Delay 5 Register Files. 6 7 8 Read Only Memory (ROM) . Logic Using Memory Arrays. Memory HDL « gic Arrays. . Programmable Logic Array (PLA). Field Programmable Gate Array (FPGA) 56 5.7 Summary. Exercises . Interview Questions Chapter 6 Architecture. . 6.1 Introduction... 6.2 Assembly Language 6.2.1 Instruction 6.2.2 Operands: Registers, Memory, and Constants 6.3 Programming . Program Flow. Logical, Shift, and Multiply Instructions. Branching. Conditional Statements . Getting Loopy « Arrays... Function Calls « Pseudoinstructions . 245 247 251 253 254 255 256 256 257 261 261 262 = 265 = 265 - 267 - 268 = 268 = 269 = 269 = 271 = 272 = 272 = 275 - 276 = 282 - 283 = 285 - 297 299 - 299 = 300 - 301 - 302 = 308 = 308 = 308 -3it - 313 - 315 - 317 - 320 - 330 xitixiv 64 65 66 67 68 69 Chapter 7 Microarchitecture 7A ‘Machine Language ... 6.4.1 R-Type Instructions. 6.4.2 Type Instructions . 6.4.3 S/B-Type Instructions . 6.4.4 U/f-Type Instructions . 6.4.5 Immediate Encodings. 6.4.6 Addressing Modes... 6.4.7 Interpreting Machine Language Code . 6.4.8 The Power of the Stored Program. Lights, Camera, Action: Compiling, Assembling, and Loading. 6.5.1 The Memory Map 65.2 Assembler Directives. 65.3 Compiling . 65.4 Assembling 65.5 Linking 65.6 Loading . ‘Odds and Ends 6.6.1 Endianness 6.6.2 Exceptions. 6.6.3 Signed and Unsigned Instructions. 6.6.4 Floating-Point Instructions . 6.6.5 Compressed Instructions. Evolution of the RISC-V Architecture . 6.7.1 RISC-V Base Instruction Sets and Extensions 6.7.2 Comparison of RISC-V and MIPS Architectures . 6.7.3 Comparison of RISC-V and ARM Architectures. Another Perspective: x86 Architecture 6.8.1 x86 Registers 6.8.2 x86 Operands. 6.8.3 Status Flags. 6.84 x86 Instructions......... 6.8.5 x86 Instruction Encoding 6.8.6 Other x86 Peculiarities... 6.8.7 The Big Picture. . Summary. foe Exercises . : Interview Questions . Introduction. 71d 7.1.2 Design Process. 7.1.3 Microarchitectures. - 332 - 332 - 334 - 336 - 338 - 340 - 341 - 342 - 343 - 344 = 346 = 348 = 350 - 353 = 355 - 355 = 355 - 356 = 360 - 361 = 362 = 363 - 364 = 365 = 365 - 366 - 366 - 367 - 369 369 371 372, 373 374 375) 390 = 393 = 393 = 393 = 394 = 39672 73 74 75 76 77 78 79 Chapter 8 Memory Systems. 81 8.2 83 Performance Analysi Single-Cycle Processor 7.3.1 Sample Program. 7.3.2. Single-Cycle Datapath 7.3.3 Single-Cycle Control. 7.3.4 More Instructions 7.3.5. Performance Analysi Multicycle Processor . 7.4.1 Multicycle Datapath 7.4.2 Multicycle Control . 7.4.3 More Instructions 7.4.4 Performance Analysis Pipelined Processor. 7.5.1 Pipelined Datapath . 7.5.2 Pipelined Control 75.3 Hazards .. 7.5.4 Performance Analysis HDL Representation . 7.6.1 Single-Cycle Processor 7.6.2 Generic Building Blocks 7.6.3 Testbench. Advanced Microarchitecture 7.7.1 Deep Pipelines . Micro-Operations Branch Prediction Superscalar Processors Out-of Order Processor. Register Renaming . Multithreading . Multiprocessors Real-World Perspective: Evolution of RISC-V Microarchitecture . Summary... Exercises «2.2... Interview Questions BURGROR Introduction .. Memory System Performance Analysis . Caches... What Data is Held in the Cache? How is Data Found? What Data is Replaced: Advanced Cache Design - 397 = 398 - 399 - 399 - 407 - 410 - 412 - 415 - 416 ~ 422 - 432 - 435 - 439 . 441 - 443 - 443 » 454 - 456 . 487 - 461 - 464 - 468 - 468 - 469 - 470 - 472 - 473 . 476 . 478 . 479 482 486 488 497 - 499 - 499 = 503 = 505 = 505 = 506 - 514 - S15 xvxvi ‘CONTENTS 8.4 Virtual Memory. 8.4.1 Address Translation, 8.4.2 The Page Table. 8.4.3 The Translation Lookaside Buffer. 8.4.4 Memory Protection. 8.4.5 Replacement Policies. 8.4.6 Multilevel Page Tables 8.5 Summary - 519 - 522 - 523 - 525 - 526 = 827 = 827 - 530 Epilogue. + 530 Exercises + 532 Interview Questions : 541 Chapter 9 Embedded 1/0 Systems . 542 9.1 Introduction ....... 542 Chapter 9 is avaiable 2s an online supplement. 542.01 9.1 Introduction = 542.01 9.2. Memory-Mapped V/O. ... 2542.01 9.3 Embedded I/O Systems . 1542.03 9.31 RED-V Board.. 2542.03 9.3.2 PE310-G002 System-on-Chip - 1542.05 9.3.3 General-Purpose Digital /O . © 542.05 9.34 Device Drivers .. : 542.010 9.3.5 Serial 1/0 542.014 9.3.6 Timers...... 542.029 9.3.7 Analog /O . 542.030 9.3.8 Interrupts. 542.039 9.4 Other Microcontroller Peripherals 542.043 94.1 Character LCDs. 542.043 9.4.2 VGA Monitor 542.045 9.4.3 Bluetooth Wireless Communication .........0.. 542053 9.4.4 Motor Control . - 542.054 9.5 Summary - 542.064 Appendix A Digital System Implementation . 2 543 A.1 Introduction . . 543 Appendix A is available as an online supplement... » $43.01 A.1 Introduction. 2543.01 A2 74xx Logic +543.e1 A21 Logic Gates +543.02 A2.2 Other Functions. 543.02-543.02 -543.62 -543.06 -543.67 -543.69 -543.69 - 543.15 A.3 Programmable Logic . A3.1_ PROMs A3.2_ PLAs. A3.3. FPGAs. A4 Application-Specific Integrated Circuits AS Datasheets. . A.6 Logic Families A.7 Switches and Light-Emitting Diodes . «543.017 ATL Switches - 543.017 A7.2_LEDs - 543.018 A.8 Packaging and Assembly. + 543.019 A.8.1 Packages: + 543.019 A8.2 Breadboards . ~ $43.€20 A8.3. Printed Circuit Boards = 543.020 AS4 Putting It All Together = 543.623 A.9 Transmission Lines = 543.023 9.1 Matched Termination . » 543.024 9.2 Open Termination. ~ 543.026 9.3. Short Termination + 543.027 94 Mismatched Termination + 543.027 A.9.5 When to Use Transmission Line Models ........ 543.30 A.9.6 Proper Transmission Line Terminations ........ 543.30 A9.7 Derivation of Zo.. = 543.632 A9.8 Derivation of the Reflection Coefficient = 543.633 A9.9 Putting It All Together ~ 543.034 A.10 Economics, = 543.035 Appendix B RISC-V Instruction Set Summary .. . 544 Appendix C C Programming . - 545 Cl Introduction = 545 ‘Appendix ¢ is available as an online supplement... 545.1 G.l_ Introduction 2545.1 2. Welcome to C. 2545.03 C21 C Program Dissection. 545.03 C.2.2 Running a C Program. 545.04 3 Compilation... 545.05 C31 Comments 545.05 C32 Aaetine, 2545.05 C33 include. 545.06 xviixviii C4 cs ce C7 C8 cy c.10 ca Further Reading Variables C41 Primitive Data Types 4.2. Global and Local Variables. 4.3 Initializing Variables Operators . Funetion Calls . Control-Flow Statements . 7.1 Conditional Statements 7.2 Loops. More Data Types. 8.1 Pointers 8.2 Arrays. 8.3 Characters . C84 Strings. C85 Structures. C86 typed 8.7 Dynamic Memory Allocation. C88 Linked Lists . ‘Compiler and Command Line Options C.10.1 Compiling Multiple C Source Files C.10.2. Compiler Options C.10.3. Command Line Arguments. ‘Common Mistakes ... 545.07 -545.08 -545.09 - 545.e11 - 545.e11 - 545.015 = 545.016 - 545.017 = 545.19 - 545.021 - 545.21 - $45.23 » 545.027 + 945.027 + $45.e29 + 945.031 + 945.032 + 945.033 + 545.035 + 545.035 + 545.040 + 945.042 + 945.042 + 945.043 + 945.043 + 945.043 + 945.044 + 945.044 . 947 - 549Preface This book is unique in its treatment in that it presents digital logic design from the perspective of computer architecture, starting at the beginning with 1's and 0's and leading through to the design of a microprocessor. We believe that building a microprocessor is a special rite of passage for engineering and computer science students. The inner workings of a processor seem almost magical to the uninitiated yet prove to be straightforward when carefully explained. Digital design in and of itself is a powerful and exciting subject. Assembly language programming unveils the inner language spoken by the processor. Microarchitecture is the link that brings it all together. The first two versions of this increasingly popular text cover the MIPS and ARM architectures. As one of the original Reduced Instruction Set Computing architectures, MIPS is clean and excep- tionally easy to understand and build. MIPS remains an important architecture, as it has inspired many of the subsequent architectures, including RISC-V, The ARM architecture has exploded in popu- larity over the past several decades because of its efficiency and rich ecosystem. More than 50 billion ARM processors have been shipped, and more than 75% of humans on the planet use products with ARM processors. Over the past decade, RISC-V has emerged as an increasingly important architecture, both pedagogically and commercially. As the first widely used open-source computer architecture, RISC-V offers the simplicity of MIPS with the flexibility and features of modern Processors. Pedagogically, the learning objectives of the MIPS, ARM, and RISC-V editions are identical. The RISC-V architecture has a number of features, including extendibility and compressed instructions, that con- tribute to its efficiency but add a small amount of complexity. The three microarchitectures are also similar, with MIPS and RISC-V architectures sharing many similarities. We expect to offer MIPS, ARM, and RISC-V editions as long as the market demands. xixxx FEATURES Side-by-Side Coverage of SystemVerilog and VHDL Hardware description languages (HDIs) are at the center of modern digital design practices. Unfortunately, designers are evenly split between the two dominant languages, SystemVerilog and VHDL. This book introduces HDLs in Chapter 4 as soon as combinational and sequential logic design has been covered. HDLs are then used in Chapters 5 and 7 to design larger building blocks and entire processors. Nevertheless, Chapter 4 can be skipped and the later chapters are still accessible for courses that choose not to cover HDLs. This book is unique in its side-by-side presentation of SystemVerilog and VHDL, enabling the reader to learn the two languages. Chapter 4 describes principles that apply to both HDLs, and then provides language- specific syntax and examples in adjacent columns. This side-by-side treatment makes it easy for an instructor to choose either HDL and for the reader to transition from one to the other, either in a class or in professional practice. RISC-V Architecture and Microarchitecture Chapters 6 and 7 offer in-depth coverage of the RISC-V architecture and microarchitecture. RISC-V is an ideal architecture because it is a real architecture shipped in an increasing number of commercial products, yet it is streamlined and easy to learn. Moreover, because of its popularity in the commercial and hobbyist worlds, simulation and development tools exist for the RISC-V architecture. Real-World Perspectives In addition to the real-world perspective in discussing the RISC-V architecture, Chapter 6 illustrates the architecture of Intel x86 pro- cessors to offer another perspective. Chapter 9 (available as an online supplement) also describes peripherals in the context of SparkFun’s RED-V RedBoard, a popular development board that centers on SiFive’s Freedom E310 RISC-V processor. These real-world perspective chapters show how the concepts in the chapters relate to the chips found in many PCs and consumer electronics. Accessible Overview of Advanced Microarchitecture Chapter 7 includes an overview of modern high-performance micro- architectural features, including branch prediction, superscalar, and out-of-order operation, multithreading, and multicore processors. ‘Thetreatment is accessible to a student in a first course and shows how the microarchitectures in the book can be extended to modern processors. End-of-Chapter Exercises and Interview Questions ‘The best way to learn digital design is to do it. Each chapter ends with numerous exercises to practice the material. The exercises are followed by a set of interview questions that our industrial colleagues have asked students who are applying for work in the field. These questions pro- vide a helpful glimpse into the types of problems that job applicants will typically encounter during the interview process. Exercise solutions are available via the book’s companion and instructor websites. ONLINE SUPPLEMENTS Supplementary materials are available online at ddcabook.com or the publisher's website: https://www.lsevier.com/books-and-journals/ ‘book-companion/9780128200643. These companion sites (accessible to all readers) include the following: » Links to video lectures » Solutions to odd-numbered exercises > Figures from the text in PDF and PPTX formats Links to professional-strength computer-aided design (CAD) tools from Intel” > Instructions on how to use Platform[O (an extension of Visual Studio Code) to compile, assemble, and simulate C and assembly code for RISC-V processors Hardware description language (HDL) code for the RISC-V processor Intel’s Quartus helpful hints Lecture slides in PowerPoint (PPTX) format Sample course and laboratory materials List of errata ‘The instructor site (accessible to instructors who register at https:// inspectioncopy.elsevier.com) includes the following: » Solutions to all exercises > Laboratory solutions ‘This book also has a companion Massive Open Online Course (MOOC) through EdX. The course includes video lectures, interactive practice xxixxii problems, and interactive problem sets and labs. The MOOC is divided into two parts: Digital Design (ENGR 85A) and Computer Architecture (ENGR8SB} offered by HarveyMuddX (on EdX, search for “Digital Design HarveyMuddX” and “Computer Architecture HarveyMuddX”). FAX does not charge for access to the videos but does charge for the inter- active exercises and certificate. BAX offers discounts for students with financial need. HOW TO USE THE SOFTWARE TOOLS IN A COURSE Intel's Quartus Software The Quartus software, either Web or Lite Edition, is a free version of Intel’s professional-strength Quartus™ FPGA design tools. It allows students to enter their digital designs in schematic or using either the SystemVerilog or the VHDL hardware description language (HDL). After entering the design, students can simulate their circuits using the ‘ModelSim™-Intel FPGA Edition or Starter Edition, which is available with Intel’s Quartus software. Quartus also includes a built-in logic synthesis tool that supports both SystemVerilog and VHDL. ‘The difference between the Web or Lite Edition and the Pro Edition is that the Web or Lite Edition supports a subset of the most common Altera FPGAs. The free versions of ModelSim degrade performance for simulations with more than 10,000 lines of HDL, whereas the professional version of ModelSim does not. Platformio PlatformlO, which is an extension of Visual Studio Code, serves as a soft- ware development kit (SDK) for RISC-V, With the explosion of SDKs for each new platform, PlatformlO has streamlined the process of program- ‘ming and using various processors by providing a unified interface for a large number of platforms and devices. It is available as a free download and can be used with SparkFun’s RED-V RedBoard, as described in the labs provided on the companion website. PlatformlO provides access to a commercial RISC-V compiler and allows students to write both C and assembly programs, compile them, and then run and debug them on SparkFun’s RED-V RedBoard (see Chapter 9 and the accompanying labs). Venus RISC-V Assembly Simulator ‘The Venus Simulator (available at: https://www:kvakil.me/venus/) is a web-based RISC-V assembly simulator. Programs are written (or copy/ pasted) in the Editor tab and then simulated and run in the Simulator tab, Registers and memory contents can be viewed as the program runs.‘The companion site includes links to a series of labs that cover topics from digital design through computer architecture. The labs teach stu- dents how to use the Quartus tools to enter, simulate, synthesize, and implement their designs. ‘The labs also include topics on C and assem- bly language programming using PlatformIO and SparkFun’s RED-V RedBoard. After synthesis, students can implement their designs using the Altera DE2, DE2-115, DEO, or other FPGA board. The labs are written to target the DE2 or DE-115 boards. These powerful and competitively priced boards are available from de2-115.terasic.com. The board con- tains an FPGA that can be programmed to implement student designs. We provide labs that describe how to implement a selection of designs on the DE2-115 board using the Quartus software. To run the labs, students will need to download and install Intel's Quartus Web or Lite Edition and Visual Studio Code with the PlatformIO extension. Instructors may also choose to install the tools ‘on lab machines. The labs include instructions on how to implement the projects on the DE2/DE2-115 board. The implementation step may be skipped, but we have found it of great value. We have tested the labs on ‘Windows, but the tools are also available for Linux. RVfpga RISC-V FPGA, also referred to as RVEpga, is a free two-course sequence that can be completed after learning the material in this book. The first course shows how to target a commercial RISC-V core to an FPGA, pro- gram it using RISC-V assembly or C, add peripherals to it, and analyze and modify the core and memory system, including adding instructions to the core. This course uses the open-source SweRVolf system-on-chip (SoC) (https://github.com/chipsalliance/Cores-SweRVolf), which is based ‘on Western Digital’s open-source commercial SweRV EHII core (https:// ‘www.westerndigital.com/companylinnovations/risc-v). The course also shows how to use Verilator, an open-source HDL. simulator, and Western Digital’s Whisper, an open-source RISC-V instruction set simulator (ISS). RVfpga-SoC, the second course, shows how to build an SoC based on SweRVolf using building blocks such as the SweRV EH1 core, inter- connect, and memories. The course then guides the user in loading and running the Zephyr operating system on the RISC-V SoC. All neces- sary software and system source code (Verilog/SystemVerilog files) are free, and the courses may be completed in simulation, so no hardware is required. RVfpga materials are freely available with registration from the Imagination Technologies University Programme: https://university. imgtec.com/rvfpgal xxiii