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ARM Lecture 3

The document discusses exceptions and interrupts in the ARM Cortex M3/M4 processors, highlighting that the NVIC manages these events and supports features like nested interrupts and dynamic priority changes. It details the configurations available for each interrupt through the NVIC and notes the behavior of pending and active interrupts. Additionally, it provides guidance on defining groups and assigning priorities for interrupts.

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26 views17 pages

ARM Lecture 3

The document discusses exceptions and interrupts in the ARM Cortex M3/M4 processors, highlighting that the NVIC manages these events and supports features like nested interrupts and dynamic priority changes. It details the configurations available for each interrupt through the NVIC and notes the behavior of pending and active interrupts. Additionally, it provides guidance on defining groups and assigning priorities for interrupts.

Uploaded by

ahmed.hecham307
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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This material is developed by IMTSchool for educational use only

All copyrights are reserved


Exceptions are events which are generated asynchronously either from inside the
core itself or from the external peripherals. In general any even that disturb the
normal behavior of the processor is an exception.

Interrupts are used with exceptions from the external peripherals. In other words
interrupt is nothing but an exception external to the processor core.

ARM Cortex M3/M4 Supports 255 exceptions

15 System Exception 240 Interrupts


The Nested Vectored Interrupt Controller NVIC is an integrated part of the Cortex
M3/M4 processor. It is closely linked to the CPU core logic and Its control
registers are accessible as memory mapped. It provides the following features:

1. Nested interrupt support


2. Vectored interrupt support
3. Dynamic priority changes support
4. Reduction of interrupt latency
5. Interrupt masking

The NVIC controls the interrupts as well as the system exceptions. The NVIC can be
accessed in the System Control Space (SCS) address range, which is memory
location 0xE000E000. Most of the interrupt control/status registers are accessible
only in privileged mode, except the Software Trigger Interrupt register (STIR),
which can be set up to be accessible in user mode.
SysTick Timer Processor Core

NMI

Peripherals NVIC
System
Exceptions
IRQn

Cortex M3/M4 Processor


Each interrupt has a set of basic configurations through NVIC which are:

1. Enable .
.
2. Clear Enable .

3. Set Pending 0xE000E400 PRI0`

.
4. Clear Pending .
.
5. Active status 0xE000E300 IABR0

6. Priority level .
.
.
0xE000E280 CLRPEND0

.
.
.
0xE000E200 SETPEND0

.
.
.
ICER0
0xE000E180
.
.
.
0xE000E100 ISER0
Note
If a pending interrupt is enabled, the NVIC activates the interrupt based on its
priority. If an interrupt is not enabled, asserting its interrupt signal changes the
interrupt state to pending, but the NVIC never activates the interrupt, regardless of
its priority.
Note
Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
Note
Writing 1 to the ISPR bit corresponding to an interrupt that is pending:
– has no effect.
Writing 1 to the ISPR bit corresponding to a disabled interrupt:
– sets the state of that interrupt to pending.
Note
A bit reads as 1 if the status of the corresponding interrupt is active or active and
pending.
Note
A bit reads as 1 if the status of the corresponding interrupt is active or active and
pending.
1- Define Number of Groups and Number of Sub Priorities
1- Assign a priority for each interrupt
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