RISC

and
CISC

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 Outline
• RISC history
• Pipelining
• CISC Architecture

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 RISC
Reduced Instruction Set Computers
• Microprocessor architecture
• Designed to perform a set of smaller
computer instructions so that it can operate
at higher speeds

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 Before the RISC era
• Compilers were hard to build especially for machines with
registers
– Make machine do more work than software
– Have instructions load and store directly to memory (memory-
to-memory operations)
• Software costs were rising and hardware costs were
dropping
– Move as much functionality to hardware
• Magnetic core memory was used as main memory which
was slow and expensive
– Minimize assembly code
• Complex Instruction Set Computers (CISC)
– Use complex instructions “MULT”, “ADD”…

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 Technology was advancing
• Compilers were improving
– Simple compilers found it difficult to use more complex
instructions
– Optimizing compilers rarely needed more powerful
instructions
• Caches
– allowed main memory to be accessed at similar speeds to
control memory
• Semiconductor memory was replacing magnetic core
memory
– Reduced performance gap between control and main
memory

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 RISC Approach
• Use only simple instructions that can be
executed within one clock cycle
– Fewer transistors for instructions = more registers
• Pipelining
• Register-to-register operations
– Operand reuse
– Reduction of load/store

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 Pipelining
Sequential
IF ID OF OE O S
IF ID O F OE OS
Clock Cycle IF ID O F OE OS

Pipelined
IF ID OF OE O S IF – Instruction Fetch
ID – Instruction Decode
IF ID O F OE OS
Clock Cycle

OF – Operand Fetch
IF ID OF OE O S OE – Operand Execution
OS – Operation Store

Time
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 Pipelining
Data Dependency
IF – Instruction Fetch
IF ID OF OE OS
ID – Instruction Decode
IF ID OF OE OS OF – Operand Fetch
OE – Operand Execution
OS – Operation Store

IF ID OF OE OS

Branch Address Dependency

IF ID O F OE OS
IF ID O F OE OS

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 Pipelining
• Data dependencies can be addressed by
reordering the instructions when possible
(compiler)
• Performance degradation from branches can
be reduced by branch prediction or executing
instructions for both branches until the
correct branch is identified

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 Other Advantages
• New microprocessors can be developed and
tested more quickly if being less complicated
is one of it’s aims
• Smaller instruction sets are easier for compiler
programmers to use

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 What is CISC?

 Definition: Pronounced "sisk" and standing for Complex

Instruction Set Computer, is a Microprocessor Architecture
that aims at achieving complex operations with single
instructions and favors the richness of the instruction set
(typically as many as 200 unique instructions) over the
speed with which individual instructions are executed.
Why should I know about CISC?
 Today’s computers still use processors which are based on CISC
designs
 It has been a prominent architecture since 1978
 Most Emerging Processor designs combine features of CISC
and RISC to create better designs.

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 Architecture
A typical x86 Architecture

Intel 8086 Architecture, the 1st member of x86 family

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 Characteristics
o CISC are Mostly Von Neumann Architecture (There are few exceptions)
o Same bus for program memory, data memory, I/O, registers, etc
o Generally Micro-coded ,Variable length instructions
o Segmentation is possible with Segment Register s like DS, ES and an offset which
can be common to all segments.
o Many powerful instructions are supported, making the assembly language
programmer’s job much easier.
o Physical Memory Extension Possible

Addressing modes
o Register Addressing Mode
o Memory Addressing Modes
o Displacement Only Addressing Mode
o Register Indirect Addressing Modes
o Indexed Addressing Modes
o Based Indexed Addressing Modes
o Based Indexed Plus Displacement Addressing

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CISC Vs RISC
Example Program

Main Memory

General Purpose
Registers

ALU

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 Consider following task of Multiplication

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Operands:

M[2:3] = operand 1 (15)

M[5:2] = operand 2(20)

Task : Multiplication

Result:

M[2:3] <= result 17

 The CISC Approach
 Operations:
1. Loads the two operands into
 Instruction : separate registers
2. Multiplies the operands in the
MULT 2:3, 5:2 execution unit
3. Then stores the product in the
some temporary register
4. Stores value back to memory
location 2:3

• MULT is what is known as a "complex instruction."

• Operates directly on the computer's memory banks
• Does not require the programmer to explicitly call any loading
or storing functions.
• closely resembles a command in a higher level language.
e.g. a ‘C’ statement "a = a * b."
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The RISC Approach  Operations:
1. Load operand1 into register A
 Instructions :
2. Load operand2 into register B
3. Multiply the operands in the
LW A, 2:3 execution unit and store result
LW B, 5:2 in A
MULT A, B 4. Store value of A back to
memory location 2:3
SW 2:3, A

• These set of Instructions is known as a “Reduced Instructions."

• Cannot Operate directly on the computer's memory banks
• Requires the programmer to explicitly call any loading or
storing functions.
• RISC processors only use simple instructions that can be
executed within one clock cycle
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• CISC • RISC
• Primary goal is to complete  Primary goal is to speedup
individual instruction
a task in as few lines of
assembly as possible  Emphasis on software
• Emphasis on hardware  Single-clock,
reduced instruction only
• Includes multi-clock
 Register to register:
complex instructions "LOAD" and "STORE"
• Memory-to-memory: are independent instructions
"LOAD" and "STORE"  Large code sizes
 Low cycles per second
incorporated in instructions
 Equal length instructions which
• Small code sizes make pipelining possible
• High cycles per second
• Variable length Instructions
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 Use of RISC today
• X86 is one of the only chips that retain CISC
architecture
– Large base of proprietary PC applications were written
for X86 or compiled into X86 machine code
– Intel was able to spend vast amounts of money on
processor development to offset the RISC advantages
enough to maintain PC market share
• CISC and RISC architectures are nearly
indistinguishable
– CISC processors use pipelining and can complete
multiple instructions per cycle
– Transistor technology has allowed more room on
chips allowing RISC to have more CISC like instruction
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 The Performance Equation
The following equation is commonly used for expressing a
computer's performance ability:

1 2

The CISC approach

• minimizes the number of instructions per program (2)
• sacrificing the number of cycles per instruction. (1)

RISC does the opposite

• reduces the cycles per instruction (1)
• sacrificing number of instructions per program (2)

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 FAQs
Which one is faster?
Well, it is commonly accepted that RISC ISA's should make
computers faster.
The main reason why is because RISC computers figure out more
words in a shorter amount of time due to pipelining.
So why isn't my computer a RISC?

• CISC ISA's were implemented in the first personal computers

• With more people buying computers, CISC isa's became more prominent
• Software (especially OS) was developed and "translated" so that personal
computers speaking x86 would be able to interact with its users
• Because there was so much software written for computers "speaking"
x86, people continued to buy those computers.
• If we tried to switch to another ISA, we would not have all of the software
choices we have now.
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So why would someone want to develop another ISA?

• x86 (and CISC) make poor use of the faster hardware we have
now.
• Another problem with x86 is that people have been trying to
make it faster for a long time, at least 20 years, and after a while
you have found most of the ways to speed the computer up
significantly

Why don't we just switch to RISC?

• Although it is not used on your desktop PC, RISC ISA's are

implemented in many mainframe computers.
• Programmers have been trying to make RISC faster for a long
time, and they have found many of the areas in which it is able
to be sped up significantly.
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