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DRAM Subsystem Explanation

DRAM is organized into hierarchical structures including bank groups, banks, rows, and columns, with data transfer sizes determined by its width (x4, x8, x16) and page sizes varying accordingly. Read and write operations involve activating rows and accessing columns, with a DDR controller optimizing address conversions and requests, while the DDR PHY ensures signal integrity. Key standards include the DFI for interface and JEDEC specifications for DDR4 memory.

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26 views2 pages

DRAM Subsystem Explanation

DRAM is organized into hierarchical structures including bank groups, banks, rows, and columns, with data transfer sizes determined by its width (x4, x8, x16) and page sizes varying accordingly. Read and write operations involve activating rows and accessing columns, with a DDR controller optimizing address conversions and requests, while the DDR PHY ensures signal integrity. Key standards include the DFI for interface and JEDEC specifications for DDR4 memory.

Uploaded by

Arun Chikkaraju
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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### DRAM Concepts and Sub-System Explanation

#### DRAM Organization

- DRAM is organized into **bank groups**, **banks**, **rows**, and **columns**.

- Each operation involves accessing a specific bank group, bank, row, and column.

#### DRAM Width and Page Size

- **DRAM Width (x4, x8, x16)** determines the size of data transfers:

- **x4 DRAM**: 4 data pins (DQ[3:0]).

- **x8 DRAM**: 8 data pins (DQ[7:0]).

- **x16 DRAM**: 16 data pins (DQ[15:0]).

- **Page Size**: Number of bits per row loaded into Sense Amplifiers upon row activation:

- **x4 DRAM**: 512 bytes.

- **x8 DRAM**: 1 KB.

- **x16 DRAM**: 2 KB.

#### Addressing in DRAM

- **Row Address**: Number of rows = 2^number_of_row_address_bits.

- **Column Address**: Always fixed at 10 bits (1024 columns).

- Logical Address is converted to Physical Address by the Controller.

#### Read and Write Operations

- **READ Operation**:

1. **ACTIVATE** command selects the row.

2. **READ (RDA)** command accesses columns, optionally with auto-precharge.

3. Data is transferred in bursts (BL8 = 8 chunks).


- **WRITE Operation**:

1. **ACTIVATE** opens the row.

2. **WRITE (WR)** to columns; subsequent WR commands do not require activation.

3. **WRA** can be used for auto-precharge.

#### DRAM Sub-System

1. **DDR Controller**: Converts logical addresses to physical addresses and optimizes requests.

2. **DDR PHY**: Handles low-level signaling and ensures signal integrity.

3. **DRAM Memory**: Stores and retrieves data.

#### Optimization and Standards

- **DFI (DDR PHY Interface)**: Standard between Controller and PHY.

- **JEDEC Specification**: Defines DDR4 memory interface.

### Key Takeaways

- DRAM is hierarchical and burst-oriented.

- Controllers optimize bandwidth by re-ordering requests.

- PHY handles analog signaling for reliable data transfer.

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