////////////////////////// SEQ ITEM ////////////////////////////
class addr_seq_item extends uvm_sequence_item;
`uvm_object_utils_begin(addr_seq_item)
`uvm_field_int(addr,UVM_DEFAULT)
`uvm_field_int(data,UVM_DEFAULT)
`uvm_object_utils_end
rand bit [7:0] addr;
rand bit [7:0] data;
function new(string name = "addr_seq_item");
super.new(name);
endfunction
constraint addr_c {soft addr inside {[0:24]};}
endclass
/////////////////////// SEQUENCE ///////////////////////////////
class base_sequence extends uvm_sequence#(addr_seq_item);
`uvm_object_utils(base_sequence)
addr_seq_item req;
function new(string name = "base_sequence");
super.new(name);
endfunction
task body();
repeat(1)
begin
req = addr_seq_item::type_id_create("req");
start_item(req);
req.randomize();
finish_item(req);
end
endtask
endclass
///////////////////////// SEQUENCER /////////////////////////////
class addr_sequencer extends uvm_sequencer#(addr_seq_item);
`uvm_component_utils(addr_sequencer)
function new(string name , uvm_component parent );
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
endclass
////////////////////////// DRIVER /////////////////////////////////
class addr_driver extends uvm_driver#(addr_seq_item);
`uvm_component_utils(addr_driver)
addr_seq_item req;
virtual addr_intf vif;
function new(string name , uvm_component parent );
super.new(name , parent );
endfunction
function build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db#(virtual addr_intf)::set(null,"*","interface",vif);
endfunction
task run_phase(uvm_phase phase);
// super.run_phase(phase) // confirm this
forever
begin
seq_item_port.get_next_item(req);
drive(req);
seq_item_port.item_done();
end
endtask
task drive(addr_seq_item req);
@(posedge vif.clk)
vif.addr <= req.addr;
vif.data <= req.data;
endtask
endclass
/////////////////////////// MONITOR ///////////////////////////////
class addr_monitor extends uvm_monitor;
`uvm_component_utils(addr_monitor)
virtual addr_intf vif;
addr_seq_item xtn;
uvm_analysis_port #(addr_seq_item) port;
function new(string name , uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db #(virtual addr_intf) :: get(null , "*","interface",vif);
port = new("port",this);
xtn = addr_seq_item::type_id:create("xtn");
endfunction
task run_phase (uvm_phase phase);
forever
begin
@(posedge vif.clk);
xtn.addr = vif.addr;
xtn.data = vif.data;
port.write(xtn);
end
endtask
endclass
////////////////////////// AGENT ///////////////////////////////
class addr_agent extends uvm_agent;
`uvm_component_utils(addr_agent)
addr_driver drv;
addr_monitor mon;
addr_sequencer seqr;
function new(string name , uvm_component parent);
super.new(name ,parent);
endfunction
function void build_phase (uvm_phase phase);
super.build_phase(phase);
drv = addr_driver::type_id::create("drv",this);
mon = addr_monitor::type_id::create("mon",this);
seqr = addr_sequencer::type_id::create("seqr",this);
endfunction
function void connect_phase (uvm_phase phase);
super.connect_phase(phase);
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction
endclass
////////////////////////// SCOREBOARD //////////////////////////
class addr_scoreboard extends uvm_scoreboard;
`uvm_component_utils(addr_scoreboard)
virtual addr_intf vif;
uvm_analysis_imp #(addr_seq_item,addr_scoreboard) collected_port;
function new(string name , uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
collected_port = new("collected_port",this);
endfunction
task cmp();
forever
begin
end
entask
function write(addr_seq_item req);
endfunction
endclass
//////////////////////// ENVIRONMENT //////////////////////////
class addr_env extends uvm_env;
`uvm_component_utils(addr_env)
addr_agent agent;
addr_scoreboard scb;
function new(string name , uvm_component parent );
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent = addr_agent::type_id::create("agent",this); // confirm this
scb = addr_scoreboard::type_id::create("scb",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase); /// confirm this
agent.mon.port.connect(scb.item_collected);
endfunction
endclass
/////////////////////////// TEST //////////////////////////////
class addr_base_test extends uvm_test;
`uvm_component_utils(addr_base_test)
addr_env env;
addr_seq seq;
function new(string name , uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = addr_env::type_id::create("env",this);
endfunction
function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction
task run_phase (uvm_phase phase);
seq = addr_seq::type_id::create("seq",this);
phase.raise_objection(this);
repeat(1)
begin
seq.randomize();
seq.start(env.agent.seqr);
end
phase.drop_objection(this);
endtask
endclass
////////////////////// TOP //////////////////////////////
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "addr_intf.sv"
`include "addr_package.sv"
module top;
import addr_package::*;
//
initial
begin
$dumpfile("file.vcd");
$dumpvars;
end
initial
begin
uvm_config_db #(virtual addr_intf)::set(null,"*","interface",intf);;
run_test();
end
endmodule
//////////////////////////////////////////////////////////
