IS42/45R86400D/16320D/32160D

IS42/45S86400D/16320D/32160D
16Mx32, 32Mx16, 64Mx8
MAY 2015
512Mb SDRAM
device OVERVIEW
ISSI's 512Mb Synchronous DRAM achieves high-speed
FEATURES data transfer using pipeline architecture. All inputs and
• Clock frequency: 200, 166, 143 MHz outputs signals refer to the rising edge of the clock input.
• Fully synchronous; all signals referenced to a The 512Mb SDRAM is organized as follows.
positive clock edge
PACKAGE INFORMATION
• Internal bank for hiding row access/precharge
IS42/45S32160D IS42/45S16320D IS42/45S86400D
• Power supply: Vdd/Vddq = 2.3V-3.6V
IS42/45R32160D IS42/45R16320D IS42/45R86400D
IS42/45SxxxxxD - Vdd/Vddq = 3.3V 4M x 32 x 4 8M x 16 x 4 16M x 8 x 4
IS42/45RxxxxxD - Vdd/Vddq = 2.5 banks banks banks

• LVTTL interface 90-ball TF-BGA 54-pin TSOP-II 54-pin TSOP-II

54-ball TF-BGA
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence: KEY TIMING PARAMETERS
Sequential/Interleave Parameter -5 -6 -7 Unit
• Auto Refresh (CBR) Clk Cycle Time
• Self Refresh CAS Latency = 3 5 6 7 ns
CAS Latency = 2 10 10 7.5 ns
• 8K refresh cycles every 64 ms
Clk Frequency
• Random column address every clock cycle CAS Latency = 3 200 167 143 Mhz
• Programmable CAS latency (2, 3 clocks) CAS Latency = 2 100 100 133 Mhz
• Burst read/write and burst read/single write Access Time from Clock
operations capability CAS Latency = 3 5.0 5.4 5.4 ns
CAS Latency = 2 6 6 5.4 ns
• Burst termination by burst stop and precharge
command
• Packages: ADDRESS TABLE
x8/x16: 54-pin TSOP-II, 54-ball TF-BGA (x16 only) Parameter 16M x 32 32M x 16 64M x 8
x32: 90-ball TF-BGA Configuration 4M x 32 x 4 8M x 16 x 4 16M x 8 x 4
• Temperature Range: banks banks banks
Commercial (0oC to +70oC) Bank Address BA0, BA1 BA0, BA1 BA0, BA1
Industrial (-40oC to +85oC) Pins
Automotive, A1 (-40oC to +85oC) Autoprecharge A10/AP A10/AP A10/AP
Automotive, A2 (-40oC to +105oC) Pins
Row Address 8K(A0 – A12) 8K(A0 – A12) 8K(A0 – A12)
Column 512(A0 – A8) 1K(A0 – A9) 2K(A0 – A9,
Address A11)
Refresh Count
Com./Ind./A1 8K / 64ms 8K / 64ms 8K / 64ms
A2 8K / 16ms 8K / 16ms 8K / 16ms

Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

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DEVICE OVERVIEW
The 512Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE function
random-access memory designed to operate in either 3.3V enabled. Precharge one bank while accessing one of the
Vdd/Vddq or 2.5V Vdd/Vddq memory systems, depending other three banks will hide the precharge cycles and provide
on the DRAM option. Internally configured as a quad-bank seamless, high-speed, random-access operation.
DRAM with a synchronous interface. SDRAM read and write accesses are burst oriented starting
The 512Mb SDRAM (536,870,912 bits) includes an AUTO at a selected location and continuing for a programmed
REFRESH MODE, and a power-saving, power-down number of locations in a programmed sequence. The
mode. All signals are registered on the positive edge of registration of an ACTIVE command begins accesses,
the clock signal, CLK. All inputs and outputs are LVTTL followed by a READ or WRITE command. The ACTIVE
compatible. command in conjunction with address bits registered are
The 512Mb SDRAM has the ability to synchronously burst used to select the bank and row to be accessed (BA0,
data at a high data rate with automatic column-address BA1 select the bank; A0-A12 select the row). The READ
generation, the ability to interleave between internal banks or WRITE commands in conjunction with address bits
to hide precharge time and the capability to randomly registered are used to select the starting column location
change column addresses on each clock cycle during for the burst access.
burst access. Programmable READ or WRITE burst lengths consist of
A self-timed row precharge initiated at the end of the burst 1, 2, 4 and 8 locations or full page, with a burst terminate
option.

FUNCTIONAL BLOCK DIAGRAM (For 8MX16X4 Banks SHOWN)

CLK DQML
CKE DQMH
CS COMMAND DATA IN
RAS DECODER BUFFER
CAS & 16 16
WE CLOCK REFRESH
GENERATOR MODE 2 DQ 0-15
CONTROLLER
REGISTER

13 SELF VDD/VDDQ
DATA OUT
A10 REFRESH Vss/VssQ
BUFFER
A12 CONTROLLER 16 16
A11
A9
A8 REFRESH
A7 COUNTER
A6
A5 8192
A4
ROW DECODER

8192
A3 8192 MEMORY CELL
MULTIPLEXER

A2 8192 ARRAY
13
A1
A0 ROW ROW BANK 0
BA0 ADDRESS ADDRESS
BA1 13
LATCH BUFFER
13 SENSE AMP I/O GATE

1024
(x 16)
COLUMN
ADDRESS LATCH BANK CONTROL LOGIC
10

BURST COUNTER

COLUMN DECODER
COLUMN
ADDRESS BUFFER
10

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PIN CONFIGURATIONS
54 pin TSOP - Type II for x8

VDD 1 54 VSS
DQ0 2 53 DQ7
VDDQ 3 52 VSSQ
NC 4 51 NC
DQ1 5 50 DQ6
VSSQ 6 49 VDDQ
NC 7 48 NC
DQ2 8 47 DQ5
VDDQ 9 46 VSSQ
NC 10 45 NC
DQ3 11 44 DQ4
VSSQ 12 43 VDDQ
NC 13 42 NC
VDD 14 41 VSS
NC 15 40 NC
WE 16 39 DQM
CAS 17 38 CLK
RAS 18 37 CKE
CS 19 36 A12
BA0 20 35 A11
BA1 21 34 A9
A10 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS

PIN DESCRIPTIONS

A0-A12 Row Address Input WE Write Enable

A0-A9, A11 Column Address Input DQM Data Input/Output Mask
BA0, BA1 Bank Select Address Vdd Power
DQ0 to DQ7 Data I/O Vss Ground
CLK System Clock Input Vddq Power Supply for I/O Pin
CKE Clock Enable Vssq Ground for I/O Pin
CS Chip Select NC No Connection
RAS Row Address Strobe Command
CAS Column Address Strobe Command

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PIN CONFIGURATIONS
54 pin TSOP - Type II for x16

VDD 1 54 VSS
DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 VDDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 43 VDDQ
DQ7 13 42 DQ8
VDD 14 41 VSS
DQML 15 40 NC
WE 16 39 DQMH
CAS 17 38 CLK
RAS 18 37 CKE
CS 19 36 A12
BA0 20 35 A11
BA1 21 34 A9
A10 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS

PIN DESCRIPTIONS
A0-A12 Row Address Input WE Write Enable
A0-A9 Column Address Input DQML x16 Lower Byte, Input/Output Mask
BA0, BA1 Bank Select Address DQMH x16 Upper Byte, Input/Output Mask
DQ0 to DQ15 Data I/O Vdd Power
CLK System Clock Input Vss Ground
CKE Clock Enable Vddq Power Supply for I/O Pin
CS Chip Select Vssq Ground for I/O Pin
RAS Row Address Strobe Command NC No Connection
CAS Column Address Strobe Command

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PIN CONFIGURATION
54-ball TF-BGA for x16 (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
package code: B

1 2 3 4 5 6 7 8 9

A
VSS DQ15 VSSQ VDDQ DQ0 VDD
B
DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C
DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D
DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E
DQ8 NC VSS VDD DQML DQ7
F
DQMH CLK CKE CAS RAS WE
G
A12 A11 A9 BA0 BA1 CS
H
A8 A7 A6 A0 A1 A10
J
VSS A5 A4 A3 A2 VDD

PIN DESCRIPTIONS
A0-A12 Row Address Input WE Write Enable
A0-A9 Column Address Input DQML x16 Lower Byte Input/Output Mask
BA0, BA1 Bank Select Address DQMH x16 Upper Byte Input/Output Mask
DQ0 to DQ15 Data I/O Vdd Power
CLK System Clock Input Vss Ground
CKE Clock Enable Vddq Power Supply for I/O Pin
CS Chip Select Vssq Ground for I/O Pin
RAS Row Address Strobe Command NC No Connection
CAS Column Address Strobe Command

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PIN CONFIGURATION
package code: B 90 bALL TF-bga (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)

1 2 3 4 5 6 7 8 9

A
DQ26 DQ24 VSS VDD DQ23 DQ21
B
DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C
VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D
VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E
VDDQ DQ31 NC NC DQ16 VSSQ
F
VSS DQM3 A3 A2 DQM2 VDD
G
A4 A5 A6 A10 A0 A1
H
A7 A8 A12 NC BA1 A11
J
CLK CKE A9 BA0 CS RAS
K
DQM1 NC NC CAS WE DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2

PIN DESCRIPTIONS
A0-A12 Row Address Input WE Write Enable
A0-A8 Column Address Input DQM0-DQM3 x32 Input/Output Mask
BA0, BA1 Bank Select Address Vdd Power
DQ0 to DQ31 Data I/O Vss Ground
CLK System Clock Input Vddq Power Supply for I/O Pin
CKE Clock Enable Vssq Ground for I/O Pin
CS Chip Select NC No Connection
RAS Row Address Strobe Command
CAS Column Address Strobe Command

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PIN FUNCTIONS
Symbol Type Function (In Detail)
A0-A12 Input Pin Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address
A0-A12) and READ/WRITE command (column address A0-A9, A11 (x8); A0-A9
(x16); A0-A8 (x32); with A10 defining auto precharge) to select one location out of
the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
BA0, BA1 Input Pin Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE Input Pin The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS Input Pin The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQM: x8 Input Pin DQx pins control the bytes of the I/O buffers. For example with x16, in read mode,
DQML, DQMH: x16 DQML and DQMH control the output buffer. When DQML or DQMH is LOW, the
DQM0-DQM3: x32 corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when DQML/DQMH is HIGH. This function corresponds
to OE in conventional DRAMs. In write mode, DQML and DQMH control the input
buffer. When DQML or DQMH is LOW, the corresponding buffer byte is enabled,
and data can be written to the device. When DQML or DQMH is HIGH, input data is
masked and cannot be written to the device.
DQ0-DQ7: x8 Input/Output Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
DQ0-DQ15: x16 output after Read commands.
DQ0-DQ31: x32
RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
Vddq Power Supply Pin Vddq is the output buffer power supply.
Vdd Power Supply Pin Vdd is the device internal power supply.
Vssq Power Supply Pin Vssq is the output buffer ground.
Vss Power Supply Pin Vss is the device internal ground.

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GENERAL DESCRIPTION

READ
The READ command selects the bank from BA0, BA1 requiring an explicit command. A10 to enable the AUTO
inputs and starts a burst read access to an active row. PRECHARGE function in conjunction with a specific READ
Inputs A0-An (For column addresses, n=A8 for x32, n=A9 or WRITE command. For each individual READ or WRITE
for x16, n=A11 for x8), provides the starting column loca- command, auto precharge is either enabled or disabled.
tion. When A10 is HIGH, this command functions as an AUTO PRECHARGE does not apply except in full-page
AUTO PRECHARGE command. When the auto precharge burst mode. Upon completion of the READ or WRITE
is selected, the row being accessed will be precharged at burst, a precharge of the bank/row that is addressed is
the end of the READ burst. The row will remain open for automatically performed.
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’s read data is subject to the logic level on
AUTO REFRESH COMMAND
the DQM inputs two clocks earlier. When a given DQM This command executes the AUTO REFRESH operation.
signal was registered HIGH, the corresponding DQ’s will The row address and bank to be refreshed are automati-
be High-Z two clocks later. DQ’s will provide valid data cally generated during this operation. The stipulated period
when the DQM signal was registered LOW. (trc) is required for a single refresh operation, and no
other commands can be executed during this period. This
WRITE command is executed at least 8192 times for every Tref
A burst write access to an active row is initiated with the period. During an AUTO REFRESH command, address
WRITE command. BA0, BA1 inputs selects the bank, and bits are “Don’t Care”. This command corresponds to CBR
the starting column location is provided by inputs A0-An Auto-refresh.
(For column addresses, n=A8 for x32, n=A9 for x16, n=A11
for x8). AUTO-PRECHARGE is determined by A10.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
The row being accessed will be precharged at the end of
the burst read and write operations by truncating either
the WRITE burst, if AUTO PRECHARGE is selected. If
fixed-length or full-page bursts and the most recently
AUTO PRECHARGE is not selected, the row will remain
registered READ or WRITE command prior to the BURST
open for subsequent accesses.
TERMINATE.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same COMMAND INHIBIT
time. Data will be written to memory when DQM signal is COMMAND INHIBIT prevents new commands from being
LOW. When DQM is HIGH, the corresponding data inputs executed. Operations in progress are not affected, apart
will be ignored, and a WRITE will not be executed to that from whether the CLK signal is enabled
byte/column location.
NO OPERATION
PRECHARGE When CS is low, the NOP command prevents unwanted
The PRECHARGE command is used to deactivate the commands from being registered during idle or wait
open row in a particular bank or the open row in all banks. states.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined LOAD MODE REGISTER
whether one or all banks are precharged. After execut- During the LOAD MODE REGISTER command the mode
ing this command, the next command for the selected register is loaded from A0-A12. This command can only
bank(s) is executed after passage of the period tRP, which be issued when all banks are idle.
is the period required for bank precharging. Once a bank
has been precharged, it is in the idle state and must be ACTIVE COMMAND
activated prior to any READ or WRITE commands being When the ACTIVE COMMAND is activated, BA0, BA1
issued to that bank. inputs selects a bank to be accessed, and the address
inputs on A0-A12 selects the row. Until a PRECHARGE
AUTO PRECHARGE command is issued to the bank, the row remains open
The AUTO PRECHARGE function ensures that the pre- for accesses.
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without

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COMMAND TRUTH TABLE

CKE A12, A11
Function n–1 n CS RAS CAS WE BA1 BA0 A10 A9 - A0
Device deselect (DESL) H × H × × × × × × ×
No operation (NOP) H × L H H H × × × ×
Burst stop (BST) H × L H H L × × × ×
Read H × L H L H V V L V
Read with auto precharge H × L H L H V V H V
Write H × L H L L V V L V
Write with auto precharge H × L H L L V V H V
Bank activate (ACT) H × L L H H V V V V
Precharge select bank (PRE) H × L L H L V V L ×
Precharge all banks (PALL) H × L L H L × × H ×
CBR Auto-Refresh (REF) H H L L L H × × × ×
Self-Refresh (SELF) H L L L L H × × × ×
Mode register set (MRS) H × L L L L L L L V
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data.

DQM TRUTH TABLE

CKE
Function n-1 n DQMH DQML
Data write / output enable H × L L
Data mask / output disable H × H H
Upper byte write enable / output enable H × L ×
Lower byte write enable / output enable H × × L
Upper byte write inhibit / output disable H × H ×
Lower byte write inhibit / output disable H × × H
Note:
1. H=Vih, L=Vil x= Vih or Vil, V = Valid Data.
2. x16 options shown. x32 DQM0-DQM3 is similar in function.

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CKE TRUTH TABLE

CKE
Current State /Function n–1 n CS RAS CAS WE Address
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend mode exit L H × × × × ×
Auto refresh command Idle (REF) H H L L L H ×
Self refresh entry Idle (SELF) H L L L L H ×
Power down entry Idle H L × × × × ×
Self refresh exit L H L H H H ×
L H H × × × ×
Power down exit L H × × × × ×
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data.

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FUNCTIONAL TRUTH TABLE

Current State CS RAS CAS WE Address Command Action
Idle H X X X X DESL Nop or Power Down(2)
L H H H X NOP Nop or Power Down(2)
L H H L X BST Nop or Power Down
L H L H BA, CA, A10 READ/READA ILLEGAL (3)
L H L L A, CA, A10 WRIT/ WRITA ILLEGAL(3)
L L H H BA, RA ACT Row activating
L L H L BA, A10 PRE/PALL Nop
L L L H X REF/SELF Auto refresh or Self-refresh(4)
L L L L OC, BA1=L MRS Mode register set
Row Active H X X X X DESL Nop
L H H H X NOP Nop
L H H L X BST Nop
L H L H BA, CA, A10 READ/READA Begin read (5)
L H L L BA, CA, A10 WRIT/ WRITA Begin write (5)
L L H H BA, RA ACT ILLEGAL (3)
L L H L BA, A10 PRE/PALL Precharge

Precharge all banks(6)
L L L H X REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Read H X X X X DESL Continue burst to end to
Row active
L H H H X NOP Continue burst to end Row
Row active
L H H L X BST Burst stop, Row active
L H L H BA, CA, A10 READ/READA Terminate burst,
begin new read (7)
L H L L BA, CA, A10 WRIT/WRITA Terminate burst,
begin write (7,8)
L L H H BA, RA ACT ILLEGAL (3)
L L H L BA, A10 PRE/PALL Terminate burst
Precharging
L L L H X REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Write H X X X X DESL Continue burst to end
Write recovering
L H H H X NOP Continue burst to end
Write recovering
L H H L X BST Burst stop, Row active
L H L H BA, CA, A10 READ/READA Terminate burst, start read :
Determine AP (7,8)
L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write :
Determine AP (7)
L L H H BA, RA RA ACT ILLEGAL (3)
L L H L BA, A10 PRE/PALL Terminate burst Precharging (9)
L L L H X REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

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FUNCTIONAL TRUTH TABLE Continued:

Current State CS RAS CAS WE Address Command Action
Read with auto H × × × × DESL Continue burst to end, Precharge
Precharging
L H H H x NOP Continue burst to end, Precharge
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL (11)
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL (11)
L L H H BA, RA ACT ILLEGAL (3)
L L H L BA, A10 PRE/PALL ILLEGAL (11)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Write with Auto H × × × × DESL Continue burst to end, Write
Precharge recovering with auto precharge
L H H H × NOP Continue burst to end, Write
recovering with auto precharge
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL(11)
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL (11)
L L H H BA, RA ACT ILLEGAL (3,11)
L L H L BA, A10 PRE/PALL ILLEGAL (3,11)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Precharging H × × × × DESL Nop, Enter idle after tRP
L H H H × NOP Nop, Enter idle after tRP
L H H L × BST Nop, Enter idle after tRP
L H L H BA, CA, A10 READ/READA ILLEGAL (3)
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL (3)
L L H H BA, RA ACT ILLEGAL(3)
L L H L BA, A10 PRE/PALL Nop Enter idle after tRP
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Row Activating H × × × × DESL Nop, Enter bank active after tRCD
L H H H × NOP Nop, Enter bank active after tRCD
L H H L × BST Nop, Enter bank active after tRCD
L H L H BA, CA, A10 READ/READA ILLEGAL (3)
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL (3)
L L H H BA, RA ACT ILLEGAL (3,9)
L L H L BA, A10 PRE/PALL ILLEGAL (3)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL

Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

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FUNCTIONAL TRUTH TABLE Continued:

Current State CS RAS CAS WE Address Command Action
Write Recovering H × × × × DESL Nop, Enter row active after tDPL
L H H H × NOP Nop, Enter row active after tDPL
L H H L × BST Nop, Enter row active after tDPL
L H L H BA, CA, A10 READ/READA Begin read (8)
L H L L BA, CA, A10 WRIT/ WRITA Begin new write
L L H H BA, RA ACT ILLEGAL (3)
L L H L BA, A10 PRE/PALL ILLEGAL (3)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Write Recovering H × × × × DESL Nop, Enter precharge after tDPL
with Auto L H H H × NOP Nop, Enter precharge after tDPL
Precharge L H H L × BST Nop, Enter row active after tDPL
L H L H BA, CA, A10 READ/READA ILLEGAL(3,8,11)
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL (3,11)
L L H H BA, RA ACT ILLEGAL (3,11)
L L H L BA, A10 PRE/PALL ILLEGAL (3,11)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Refresh H × × × × DESL Nop, Enter idle after tRC
L H H × × NOP/BST Nop, Enter idle after tRC
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Mode Register H × × × × DESL Nop, Enter idle after 2 clocks
Accessing L H H H × NOP Nop, Enter idle after 2 clocks
L H H L × BST ILLEGAL
L H L × BA, CA, A10 READ/WRITE ILLEGAL
L L × × BA, RA ACT/PRE/PALL ILLEGAL
REF/MRS
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be
disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will be
disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.

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CKE RELATED COMMAND TRUTH TABLE(1)

CKE
Current State Operation n-1 n CS RAS CAS WE Address
Self-Refresh (S.R.) INVALID, CLK (n - 1) would exit S.R. H X X X X X X
Self-Refresh Recovery(2) L H H X X X X
Self-Refresh Recovery(2) L H L H H X X
Illegal L H L H L X X
Illegal L H L L X X X
Maintain S.R. L L X X X X X
Self-Refresh Recovery Idle After trc H H H X X X X
Idle After trc H H L H H X X
Illegal H H L H L X X
Illegal H H L L X X X
Begin clock suspend next cycle(5) H L H X X X X
Begin clock suspend next cycle(5) H L L H H X X
Illegal H L L H L X X
Illegal H L L L X X X
Exit clock suspend next cycle(2) L H X X X X X
Maintain clock suspend L L X X X X X
Power-Down (P.D.) INVALID, CLK (n - 1) would exit P.D. H X X X X X —
EXIT P.D. --> Idle(2) L H X X X X X
Maintain power down mode L L X X X X X
All Banks Idle Refer to operations in Operative Command Table H H H X X X —
Refer to operations in Operative Command Table H H L H X X —
Refer to operations in Operative Command Table H H L L H X —
Auto-Refresh H H L L L H X
Refer to operations in Operative Command Table H H L L L L Op - Code
Refer to operations in Operative Command Table H L H X X X —
Refer to operations in Operative Command Table H L L H X X —
Refer to operations in Operative Command Table H L L L H X —
Self-Refresh(3) H L L L L H X
Refer to operations in Operative Command Table H L L L L L Op - Code
Power-Down(3) L X X X X X X
Any state Refer to operations in Operative Command Table H H X X X X X
other than Begin clock suspend next cycle(4) H L X X X X X
listed above Exit clock suspend next cycle L H X X X X X
Maintain clock suspend L L X X X X X

Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if txsr is not satisfied.

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STATE DIAGRAM

Self
Refresh
SELF

SELF exit
Mode MRS
Register REF CBR (Auto)
IDLE
Set Refresh

CKE

CKE

ACT Power
Down

CKE Active
Row
Power
Active CKE
Down
BST
BST
Write Read
Au
rge
th

Re
to

Write
ha
wi

Read
ad arge
Pr
ec
rite

ec
Pr

wit
W

h
to

CKE Read CKE

Au

WRITE READ
WRITE READ
SUSPEND SUSPEND
CKE Write CKE
RR

n)
tio
E(

na

CKE CKE READA

WRITEA
Pre

mi

WRITEA READA
ter

SUSPEND SUSPEND
ch

CKE CKE
arg

rge
et

ha
erm

rec
(P
ina

E
tio

PR
n)

Precharge
POWER
Precharge
ON

Automatic sequence

Manual Input

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ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameters Rating Unit
Vdd max Maximum Supply Voltage –0.5 to +4.6 V
Vddq max Maximum Supply Voltage for Output Buffer –0.5 to +4.6 V
Vin Input Voltage –0.5 to Vdd + 0.5 V
Vout Output Voltage –1.0 to Vddq + 0.5 V
Pd max Allowable Power Dissipation 1 W
Ics Output Shorted Current 50 mA
Topr Operating Temperature Com. 0 to +70 °C
Ind. -40 to +85
A1 -40 to +85
A2 -40 to +105
Tstg Storage Temperature –65 to +150 °C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.

DC RECOMMENDED OPERATING CONDITIONS

IS42/45SxxxxxD - 3.3V Operation

Symbol Parameters Min. Typ. Max. Unit
Vdd Supply Voltage 3.0 3.3 3.6 V
Vddq I/O Supply Voltage 3.0 3.3 3.6 V
Vih(1) Input High Voltage 2.0 – Vddq+0.3 V
Vil(2) Input Low Voltage -0.3 – 0.8 V
Iil Input Leakage Current (0V ≤ Vin ≤ Vdd) -5 – +5 µA
Iol Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd) -5 – +5 µA
Voh Output High Voltage Current (Ioh = -2mA) 2.4 – – V
Vol Output Low Voltage Current (Iol = 2mA) – – 0.4 V

IS42/45RxxxxxD - 2.5V Operation

Symbol Parameters Min. Typ. Max. Unit
Vdd Supply Voltage 2.3 2.5 2.7 V
Vddq I/O Supply Voltage 2.3 2.5 2.7 V
Vih(1) Input High Voltage 2.0 - Vddq+0.3 V
Vil(2) Input Low Voltage -0.3 - 0.55 V
Iil Input Leakage Current (0V ≤ Vin ≤ Vdd) -5 – +5 µA
Iol Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd) -5 – +5 µA
Voh Output High Voltage Current (Ioh = -2mA) Vddq-0.2 – - V
Vol Output Low Voltage Current (Iol = 2mA) - – 0.2 V
Notes:
1. Vih (overshoot): Vih (max) = Vddq +1.2V (pulse width < 3ns).
2. Vil (undershoot): Vih (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.

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CAPACITANCE CHARACTERISTICS(1) (At Ta = 0 to +25°C, Vdd = Vddq = 3.3 ± 0.3V, f = 1MHz)
Symbol Parameter Min. Max. Unit
Cin1 Input Capacitance: CLK 2.5 3.5 pF
Cin2 Input Capacitance:All other input pins 2.5 3.8 pF
Ci/o Data Input/Output Capacitance: DQS 4.0 6.0 pF
Note: 1. The parameter is characterized.

THERMAL RESISTANCE
Package Substrate Theta-ja Theta-ja Theta-ja Theta-jc Units
(Airflow = 0m/s) (Airflow = 1m/s) (Airflow = 2m/s)
Alloy42 TSOP2(54) 4-layer 53.3 45.2 42.0 7.8 C/W
Copper TSOP2(54) 4-layer 42.3 37.1 34.5 7.5 C/W
BGA(54) 4-layer 36.7 30.5 28.9 4.2 C/W
BGA(90) 4-layer 36.1 30.7 27.7 3.0 C/W

DC ELECTRICAL CHARACTERISTICS (x8, x16)

(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition -5 -6 -7 Unit
Idd1 (1)
Operating Current One bank active, CL = 3, BL = 1, 170 150 140 mA
tclk = tclk (min), trc = trc (min)
Idd2p Precharge Standby Current CKE ≤ Vil (max), tck = 15ns 8 8 8 mA
(In Power-Down Mode)
Idd2ps Precharge Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) 8 8 8 mA
(In Power-Down Mode)
Idd2n (2) Precharge Standby Current CS ≥ Vcc - 0.2V, CKE ≥ Vih (min) 35 35 35 mA
(In Non Power-Down Mode) tck = 15ns
Idd2ns Precharge Standby Current CS ≥ Vcc - 0.2V, CKE ≥ Vih (min) or 30 30 30 mA
(In Non Power-Down Mode) CKE ≤ Vil (max), All inputs stable
Idd3p Active Standby Current CKE ≤ Vil (max), tck = 15ns 15 15 15 mA
(Power-Down Mode)
Idd3ps Active Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) 15 15 15 mA
(Power-Down Mode)
Idd3n (2)
Active Standby Current CS ≥ Vcc - 0.2V, CKE ≥ Vih (min) 40 40 40 mA
(In Non Power-Down Mode) tck = 15ns
Idd3ns Active Standby Current CS ≥ Vcc - 0.2V, CKE ≥ Vih (min) or 30 30 30 mA
(In Non Power-Down Mode) CKE ≤ Vil (max), All inputs stable
Idd4 Operating Current All banks active, BL = 4, CL = 3, 200 180 160 mA
tck = tck (min)
Idd5 Auto-Refresh Current trc = trc (min), tclk = tclk (min) 250 230 210 mA
Idd6 Self-Refresh Current CKE ≤ 0.2V 12 12 12 mA
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. All values applicable for operation with Ta ≤ 85°C.
4. For A2 temperature grade with Ta > 85°C: IDD2P and IDD2PS are derated to 50% above the values; IDD3P and IDD3PS are
derated to 30% above the values.

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DC ELECTRICAL CHARACTERISTICS (x32)

(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition -5 -6 -7 Unit
Idd1 (1)
Operating Current One bank active, CL = 3, BL = 1, 190 180 170 mA
tclk = tclk (min), trc = trc (min)
Idd2p Precharge Standby Current CKE ≤ Vil (max), tck = 15ns 4 4 4 mA
(In Power-Down Mode)
Idd2ps Precharge Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) 4 4 4 mA
(In Power-Down Mode)
Idd2n (2) Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) 45 45 45 mA
(In Non Power-Down Mode) tck = 15ns
Idd2ns Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) or 20 20 20 mA
(In Non Power-Down Mode) CKE ≤ Vil (max), All inputs stable
Idd3p Active Standby Current CKE ≤ Vil (max), tck = 15ns 15 15 15 mA
(Power-Down Mode)
Idd3ps Active Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) 15 15 15 mA
(Power-Down Mode)
Idd3n (2)
Active Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) 65 65 65 mA
(In Non Power-Down Mode) tck = 15ns
Idd3ns Active Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) or 45 45 45 mA
(In Non Power-Down Mode) CKE ≤ Vil (max), All inputs stable
Idd4 Operating Current All banks active, BL = 4, CL = 3, 285 245 230 mA
tck = tck (min)
Idd5 Auto-Refresh Current trc = trc (min), tclk = tclk (min) 270 260 250 mA
Idd6 Self-Refresh Current CKE ≤ 0.2V 6 6 6 mA
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. All values applicable for operation with Ta ≤ 85°C.
4. For A2 temperature grade with Ta > 85°C: IDD1 is derated to 10% above the values.

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AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5 -6 -7
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tck3 Clock Cycle Time CAS Latency = 3 5 — 6 — 7 — ns
tck2 CAS Latency = 2 10 — 10 — 7.5 — ns
tac3 Access Time From CLK CAS Latency = 3 — 5.0 — 5.4 — 5.4 ns
tac2 CAS Latency = 2 — 6 — 6 — 5.4 ns
tch CLK HIGH Level Width 2 — 2.5 — 2.5 — ns
tcl CLK LOW Level Width 2 — 2.5 — 2.5 — ns
toh3 Output Data Hold Time CAS Latency = 3 2.5 — 2.7 — 2.7 — ns
toh2 CAS Latency = 2 2.5 — 2.7 — 2.7 — ns
tlz Output LOW Impedance Time 0 — 0 — 0 — ns
thz3 Output HIGH Impedance Time — 5 — 5.4 — 5.4 ns
thz2 — 6 — 6 — 5.4 ns
tds Input Data Setup Time(2) 1.8 — 1.5 — 1.5 — ns
tdh Input Data Hold Time (2)
0.8 — 0.8 — 0.8 — ns
tas Address Setup Time(2) 1.5 — 1.5 — 1.5 — ns
tah Address Hold Time (2)
0.8 — 0.8 — 0.8 — ns
tcks CKE Setup Time (2)
1.5 — 1.5 — 1.5 — ns
tckh CKE Hold Time(2) 0.8 — 0.8 — 0.8 — ns
tcms Command Setup Time (CS, RAS, CAS, WE, DQM)(2) 1.5 — 1.5 — 1.5 — ns
tcmh Command Hold Time (CS, RAS, CAS, WE, DQM) (2)
0.8 — 0.8 — 0.8 — ns
trc Command Period (REF to REF / ACT to ACT) 55 — 60 — 60 — ns
tras Command Period (ACT to PRE) 38 100K 42 100K 37 100K ns
trp Command Period (PRE to ACT) 15 — 18 — 15 — ns
trcd Active Command To Read / Write Command Delay Time 15 — 18 — 15 — ns
trrd Command Period (ACT [0] to ACT[1]) 10 — 12 — 14 — ns
tdpl Input Data To Precharge 10 — 12 — 14 — ns
Command Delay time
tdal Input Data To Active / Refresh 25 — 30 — 29 — ns
Command Delay time (During Auto-Precharge)
tmrd Mode Register Program Time 10 — 12 — 14 — ns
tdde Power Down Exit Setup Time 5 — 6 — 7 — ns
txsr Self-Refresh Exit Time 60 — 70 — 67 — ns
tt Transition Time 0.3 1.2 0.3 1.2 0.3 1.2 ns
tref Refresh Cycle Time (8192) Ta ≤ 70oC Com, Ind, A1, A2 — 64 — 64 — 64 ms
Ta ≤ 85oC Ind, A1, A2 — 64 — 64 — 64 ms
Ta > 85oC A2 — — — — — 16 ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tt /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vih(min.) and Vil
(max).

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OPERATING FREQUENCY / LATENCY RELATIONSHIPS

Symbol
Parameter -5 -6 -7 -7 Units
— Clock Cycle Time 5 6 7 7.5 ns
— Operating Frequency 200 167 143 133 MHz
tcac CAS Latency 3 3 3 2 cycle
trcd Active Command To Read/Write Command Delay Time 3 3 3 2 cycle
trac RAS Latency (trcd + tcac) CAS Latency = 3 6 6 6 — cycle
CAS Latency = 2 — — — 4
trc Command Period (REF to REF / ACT to ACT) 10 10 9 8 cycle
tras Command Period (ACT to PRE) 7 7 6 5 cycle
trp Command Period (PRE to ACT) 3 3 3 2 cycle
trrd Command Period (ACT[0] to ACT [1]) 2 2 2 2 cycle
tccd Column Command Delay Time 1 1 1 1 cycle
(READ, READA, WRIT, WRITA)
tdpl Input Data To Precharge Command Delay Time 2 2 2 2 cycle
tdal Input Data To Active/Refresh Command Delay Time 5 5 5 4 cycle
(During Auto-Precharge)
trbd Burst Stop Command To Output in HIGH-Z Delay Time CAS Latency = 3 3 3 3 — cycle
(Read) CAS Latency = 2 — — — 2
twbd Burst Stop Command To Input in Invalid Delay Time 0 0 0 0 cycle
(Write)
trql Precharge Command To Output in HIGH-Z Delay Time CAS Latency = 3 3 3 3 — cycle
(Read) CAS Latency = 2 — — — 2
twdl Precharge Command To Input in Invalid Delay Time 0 0 0 0 cycle
(Write)
tpql Last Output To Auto-Precharge Start Time (Read) CAS Latency = 3 -2 -2 –2 — cycle
CAS Latency = 2 — — — -1
tqmd DQM To Output Delay Time (Read) 2 2 2 2 cycle
tdmd DQM To Input Delay Time (Write) 0 0 0 0 cycle
tmrd Mode Register Set To Command Delay Time 2 2 2 2 cycle

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AC TEST CONDITIONS: 3.3V

Input Load Output Load

tCK
tCH tCL
3.0V
CLK 1.4V
0V 1.4V
tCMS tCMH
3.0V
Z = 50Ω 50Ω
INPUT 1.4V Output
0V 50 pF
tAC
tOH

OUTPUT 1.4V 1.4V

AC TEST CONDITIONS
IS42/45Sxxxxx IS42/45Rxxxxx
Parameter Rating Rating
AC Input Levels 0V to 3.0V 0V to 2.5V
Input Rise and Fall Times 1 ns 1 ns
Input Timing Reference Level 1.4V 1.25V
Output Timing Measurement Reference Level 1.4V 1.25V

AC TEST CONDITIONS: 2.5V

Input Load Output Load

tCK
tCH tCL
2.5V
1.25V 1.25V
CLK
0.0V 50Ω
tCMS tCMH Z = 50Ω
2.5V Output
50 pF
INPUT 1.25V
0.0V
tOH tAC

1.25V 1.25V
OUTPUT

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FUNCTIONAL DESCRIPTION Initialization

The 512Mb SDRAMs are quad-bank DRAMs which oper- SDRAMs must be powered up and initialized in a
ate at 3.3V or 2.5V and include a synchronous interface predefined manner.
(all signals are registered on the positive edge of the clock The 512Mb SDRAM is initialized after the power is applied
signal, CLK). to Vdd and Vddq (simultaneously) and the clock is stable
Read and write accesses to the SDRAM are burst oriented; with DQM High and CKE High.
accesses start at a selected location and continue for A 100µs delay is required prior to issuing any command
a programmed number of locations in a programmed other than a COMMAND INHIBIT or a NOP. The COMMAND
sequence. Accesses begin with the registration of an AC- INHIBIT or NOP may be applied during the 100us period and
TIVE command which is then followed by a READ or WRITE should continue at least through the end of the period.
command. The address bits registered coincident with the With at least one COMMAND INHIBIT or NOP command
ACTIVE command are used to select the bank and row to having been applied, a PRECHARGE command should
be accessed (BA0 and BA1 select the bank, A0-A12 select the be applied once the 100µs delay has been satisfied. All
row). The address bits A0-An; registered coincident with the banks must be precharged. This will leave all banks in an
READ or WRITE command are used to select the starting idle state after which at least two AUTO REFRESH cycles
column location for the burst access. must be performed. After the AUTO REFRESH cycles are
Prior to normal operation, the SDRAM must be initial- complete, the SDRAM is then ready for mode register
ized. The following sections provide detailed information programming.
covering device initialization, register definition, command
The mode register should be loaded prior to applying
descriptions and device operation.
any operational command because it will power up in an
unknown state.

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Initialize and Load Mode Register(1)

T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3

CLK tCK tCH tCL

tCKS tCKH
CKE

tCMS tCMH tCMS tCMH tCMS tCMH

COMMAND AUTO AUTO Load MODE
NOP PRECHARGE REFRESH NOP REFRESH NOP REGISTER NOP ACTIVE

DQM/
DQML, DQMH
tAS tAH
A0-A9, A11, A12 CODE ROW
tAS tAH
ALL BANKS
A10 CODE ROW
SINGLE BANK tAS tAH
BA0, BA1 ALL BANKS CODE BANK

DQ
tRP tRC tRC tMRD
T
Power-up: VCC Precharge AUTO REFRESH AUTO REFRESH Program MODE REGISTER (2, 3, 4)
and CLK stable all banks
At least 2 Auto-Refresh Commands
T = 100µs Min. DON'T CARE

Notes:
1. If CS is High at clock High time, all commands applied are NOP.
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after the command is issued.

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Auto-Refresh Cycle

T0 T1 T2 Tn+1 To+1
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND Auto Auto
PRECHARGE NOP Refresh NOP Refresh NOP ACTIVE

DQM/
DQML, DQMH

A0-A9, A11, A12 ROW

ALL BANKS
A10 ROW
SINGLE BANK
BA0, BA1 BANK(s) BANK
tAS tAH

DQ High-Z
tRP tRC tRC

DON'T CARE

Notes:
1. CAS latency = 2, 3

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Self-Refresh Cycle

T0 T1 T2 Tn+1 To+1 To+2

CLK tCK tCH tCL

tCKS tCKH tCKS

≥ tRAS
CKE

tCMS tCMH tCKS

COMMAND Auto Auto

PRECHARGE NOP Refresh NOP NOP Refresh

DQM/
DQML, DQMH

A0-A9, A11, A12

ALL BANKS
A10
SINGLE BANK
tAS tAH
BA0, BA1 BANK

DQ High-Z
tRP tXSR

Precharge all Enter self CLK stable prior to exiting Exit self refresh mode
active banks refresh mode self refresh mode (Restart refresh time base) DON'T CARE

Notes:
1. Self-Refresh mode is not supported for A2 grade with Ta > +85oC.

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Register Definition
Mode Register
The mode register is used to define the specific mode Mode register bits M0-M2 specify the burst length, M3
of operation of the SDRAM. This definition includes the specifies the type of burst (sequential or interleaved), M4- M6
selection of a burst length, a burst type, a CAS latency, specify the CAS latency, M7 and M8 specify the operating
an operating mode and a write burst mode, as shown in mode, M9 specifies the WRITE burst mode, and M10, M11,
MODE REGISTER DEFINITION. and M12 are reserved for future use.
The mode register is programmed via the LOAD MODE The mode register must be loaded when all banks are
REGISTER command and will retain the stored information idle, and the controller must wait the specified time before
until it is programmed again or the device loses power. initiating the subsequent operation.Violating either of these
requirements will result in unspecified operation.

MODE REGISTER DEFINITION

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax)

Mode Register (Mx)

(1)
Reserved Burst Length

M2 M1 M0 M3=0 M3=1
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved

Burst Type

M3 Type
0 Sequential
1 Interleaved

Latency Mode

M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved

Operating Mode

M8 M7 M6-M0 Mode
0 0 Defined Standard Operation
— — — All Other States Reserved

Write Burst Mode

M9 Mode
0 Programmed Burst Length 1. To ensure compatibility with future devices,
1 Single Location Access should program BA1, BA0, A12, A11, A10 = "0"

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Burst Length
Read and write accesses to the SDRAM are burst oriented, reached. The block is uniquely selected by A1-An when the
with the burst length being programmable, as shown in burst length is set to two; by A2-An when the burst length
MODE REGISTER DEFINITION. The burst length deter- is set to four; and by A3-An when the burst length is set
mines the maximum number of column locations that can to eight. An = A8 for x32, An = A9 for x16, and An = A11
be accessed for a given READ or WRITE command. Burst for x8. The remaining (least significant) address bit(s) is
lengths of 1, 2, 4 or 8 locations are available for both the (are) used to select the starting location within the block.
sequential and the interleaved burst types, and a full-page Full-page bursts wrap within the page if the boundary is
burst is available for the sequential type. The full-page reached.
burst is used in conjunction with the BURST TERMINATE
Burst Type
command to generate arbitrary burst lengths.
Accesses within a given burst may be programmed to be
Reserved states should not be used, as unknown operation
either sequential or interleaved; this is referred to as the
or incompatibility with future versions may result.
burst type and is selected via bit M3.
When a READ or WRITE command is issued, a block of
The ordering of accesses within a burst is determined by
columns equal to the burst length is effectively selected. All
the burst length, the burst type and the starting column
accesses for that burst take place within this block, mean-
address, as shown in BURST DEFINITION table.
ing that the burst will wrap within the block if a boundary is

Burst Definition
Burst Starting Column Order of Accesses Within a Burst
Length Address Type = Sequential Type = Interleaved
A 0
2 0 0-1 0-1
1 1-0 1-0
A 1 A0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full n = A0-A8 (x32) Cn, Cn + 1, Cn + 2 Not Supported
Page n = A0-A9 (x16) Cn + 3, Cn + 4...
(y) n = A0-A9, A11 (x8) …Cn - 1,
(location 0-y) Cn…

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CAS Latency Operating Mode

The CAS latency is the delay, in clock cycles, between The normal operating mode is selected by setting M7 and M8
the registration of a READ command and the availability of to zero; the other combinations of values for M7 and M8 are
the first piece of output data. The latency can be set to two or reserved for future use and/or test modes. The programmed
three clocks. burst length applies to both READ and WRITE bursts.
If a READ command is registered at clock edge n, and Test modes and reserved states should not be used be-
the latency is m clocks, the data will be available by clock cause unknown operation or incompatibility with future
edge n + m. The DQs will start driving as a result of the versions may result.
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
Write Burst Mode
clock edge n + m. For example, assuming that the clock When M9 = 0, the burst length programmed via M0-M2
cycle time is such that all relevant access times are met, applies to both READ and WRITE bursts; when M9 = 1,
if a READ command is registered at T0 and the latency the programmed burst length applies to READ bursts, but
is programmed to two clocks, the DQs will start driving write accesses are single-location (nonburst) accesses.
after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams. The Allowable Operating Frequency CAS Latency
table indicates the operating frequencies at which each Allowable Operating Frequency (MHz)
CAS latency setting can be used. Speed CAS Latency = 2 CAS Latency = 3
Reserved states should not be used as unknown operation -5 100 200
or incompatibility with future versions may result.
-6 100 167
-7 133 143

CAS Latency

T0 T1 T2 T3
CLK

COMMAND READ NOP NOP

tAC
DQ DOUT
tLZ tOH
CAS Latency - 2

T0 T1 T2 T3 T4
CLK

COMMAND READ NOP NOP NOP

tAC
DQ DOUT
tLZ tOH
CAS Latency - 3

DON'T CARE

UNDEFINED

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CHIP Operation Activating Specific Row Within Spe-

cific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command, CLK
which selects both the bank and the row to be activated HIGH
(see Activating Specific Row Within Specific Bank). CKE

After opening a row (issuing an ACTIVE command), a READ

or WRITE command may be issued to that row, subject to CS
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number RAS
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a trcd specification of 15ns with a CAS
143 MHz clock (7ns period) results in 2.14 clocks, rounded
to 3. This is reflected in the following example, which cov- WE
ers any case where 2 < [trcd (MIN)/tck] ≤ 3. (The same
procedure is used to convert other specification limits from
time units to clock cycles). A0-A12 ROW ADDRESS

A subsequent ACTIVE command to a different row in the BA0, BA1 BANK ADDRESS
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by trc.

A subsequent ACTIVE command to another bank can be

issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by trrd.

Example: Meeting trcd (MIN) when 2 < [trcd (min)/tck] ≤ 3

T0 T1 T2 T3 T4
CLK

READ or
COMMAND ACTIVE NOP NOP WRITE
tRCD

DON'T CARE

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READs READ COMMAND

READ bursts are initiated with a READ command, as
shown in the READ COMMAND diagram. CLK
The starting column and bank addresses are provided with
HIGH
the READ command, and auto precharge is either enabled or CKE
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
the burst. For the generic READ commands used in the fol- CS
lowing illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the RAS
starting column address will be available following the
CAS latency after the READ command. Each subsequent CAS
data-out element will be valid by the next positive clock
edge. The CAS Latency diagram shows general timing WE
for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands A0-A9, A11 COLUMN ADDRESS
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will A12
wrap to column 0 and continue.)
AUTO PRECHARGE
Data from any READ burst may be truncated with a sub-
A10
sequent READ command, and data from a fixed-length
NO PRECHARGE
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data BA0, BA1 BANK ADDRESS

can be maintained. The first data element from the new

burst follows either the last element of a completed burst Note:
or the last desired data element of a longer burst which x32: A9 and A11 are "Don't Care"
is being truncated. x16: A11 is "Don't Care"
The new READ command should be issued x cycles before
the clock edge at which the last desired data element is The DQM input is used to avoid I/O contention, as shown
valid, where x equals the CAS latency minus one. This is in Figures RW1 and RW2. The DQM signal must be as-
shown in Consecutive READ Bursts for CAS latencies of serted (HIGH) at least three clocks prior to the WRITE
two and three; data element n + 3 is either the last of a command (DQM latency is two clocks for output buffers)
burst of four or the last desired of a longer burst. The 512Mb to suppress data-out from the READ. Once the WRITE
SDRAM uses a pipelined architecture and therefore does command is registered, the DQs will go High-Z (or remain
not require the 2n rule associated with a prefetch architec- High-Z), regardless of the state of the DQM signal, provided
ture. A READ command can be initiated on any clock cycle the DQM was active on the clock just prior to the WRITE
following a previous READ command. Full-speed random command that truncated the READ command. If not, the
read accesses can be performed to the same bank, as second WRITE will be an invalid WRITE. For example, if
shown in Random READ Accesses, or each subsequent DQM was LOW during T4 in Figure RW2, then the WRITEs
READ may be performed to a different bank. at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
Data from any READ burst may be truncated with a sub-
sequent WRITE command, and data from a fixed-length The DQM signal must be de-asserted prior to the WRITE
READ burst may be immediately followed by data from a command (DQM latency is zero clocks for input buffers)
WRITE command (subject to bus turnaround limitations). to ensure that the written data is not masked.
The WRITE burst may be initiated on the clock edge im- A fixed-length READ burst may be followed by, or truncated
mediately following the last (or last desired) data element with, a PRECHARGE command to the same bank (provided
from the READ burst, provided that I/O contention can be that auto precharge was not activated), and a full-page burst
avoided. In a given system design, there may be a pos- may be truncated with a PRECHARGE command to the
sibility that the device driving the input data will go Low-Z same bank.The PRECHARGE command should be issued
before the SDRAM DQs go High-Z. In this case, at least x cycles before the clock edge at which the last desired
a single-cycle delay should occur between the last read data element is valid, where x equals the CAS latency
data and the WRITE command. minus one. This is shown in the READ to PRECHARGE

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diagram for each possible CAS latency; data element n +

3 is either the last of a burst of four or the last desired of
a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until trp is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the PRE-
CHARGE command is that it requires that the command
and address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated.The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.

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RW1 - READ to WRITE

T0 T1 T2 T3 T4 T5 T6
CLK

DQM

COMMAND READ NOP NOP NOP NOP NOP WRITE

ADDRESS BANK, BANK,

COL n COL b

tHZ
DQ DOUT n DOUT n+1 DOUT n+2 DIN b
CAS Latency - 2 tDS

DON'T CARE

RW2 - READ to WRITE

T0 T1 T2 T3 T4 T5
CLK

DQM

COMMAND READ NOP NOP NOP NOP WRITE

ADDRESS BANK, BANK,

COL n COL b

tHZ
DQ DOUT n DIN b
CAS Latency - 3 tDS

DON'T CARE

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Consecutive READ Bursts

T0 T1 T2 T3 T4 T5 T6
CLK

COMMAND READ NOP NOP NOP READ NOP NOP

ADDRESS BANK, BANK,

COL n COL b

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b

CAS Latency - 2
DON'T CARE

T0 T1 T2 T3 T4 T5 T6 T7
CLK

COMMAND READ NOP NOP NOP READ NOP NOP NOP

ADDRESS BANK, BANK,

COL n COL b

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b

CAS Latency - 3
DON'T CARE

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Random READ Accesses

T0 T1 T2 T3 T4 T5
CLK

COMMAND READ READ READ READ NOP NOP

ADDRESS BANK, BANK, BANK, BANK,

COL n COL b COL m COL x

DQ DOUT n DOUT b DOUT m DOUT x

CAS Latency - 2
DON'T CARE

T0 T1 T2 T3 T4 T5 T6
CLK

COMMAND READ READ READ READ NOP NOP NOP

ADDRESS BANK, BANK, BANK, BANK,

COL n COL b COL m COL x

DQ DOUT n DOUT b DOUT m DOUT x

CAS Latency - 3
DON'T CARE

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READ Burst Termination

T0 T1 T2 T3 T4 T5 T6
CLK

BURST
COMMAND READ NOP NOP NOP TERMINATE NOP NOP
x = 1 cycle

ADDRESS BANK a,
COL n

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3

CAS Latency - 2
DON'T CARE

T0 T1 T2 T3 T4 T5 T6 T7
CLK

BURST
COMMAND READ NOP NOP NOP TERMINATE NOP NOP NOP
x = 2 cycles

ADDRESS BANK,
COL n

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3

CAS Latency - 3
DON'T CARE

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ALTERNATING BANK READ ACCESSES

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE
tCMS tCMH

COMMAND ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW COLUMN b(2) ROW
tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
A10 ROW ROW ROW
tAS tAH
BA0, BA1 BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

tLZ tOH tOH tOH tOH tOH

DQ DOUT m DOUT m+1 DOUT m+2 DOUT m+3 DOUT b
tAC tAC tAC tAC tAC tAC
tRCD - BANK 0 CAS Latency - BANK 0 tRP - BANK 0 tRCD - BANK 0
tRRD tRCD - BANK 3 CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE

Notes:
1) CAS latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

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READ - FULL-PAGE BURST

T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4

CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP

tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2)
tAS tAH
A10 ROW
tAS tAH
BA0, BA1 BANK BANK
tAC tAC tAC tAC tAC tAC tHZ
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m-1 DOUT m DOUT m+1
tLZ
tOH tOH tOH tOH tOH tOH
tRCD CAS Latency
DON'T CARE
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command. UNDEFINED

Notes:
1) Cas latency = 2, Burst Length = Full Page
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

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READ - DQM OPERATION

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2)
tAS tAH ENABLE AUTO PRECHARGE

A10 ROW
tAS tAH DISABLE AUTO PRECHARGE

BA0, BA1 BANK BANK

tAC tOH tAC tOH tOH
DQ DOUT m DOUT m+2 DOUT m+3
tLZ tLZ
tHZ tAC tHZ
DON'T CARE
tRCD CAS Latency
UNDEFINED

Notes:
1) Cas latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

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READ to PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7
CLK
tRP
COMMAND READ NOP NOP NOP PRECHARGE NOP ACTIVE NOP

ADDRESS BANK a, BANK BANK a,

COL n (a or all) ROW

tRQL High-Z

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3

CAS Latency - 2
DON'T CARE

T0 T1 T2 T3 T4 T5 T6 T7
CLK
tRP
COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE

ADDRESS BANK, BANK, BANK a,

COL n COL b ROW

tRQL High-Z

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3

CAS Latency - 3
DON'T CARE

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WRITEs
WRITE bursts are initiated with a WRITE command, as An example is shown in WRITE to WRITE diagram. Data
shown in WRITE Command diagram. n + 1 is either the last of a burst of two or the last desired
of a longer burst. The 512Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule as-
WRITE Command
sociated with a prefetch architecture. A WRITE command
CLK can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within
HIGH a page can be performed to the same bank, as shown in
CKE
Random WRITE Cycles, or each subsequent WRITE may
be performed to a different bank.
CS
Data for any WRITE burst may be truncated with a subse-
quent READ command, and data for a fixed-length WRITE
RAS burst may be immediately followed by a subsequent READ
command. Once the READ com mand is registered, the
CAS data inputs will be ignored, and WRITEs will not be ex-
ecuted. An example is shown in WRITE to READ. Data n
WE + 1 is either the last of a burst of two or the last desired
of a longer burst.
A0-A9, A11 COLUMN ADDRESS
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not acti-
A12
vated), and a full-page WRITE burst may be truncated
AUTO PRECHARGE with a PRECHARGE command to the same bank. The
A10 PRECHARGE command should be issued tdpl after the
NO PRECHARGE clock edge at which the last desired input data element
BA0, BA1 BANK ADDRESS is registered. The auto precharge mode requires a tdpl of
at least one clock plus time, regardless of frequency. In
Note: addition, when truncating a WRITE burst, the DQM signal
x32: A9 and A11 are "Don't Care" must be used to mask input data for the clock edge prior
x16: A11 is "Don't Care" to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in the WRITE to PRE-
The starting column and bank addresses are provided with CHARGE diagram. Data n+1 is either the last of a burst
the WRITE command, and auto precharge is either enabled of two or the last desired of a longer burst. Following the
or disabled for that access. If auto precharge is enabled, PRECHARGE command, a subsequent command to the
the row being accessed is precharged at the completion of same bank cannot be issued until trp is met.
the burst. For the generic WRITE commands used in the In the case of a fixed-length burst being executed to comple-
following illustrations, auto precharge is disabled. tion, a PRECHARGE command issued at the optimum
During WRITE bursts, the first valid data-in element will be time (as described above) provides the same operation that
registered coincident with the WRITE command. Subsequent would result from the same fixed-length burst with auto
data elements will be registered on each successive posi- precharge.The disadvantage of the PRECHARGE command
tive clock edge. Upon completion of a fixed-length burst, is that it requires that the command and address buses be
assuming no other commands have been initiated, the available at the appropriate time to issue the command; the
DQs will remain High-Z and any additional input data will advantage of the PRECHARGE command is that it can be
be ignored (see WRITE Burst). A full-page burst will con- used to truncate fixed-length or full-page bursts.
tinue until terminated. (At the end of the page, it will wrap Fixed-length or full-page WRITE bursts can be truncated
to column 0 and continue.) with the BURST TERMINATE command. When truncat-
Data for any WRITE burst may be truncated with a subse- ing a WRITE burst, the input data applied coincident with
quent WRITE command, and data for a fixed-length WRITE the BURST TERMINATE command will be ignored. The
burst may be immediately followed by data for a WRITE last data written (provided that DQM is LOW at that time)
command. The new WRITE command can be issued on will be the input data applied one clock previous to the
any clock following the previous WRITE command, and the BURST TERMINATE command. This is shown in WRITE
data provided coincident with the new command applies to Burst Termination, where data n is the last desired data
the new command. element of a longer burst.

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WRITE Burst

T0 T1 T2 T3
CLK

COMMAND WRITE NOP NOP NOP

ADDRESS BANK,
COL n

DQ DIN n DIN n+1

DON'T CARE

WRITE to WRITE

T0 T1 T2
CLK

COMMAND WRITE NOP WRITE

ADDRESS BANK, BANK,

COL n COL b

DQ DIN n DIN n+1 DIN b

DON'T CARE

Random WRITE Cycles

T0 T1 T2 T3
CLK

COMMAND WRITE WRITE WRITE WRITE

ADDRESS BANK, BANK, BANK, BANK,

COL n COL b COL m COL x

DQ DIN n DIN b DIN m DIN x

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WRITE to READ

T0 T1 T2 T3 T4 T5
CLK

COMMAND WRITE NOP READ NOP NOP NOP

ADDRESS BANK, BANK,

COL n COL b

DQ DIN n DIN n+1 DOUT b DOUT b+1

CAS Latency - 2
DON'T CARE

WP1 - WRITE to PRECHARGE

T0 T1 T2 T3 T4 T5 T6
CLK

DQM
tRP
COMMAND WRITE NOP NOP PRECHARGE NOP ACTIVE NOP

ADDRESS BANK a, BANK BANK a,

COL n (a or all) ROW
tDPL

DQ DIN n DIN n+1 DIN n+2

DON'T CARE

42 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

WP2 - WRITE to PRECHARGE

T0 T1 T2 T3 T4 T5 T6
CLK

DQM
tRP
COMMAND WRITE NOP NOP PRECHARGE NOP NOP ACTIVE

ADDRESS BANK a, BANK BANK a,

COL n (a or all) ROW
tDPL

DQ DIN n DIN n+1

DON'T CARE

WRITE Burst Termination

T0 T1 T2
CLK

BURST NEXT
COMMAND WRITE TERMINATE COMMAND

ADDRESS BANK, (ADDRESS)

COL n

DQ DIN n (DATA)

DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com 43

Rev. B
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IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

write - full page burst

T0 T1 T2 T3 T4 T5 Tn+1 Tn+2
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP

tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2)
tAS tAH
A10 ROW
tAS tAH
BA0, BA1 BANK BANK
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN m DIN m+1 DIN m+2 DIN m+3 DIN m-1
tRCD
Full page completed DON'T CARE

Notes:
1) Burst Length = Full Page
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

44 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
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WRITE - DQM OPERATION

T0 T1 T2 T3 T4 T5 T6 T7
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2)
tAS tAH ENABLE AUTO PRECHARGE

A10 ROW
tAS tAH DISABLE AUTO PRECHARGE

BA0, BA1 BANK BANK

tDS tDH tDS tDH tDS tDH
DQ DIN m DIN m+2 DIN m+3
tRCD
DON'T CARE

Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com 45

Rev. B
05/12/2015
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ALTERNATING BANK WRITE ACCESSES

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK tCK tCL tCH

tCKS tCKH
CKE
tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW COLUMN b(2) ROW
tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
A10 ROW ROW ROW
tAS tAH
BA0, BA1 BANK 0 BANK 0 BANK 1 BANK 1 BANK 0
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m+1 DIN m+2 DIN m+3 DIN b DIN b+1 DIN b+2 DIN b+3
tRCD - BANK 0 tDPL - BANK 0 tRP - BANK 0 tRCD - BANK 0
tRRD tRCD - BANK 1 tDPL - BANK 1
tRAS - BANK 0
tRC - BANK 0

DON'T CARE

Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

46 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst of a suspended internal clock edge is ignored; any data
is in progress and CKE is registered LOW. In the clock present on the DQ pins remains driven; and burst counters
suspend mode, the internal clock is deactivated, “freezing” are not incremented, as long as the clock is suspended.
the synchronous logic. (See following examples.)
For each positive clock edge on which CKE is sampled Clock suspend mode is exited by registering CKE HIGH;
LOW, the next internal positive clock edge is suspended. the internal clock and related operation will resume on the
Any command or data present on the input pins at the time subsequent positive clock edge.

Clock Suspend During WRITE Burst

T0 T1 T2 T3 T4 T5
CLK

CKE

INTERNAL
CLOCK

COMMAND NOP WRITE NOP NOP

ADDRESS BANK a,
COL n

DQ DIN n DIN n+1 DIN n+2

DON'T CARE

Clock Suspend During READ Burst

T0 T1 T2 T3 T4 T5 T6
CLK

CKE

INTERNAL
CLOCK

COMMAND READ NOP NOP NOP NOP NOP

ADDRESS BANK a,
COL n

DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3

DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com 47

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

Clock Suspend Mode

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK tCK tCL tCH

tCKS tCKH tCKS tCKH

CKE
tCMS tCMH

COMMAND READ NOP NOP NOP NOP NOP WRITE NOP

tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 COLUMN m(2) COLUMN n(2)
tAS tAH
A10
tAS tAH
BA0, BA1 BANK BANK
tDS tDH
tAC tAC tHZ
DQ DOUT m DOUT m+1 DIN e DIN e+1
tLZ tOH
DON'T CARE
UNDEFINED

Notes:
1) Cas latency = 3, Burst Length = 2, Auto Precharge is disabled.
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

48 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

PRECHARGE PRECHARGE Command

The PRECHARGE command (see figure) is used to deac-
tivate the open row in a particular bank or the open row in
all banks.The bank(s) will be available for a subsequent row CLK
access some specified time (trp) after the PRECHARGE
command is issued. Input A10 determines whether one or HIGH
CKE
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0, CS
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated RAS
prior to any READ or WRITE commands being issued to
that bank. CAS

WE
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
A0-A9, A11, A12
with a NOP or COMMAND INHIBIT when no accesses
ALL BANKS
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; A10
BANK SELECT
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down. BA0, BA1 BANK ADDRESS
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-down
state longer than the refresh period (64ms) since no refresh
operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tcks). See figure "Power-Down".

POWER-DOWN

CLK
tCKS ≥ tCKS
CKE

COMMAND NOP NOP ACTIVE

All banks idle Input buffers gated off tRCD
tRAS
Enter power-down mode Exit power-down mode tRC

less than 64ms DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com 49

Rev. B
05/12/2015
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Power-Down Mode Cycle

T0 T1 T2 Tn+1 Tn+2
CLK tCK tCL tCH

tCKS tCKH tCKS tCKS

CKE

tCMS tCMH
COMMAND PRECHARGE NOP NOP NOP ACTIVE

DQM/DQML
DQMH

A0-A9, A11, A12 ROW

ALL BANKS
A10 ROW
SINGLE BANK
tAS tAH
BA0, BA1 BANK BANK

DQ High-Z
Two clock cycles Input buffers gated All banks idle
off while in
Precharge all All banks idle, enter power-down mode
active banks power-down mode Exit power-down mode DON'T CARE

50 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming SDRAMs support CONCURRENT AUTO PRECHARGE.
the write burst mode bit (M9) in the mode register to a logic Four cases where CONCURRENT AUTO PRECHARGE
1. In this mode, all WRITE commands result in the access occurs are defined below.
of a single column location (burst of one), regardless of READ with Auto Precharge
the programmed burst length. READ commands access
1. Interrupted by a READ (with or without auto precharge):
columns according to the programmed burst length and
A READ to bank m will interrupt a READ on bank n,
sequence, just as in the normal mode of operation (M9
CAS latency later. The PRECHARGE to bank n will
= 0).
begin when the READ to bank m is registered.
CONCURRENT AUTO PRECHARGE 2. Interrupted by a WRITE (with or without auto precharge):
An access command (READ or WRITE) to another bank A WRITE to bank m will interrupt a READ on bank n
while an access command with auto precharge enabled is when registered. DQM should be used three clocks prior
executing is not allowed by SDRAMs, unless the SDRAM to the WRITE command to prevent bus contention. The
supports CONCURRENT AUTO PRECHARGE. ISSI PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
READ With Auto Precharge interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK

READ - AP READ - AP
COMMAND NOP BANK n NOP BANK m NOP NOP NOP NOP

BANK n Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle

Internal States tRP - BANK n tRP - BANK m

BANK m Page Active READ with Burst of 4 Precharge

ADDRESS BANK n, BANK n,

COL a COL b

DQ DOUT a DOUT a+1 DOUT b DOUT b+1

CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m) DON'T CARE

READ With Auto Precharge interrupted by a WRITE

T0 T1 T2 T3 T4 T5 T6 T7
CLK

READ - AP WRITE - AP
COMMAND BANK n NOP NOP NOP BANK m NOP NOP NOP

BANK n READ with Burst of 4 Interrupt Burst, Precharge Idle

Page Active tRP - BANK n tDPL - BANK m
Internal States
BANK m Page Active WRITE with Burst of 4 Write-Back

ADDRESS BANK n, BANK m,

COL a COL b

DQM

DQ DOUT a DIN b DIN b+1 DIN b+2 DIN b+3

CAS Latency - 3 (BANK n)
DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com 51

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WRITE with Auto Precharge

3. Interrupted by a READ (with or without auto precharge): 4. Interrupted by a WRITE (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when AWRITE to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing (CAS latency) registered. The PRECHARGE to bank n will begin after
later. The PRECHARGE to bank n will begin after tdpl tdpl is met, where tdpl begins when the WRITE to bank
is met, where tdpl begins when the READ to bank m is m is registered. The last valid data WRITE to bank n
registered. The last valid WRITE to bank n will be data-in will be data registered one clock prior to a WRITE to
registered one clock prior to the READ to bank m. bank m.

WRITE With Auto Precharge interrupted by a READ

T0 T1 T2 T3 T4 T5 T6 T7
CLK

WRITE - AP READ - AP
COMMAND NOP BANK n NOP BANK m NOP NOP NOP NOP

BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Internal States tDPL - BANK n tRP - BANK n

tRP - BANK m
BANK m Page Active READ with Burst of 4 Precharge

ADDRESS BANK n, BANK m,

COL a COL b

DQ DIN a DIN a+1 DOUT b DOUT b+1

CAS Latency - 3 (BANK m)

DON'T CARE

WRITE With Auto Precharge interrupted by a WRITE

T0 T1 T2 T3 T4 T5 T6 T7
CLK

WRITE - AP WRITE - AP
COMMAND NOP BANK n NOP NOP BANK m NOP NOP NOP

BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Internal States tDPL - BANK n tRP - BANK n

tDPL - BANK m
BANK m Page Active WRITE with Burst of 4 Write-Back

ADDRESS BANK n, BANK m,

COL a COL b

DQ DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3

DON'T CARE

52 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
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READ WITH AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH ENABLE AUTO PRECHARGE
A10 ROW ROW
tAS tAH
BA0, BA1 BANK BANK BANK
tAC tAC tAC tAC tHZ
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m+3
tLZ tOH tOH tOH tOH
tRCD CAS Latency DON'T CARE
tRAS tRP
tRC UNDEFINED

Notes:
1) Cas latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com 53

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

READ WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH
ALL BANKS
A10 ROW ROW
tAS tAH DISABLE AUTO PRECHARGE SINGLE BANK
BA0, BA1 BANK BANK BANK BANK
tAC tAC tAC tAC tHZ
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m+3
tLZ tOH tOH tOH tOH
tRCD CAS Latency DON'T CARE
tRAS tRP
UNDEFINED
tRC

Notes:
1) Cas latency = 2, Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

54 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

SINGLE READ WITH AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP

tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH ENABLE AUTO PRECHARGE
A10 ROW ROW
tAS tAH
BA0, BA1 BANK BANK BANK
tAC tOH
DQ DOUT m
tHZ
tRCD CAS Latency DON'T CARE
tRAS tRP UNDEFINED
tRC

Notes:
1) Cas latency = 2, Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com 55

Rev. B
05/12/2015
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SINGLE READ WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE

tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP PRECHARGE NOP ACTIVE NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH ALL BANKS
A10 ROW ROW
tAS tAH DISABLE AUTO PRECHARGE SINGLE BANK
BA0, BA1 BANK BANK BANK BANK
tAC tOH
DQ DOUT m
tLZ tHZ
tRCD CAS Latency DON'T CARE
tRAS tRP UNDEFINED
tRC

Notes:
1) Cas latency = 2, Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

56 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

WRITE - WITH AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK tCK tCL tCH

tCKS tCKH
CKE
tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH
ENABLE AUTO PRECHARGE
A10 ROW ROW
tAS tAH
BA0, BA1 BANK BANK BANK
tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m+1 DIN m+2 DIN m+3

tRCD tDPL tRP
tRAS
tRC

DON'T CARE

Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com 57

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

WRITE - WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE
tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP NOP PRECHARGE NOP ACTIVE
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH
ALL BANKS
A10 ROW ROW
tAS tAH DISABLE AUTO PRECHARGE SINGLE BANK
BA0, BA1 BANK BANK BANK BANK
tDS tDH tDS tDH tDS tDH tDS tDH

DQ DIN m DIN m+1 DIN m+2 DIN m+3

tRCD tDPL(3) tRP
tRAS
tRC
DON'T CARE

Notes:
1) Burst Length = 4
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"
3) tras must not be violated.

58 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

SINGLE WRITE WITH AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK tCK tCL tCH

tCKS tCKH

CKE
tCMS tCMH

COMMAND ACTIVE NOP NOP NOP WRITE NOP NOP NOP ACTIVE NOP
tCMS tCMH
DQM/DQML, DQMH

tAS tAH
A0-A9, A11, A12
ROW COLUMN m(2) ROW
tAS tAH ENABLE AUTO PRECHARGE
A10
ROW ROW
tAS tAH
BA0, BA1
BANK BANK BANK
tDS tDH
DQ
DIN m
tRCD tDPL tRP
tRAS
DON'T CARE
tRC

Notes:
1) Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com 59

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

SINGLE WRITE - WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCK tCL tCH

tCKS tCKH
CKE
tCMS tCMH

COMMAND ACTIVE NOP WRITE NOP NOP PRECHARGE NOP ACTIVE NOP
tCMS tCMH
DQM/DQML
DQMH
tAS tAH
A0-A9, A11, A12 ROW COLUMN m(2) ROW
tAS tAH DISABLE AUTO PRECHARGE ALL BANKS
A10 ROW ROW
tAS tAH SINGLE BANK

BA0, BA1 BANK BANK BANK BANK

tDS tDH

DQ DIN m
tRCD tDPL(3) tRP
tRAS
DON'T CARE
tRC

Notes:
1) Burst Length = 1
2) x8: A12 = "Don't Care"
x16: A11, A12 = "Don't Care"
x32: A9, A11, A12 = "Don't Care"
3) tras must not be violated.

60 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

ORDERING INFORMATION - Vdd = 2.5V for x16

Commercial Range: 0oC to +70oC
Frequency Speed (ns) Order Part No. Package
200 MHz 5 IS42R16320D-5TL 54-Pin TSOPII, Lead-free
IS42R16320D-5BL 54-ball BGA, Lead-free
167 MHz 6 IS42R16320D-6TL 54-Pin TSOPII, Lead-free
IS42R16320D-6BL 54-ball BGA, Lead-free
143 MHz 7 IS42R16320D-7TL 54-Pin TSOPII, Lead-free
IS42R16320D-7BL 54-ball BGA, Lead-free

Industrial Range: -40oC to +85oC

Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS42R16320D-6TLI 54-Pin TSOPII, Lead-free
IS42R16320D-6BLI 54-ball BGA, Lead-free
143 MHz 7 IS42R16320D-7TLI 54-Pin TSOPII, Lead-free
IS42R16320D-7BLI 54-ball BGA, Lead-free

ORDERING INFORMATION - VDD = 2.5V for x32

Commercial Range: 0°C to +70°C
Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS42R32160D-6BL 90-Ball BGA, Lead-free
143 MHz 7 IS42R32160D-7BL 90-Ball BGA, Lead-free

Industrial Range: -40°C to +85°C

Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS42R32160D-6BLI 90-Ball BGA, Lead-free
143 MHz 7 IS42R32160D-7BLI 90-Ball BGA, Lead-free

For 2.5V and automotive product support, please contact ISSI.

Integrated Silicon Solution, Inc. — www.issi.com 61

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ORDERING INFORMATION - Vdd = 3.3V for x8

Commercial Range: 0oC to +70oC
Frequency Speed (ns) Order Part No. Package
200 MHz 5 IS42S86400D-5TL 54-Pin TSOPII, Lead-free
167 MHz 6 IS42S86400D-6TL 54-Pin TSOPII, Lead-free
143 MHz 7 IS42S86400D-7TL 54-Pin TSOPII, Lead-free

Industrial Range: -40oC to +85oC

Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS42S86400D-6TLI 54-Pin TSOPII, Lead-free
143 MHz 7 IS42S86400D-7TLI 54-Pin TSOPII, Lead-free

ORDERING INFORMATION - Vdd = 3.3V for x16

Commercial Range: 0oC to +70oC
Frequency Speed (ns) Order Part No. Package
200 MHz 5 IS42S16320D-5TL 54-Pin TSOPII, Lead-free
IS42S16320D-5BL 54-ball BGA, Lead-free
167 MHz 6 IS42S16320D-6TL 54-Pin TSOPII, Lead-free
IS42S16320D-6BL 54-ball BGA, Lead-free
143 MHz 7 IS42S16320D-7TL 54-Pin TSOPII, Lead-free
IS42S16320D-7BL 54-ball BGA, Lead-free

Industrial Range: -40oC to +85oC

Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS42S16320D-6TLI 54-Pin TSOPII, Lead-free
IS42S16320D-6BLI 54-ball BGA, Lead-free
143 MHz 7 IS42S16320D-7TLI 54-Pin TSOPII, Lead-free
IS42S16320D-7BLI 54-ball BGA, Lead-free

62 Integrated Silicon Solution, Inc. — www.issi.com

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05/12/2015
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ORDERING INFORMATION - Vdd = 3.3V for x16

Automotive Range, A1: -40oC to +85oC
Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS45S16320D-6TLA1 54-Pin TSOPII, Lead-free
IS45S16320D-6BLA1 54-ball BGA, Lead-free
143 MHz 7 IS45S16320D-7TLA1 54-Pin TSOPII, Lead-free
IS45S16320D-7CTLA1 54-Pin TSOPII, Copper Lead frame, Lead-free
IS45S16320D-7BLA1 54-ball BGA, Lead-free

Automotive Range, A2: -40oC to +105oC

Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS45S16320D-7TLA2 54-Pin TSOPII, Lead-free
IS45S16320D-7CTLA2 54-Pin TSOPII, Copper Lead frame, Lead-free
IS45S16320D-7BLA2 54-ball BGA, Lead-free

ORDERING INFORMATION - VDD = 3.3V for x32

Commercial Range: 0°C to +70°C
Frequency Speed (ns) Order Part No. Package
200 MHz 5 IS42S32160D-5BL 90-Ball BGA, Lead-free
167 MHz 6 IS42S32160D-6BL 90-Ball BGA, Lead-free
143 MHz 7 IS42S32160D-7BL 90-Ball BGA, Lead-free

Industrial Range: -40°C to +85°C

Frequency Speed (ns) Order Part No. Package
167 MHz 6 IS42S32160D-6BLI 90-Ball BGA, Lead-free
143 MHz 7 IS42S32160D-7BLI 90-Ball BGA, Lead-free
143 MHz 7 IS42S32160D-7BI 90-Ball BGA, Leaded

Note: Contact ISSI for leaded parts support.

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Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

D1
0.80
Package Outline

0.45

NOTE :
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
08/14/2008

64 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

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05/12/2015
IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

2. Reference document : JEDEC MS-207

NOTE :
Package Outline

1. CONTROLLING DIMENSION : MM .
08/29/2008

66 Integrated Silicon Solution, Inc. — www.issi.com

Rev. B
05/12/2015