CDA 4253 FGPA System Design
Xilinx FPGA Memories
Dr. Hao Zheng
Comp Sci & Eng
University of South Florida
Xilinx 7-Series FPGA Architecture
On-Chip block RAM On-Chip block RAM
Distributed
Distributed RAM by
RAM by Logic Fabric
Logic Fabric
Recommended Reading
• 7 Series FPGA Memory Resources: User Guide
Google search: UG473
• 7 Series FPGA Configurable Logic Block: User Guide
Google search: UG474
• Xilinx 7 Series FPGA Embedded Memory Advantages: White
Paper
Google search: WP377
• XST User Guide for Virtex-6, Spartan-6, and 7 Series Device
Google search: UG687
• Chu’s book, chapter 7
3
Memory Types
4
Generic Memory Types
Memory
RAM ROM
Memory
Single port Dual port
Memory
With asynchronous With synchronous
read read
5
Memory Types Specific to Xilinx FPGAs
Memory
Distributed Block RAM-based
(MLUT-based) (BRAM-based)
Memory
Inferred Instantiated
Manually Using CORE
Generator
6
On-Chip Memory
➜ Distributed RAM
➜ Synchronous write
➜ Asynchronous read
➜ Block Ram
➜ Synchronous write
➜ Synchronous read
7
FPGA Distributed Memory
7 Series FPGAs Configurable Logic Block User Guide
UG474 (v1.7) November 17, 2014
8
Zynq-7000 SoC Data Sheet: Overview
Table 1: Zynq-7000 and Zynq-7000S SoCs (Cont’d)
Device Name Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100
Part Number XC7Z007S XC7Z012S XC7Z014S XC7Z010 XC7Z015 XC7Z020 XC7Z030 XC7Z035 XC7Z045 XC7Z100
Xilinx 7 Series
Artix®-7 Artix-7 Artix-7 Artix-7 Artix-7 Artix-7 Kintex®-7 Kintex-7 Kintex-7 Kintex-7
Programmable Logic
FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA
Equivalent
Programmable Logic
23K 55K 65K 28K 74K 85K 125K 275K 350K 444K
Cells
Look-Up Tables (LUTs) 14,400 34,400 40,600 17,600 46,200 53,200 78,600 171,900 218,600 277,400
Flip-Flops 28,800 68,800 81,200 35,200 92,400 106,400 157,200 343,800 437,200 554,800
Programmable Logic
Block RAM 1.8 Mb 2.5 Mb 3.8 Mb 2.1 Mb 3.3 Mb 4.9 Mb 9.3 Mb 17.6 Mb 19.2 Mb 26.5 Mb
(# 36 Kb Blocks) (50) (72) (107) (60) (95) (140) (265) (500) (545) (755)
DSP Slices
66 120 170 80 160 220 400 900 900 2,020
(18x25 MACCs)
Peak DSP
73 131 187 100 200 276 593 1,334 1,334 2,622
Performance
GMACs GMACs GMACs GMACs GMACs GMACs GMACs GMACs GMACs GMACs
(Symmetric FIR)
PCI Express
(Root Complex or Gen2 x4 Gen2 x4 Gen2 x4 Gen2 x8 Gen2 x8 Gen2 x8
Endpoint)(3)
Analog Mixed Signal 2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
(AMS) / XADC
Security(2) AES and SHA 256b for Boot Code and Programmable Logic Configuration, Decryption, and Authentication
Notes:
1. Restrictions apply for CLG225 package. Refer to the UG585, Zynq-7000 SoC Technical Reference Manual (TRM) for details.
2. Security is shared by the Processing System and the Programmable Logic.
Source: Zynq-7000 SoC Data Sheet: Overview, DS 190
3. Refer to PG054, 7 Series FPGAs Integrated Block for PCI Express for PCI Express support in specific devices.
9
X0Y0 X2Y0
7 Series FPGA CLB Resources UG474_c2_01_092210
Figure 2-2: Row and Column Relationship between CLBs and Slices
ce Configurations
Table 2-1 summarizes the logic resources in one CLB. Each SLICEM LUT can be configured
as a look-up table, distributed RAM, or a shift register.
Table 2-1: Logic Resources in One CLB
Arithmetic and
Slices LUTs Flip-Flops Distributed RAM(1) Shift Registers(1)
Carry Chains
2 8 16 2 256 bits 128 bits
Notes:
1. SLICEM only, SLICEL does not have distributed RAM or shift registers.
10
Table 2-3 shows the number of LUTs (four per slice) occupied by each distributed RAM
configuration. See UG953, Vivado Design Suite 7 Series FPGA and Zynq-7000 All
7 Series FPGA Distributed RAM Config.
Programmable SoC Libraries Guide for details of available distributed RAM primitives.
Table 2-3: Distributed RAM Configuration
RAM Description Primitive Number of LUTs
32 x 1S Single port RAM32X1S 1
32 x 1D Dual port RAM32X1D 2
32 x 2Q Quad port RAM32M 4
32 x 6SDP Simple dual port RAM32M 4
64 x 1S Single port RAM64X1S 1
64 x 1D Dual port RAM64X1D 2
64 x 1Q Quad port RAM64M 4
64 x 3SDP Simple dual port RAM64M 4
128 x 1S Single port RAM128X1S 2
128 x 1D Dual port RAM128X1D 4
256 x 1S Single port RAM256X1S 4
Distributed RAM configurations include:
11
Single-Port 64x1-bit Distributed RAM
RAM64X1S
SPRAM64
(DI) O
D DI1 O6 Output
6 (D[6:1]) Registered
A[5:0] A[6:1] D Q
Output
6
WA[6:1]
(CLK) (Optional)
WCLK CLK
(WE/CE)
WE WE
UG474_c2_07_101210
Four of 2-8:
Figure these64signal port 64x1
X 1 Single Port RAMs can be
Distributed implemented
RAM (RAM64X1S)in
a single SLICEM to form a 64x4b RAM.
ngle-port 64 x 1-bit modules are each built as shown in Figure 2-8, the fo
12
enable, and shared read and write port address inputs. This configuration equates to a
Dual-Port 64x1b Distributed RAM
64 x 2-bit dual-port distributed RAM.
Ref Target - Figure 2-9
RAM64X1D
DPRAM64
(DI) SPO
D DI1 O6
(D[6:1]) 6 Registered
A[5:0] A[6:1] D Q
Output
6
WA[6:1]
(CLK) (Optional)
WCLK CLK
(WE/CE)
WE WE
DPRAM64
DPO
DI1 O6
(C[6:1]) 6 Registered
DPRA[5:0] A[6:1] D Q
Output
6
WA[6:1]
(Optional)
CLK
WE
UG474_c2_08_101210
Distributed RAM (Available in SLICEM Only)
Single-Port 128x1b Distributed RAM
X-Ref Target - Figure 2-12
RAM128X1S
A6 (CX)
SPRAM64
(DI)
D DI1 O6
[5:0]
A[6:0] A[6:1]
7
WA[7:1]
(CLK)
WCLK CLK
(WE/CE)
WE WE
0
Output
SPRAM64 Registered
F7BMUX D Q
Output
DI1 O6
[5:0]
(Optional)
A[6:1]
7
WA[7:1]
CLK
WE
UG474_c2_11_101210
Three configurations are available: ROM64X1, ROM128X1, and ROM256X1. ROM contents
are loaded at each device configuration. Table 2-4 shows the number of LUTs occupied by
7 Series FPGA ROM Configurations on LUTs
each ROM configuration size.
Table 2-4: ROM Configuration
ROM Number of LUTs
64 x 1 1
128 x 1 2
256 x 1 4
Configuration
rs (Available Primitives:
in SLICEM Only)
• ROM64X1
A SLICEM function generator can also be configured as a 32-bit shift register without using
the flip-flops available in a slice. Used in this way, each LUT can delay serial data from 1 to
32 clock ROM128X1
• cycles. The shiftin D (DI1 LUT pin) and shiftout Q31 (MC31 LUT pin) lines cascade
ROM256X1
LUTs•to form larger shift registers. The four LUTs in a SLICEM are thus cascaded to
produce delays up to 128 clock cycles. It is also possible to combine shift registers across
more than one SLICEM. There are no direct connections between slices to form longer shift
LUTs
registers, nor isare often
the MC31 used
output to
at LUTimplemented small
B/C/D available. The
delays can be used to balance the timing of data pipelines.
memories
resulting programmable
with less than 256 bits.
15
FPGA Block RAM
7 Series FPGAs Memory Resources User Guide
UG 473 2014
16
Location of Block RAMs
On-Chip block RAM On-Chip block RAM
Use block RAM for storage with 64+ depth or 16+ width.
17
7 Series FPGA Block RAM Resources Zynq-7000 SoC Data Sheet: Overview
Table 1: Zynq-7000 and Zynq-7000S SoCs (Cont’d)
Device Name Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100
Part Number XC7Z007S XC7Z012S XC7Z014S XC7Z010 XC7Z015 XC7Z020 XC7Z030 XC7Z035 XC7Z045 XC7Z100
Xilinx 7 Series
Artix®-7 Artix-7 Artix-7 Artix-7 Artix-7 Artix-7 Kintex®-7 Kintex-7 Kintex-7 Kintex-7
Programmable Logic
FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA
Equivalent
Programmable Logic
23K 55K 65K 28K 74K 85K 125K 275K 350K 444K
Cells
Look-Up Tables (LUTs) 14,400 34,400 40,600 17,600 46,200 53,200 78,600 171,900 218,600 277,400
Flip-Flops 28,800 68,800 81,200 35,200 92,400 106,400 157,200 343,800 437,200 554,800
Programmable Logic
Block RAM 1.8 Mb 2.5 Mb 3.8 Mb 2.1 Mb 3.3 Mb 4.9 Mb 9.3 Mb 17.6 Mb 19.2 Mb 26.5 Mb
(# 36 Kb Blocks) (50) (72) (107) (60) (95) (140) (265) (500) (545) (755)
DSP Slices
66 120 170 80 160 220 400 900 900 2,020
(18x25 MACCs)
Peak DSP
73 131 187 100 200 276 593 1,334 1,334 2,622
Performance
GMACs GMACs GMACs GMACs GMACs GMACs GMACs GMACs GMACs GMACs
(Symmetric FIR)
PCI Express
(Root Complex or Gen2 x4 Gen2 x4 Gen2 x4 Gen2 x8 Gen2 x8 Gen2 x8
Endpoint)(3)
Analog Mixed Signal 2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
(AMS) / XADC
Security(2) AES and SHA 256b for Boot Code and Programmable Logic Configuration, Decryption, and Authentication
Notes:
1. Restrictions apply for CLG225 package. Refer to the UG585, Zynq-7000 SoC Technical Reference Manual (TRM) for details.
Each 36Kb block RAM can be configured as two
2. Security is shared by the Processing System and the Programmable Logic.
3. Refer to PG054, 7 Series FPGAs Integrated Block for PCI Express for PCI Express support in specific devices.
independent 18Kb RAM blocks.
18
Block RAM Configurations (Aspect Ratios)
1 2
0 4
0
0
16K x 2
8K x 4
4,095
32k x 1 16383
8+1
0
4k x (8+1)
4095
32+4
0
1023
1024 x 36
32767
19
Block RAM Interface
CASCADEOUTA CASCADEOUTB
36-Kbit Block RAM
True Dual Port 32
4
DIA
DIPA
16 Port A
ADDRA
Ports A and B are fully 4
WEA
independent. ENA
RSTREGA
32
RSTRAMA DOA
Each port has its own CLKA
REGCEA
DOPA 4
address, data in/out, 36 Kb
Memory
Array
clock, and WR enable. 32 32
DIB DOB
4 4
Both read/write are 16
DIPB
ADDRB
DOPB
4
synchronous. WEB
ENB Port B
RSTREGB
Simultaneously writing to RSTRAMB
the same address causes CLKB
REGCEB
data uncertainty.
CASCADEINA CASCADEINB
20
mode. 7 series FPGAs support these modes in SDP (READ_FIRST, WRIT
Block RAM Interface
Figure 1-6 shows the simple dual-port data flow for and RAMB36 in SD
Simple Dual Port
X-Ref Target - Figure 1-6
36 Kb Memory Array
64 64
DI DO
Independent read/write 8
DIP DOP
8
15
ports. RDADDR
RDCLK
Max port width is 64+8b. RDEN
REGCE
Reading & writing to the SSR
8
same mem location WE
15
causes data uncertainty. WRADDR
WRCLK
WREN
UG473_c1_06_011414
Figure 1-6: RAMB36 in the Simple Dual-Port Data Fl
21
22
VHDL Coding for Memory
XST User Guide for Virtex-6, Spartan-6, and 7 Series
Devices
Chapter 7, HDL Coding Techniques
Sections:
RAM HDL Coding Techniques
ROM HDL Coding Techniques
23
Distributed vs Block RAMs
• Distributed RAM: must be used for RAM descriptions
with asynchronous read.
• Block RAM: generally used for RAM descriptions with
synchronous read.
• Synchronous write for both types of RAMs.
• Any size and data width are allowed in RAM
descriptions.
- Depending on resource availability
• Up to two write ports are allowed.
24
Inferring ROM
25
Distributed ROM with Asynchronous Read
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
generic(w : integer := 7; -- number of bits per ROM word
r : integer := 4 -- 2^r = number of words in ROM
);
port (addr : in std_logic_vector(r-1 downto 0);
dout : out std_logic_vector(w-1 downto 0));
end ROM;
26
Distributed ROM with Asynchronous Read
architecture behavioral of ROM is
type rom_type is array (2**r-1 downto 0) of
std_logic_vector (w-1 downto 0);
constant ROM_array : rom_type := (
”1000000", ”1111001", ”0100100", ”0110000”,
”0011001", ”0010010", "0000010", "1111000”,
“0000000”. “0010000”, “0001000”, “0000011”,
“1000110”, “0100001”, “0000110”, “0001110”);
begin
dout <= ROM_array(conv_integer(addr));
end architecture behavioral;
How is it implemented?
27
--
-- A dual-port ROM
Dual-Port ROM with Sync. Read in VHDL
-- Implementation on LUT or BRAM controlled with a ram_style constraint
--
-- Download: http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/roms_dualport.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity roms_dualport is
port (clk : in std_logic;
ena, enb : in std_logic;
addra, addrb : in std_logic_vector(5 downto 0);
dataa, datab : out std_logic_vector(19 downto 0));
end roms_dualport;
architecture behavioral of roms_dualport is
type rom_type is array (63 downto 0) of std_logic_vector (19 downto 0);
signal ROM : rom_type:= (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
can be implemented X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
either on LUTs or X"04004", X"00304", X"04040", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
X"02500",
--block RAMs.
attribute ram_style : string;
-- attribute ram_style of ROM : signal is "distributed";
begin 28
X"04004", X"00304", X"04
X"0030D", X"02341", X"08
Dual-Port ROM with Sync. Read in VHDL
-- attribute ram_style : string;
-- attribute ram_style of ROM : signal is "distri
begin
process (clk)
begin
if rising_edge(clk) then
if (ena = ’1’) then
Port 1 dataa <= ROM(conv_integer(addra));
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (enb = ’1’) then
Port 2 datab <= ROM(conv_integer(addrb));
end if;
end if;
end process;
end behavioral;
29
Design Example
9
How to implement f = ⇥ c + 32 ?
5
30
Inferring RAM
31
Single-Port RAM with Async. Read
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity raminfr is
generic(w : integer := 32; -- number of bits per RAM word
r : integer := 3 -- 2^r = number of words in RAM
);
port(clk : in std_logic;
we : in std_logic;
addr: in std_logic_vector(r-1 downto 0);
di : in std_logic_vector(w-1 downto 0);
do : out std_logic_vector(w-1 downto 0));
end raminfr;
32
Single-Port RAM with Async. Read – cont’d
architecture behavioral of raminfr is
type ram_type is array (2**r-1 downto 0) of
std_logic_vector (w-1 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
RAM(conv_integer(addr)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(addr));-- async read
end behavioral;
33
Block RAM with Sync. Read (Read-First Mode)
34
Block RAM with Sync. Read (Read-First Mode)
35
Block RAM with Sync. Read (Read-First Mode)
process (clk)
begin
if rising_edge(clk) then
if (en = '1') then
do <= RAM(conv_integer(addr));
if (we = '1') then
RAM(conv_integer(addr)) <= di;
end if;
end if;
end if;
end process;
36
Block RAM with Sync. Read (Write-First
Mode)
37
Block RAM with Sync. Read (Write-First
Mode)
process (clk)
begin
if rising_edge(clk) then
if (en = '1') then
if (we = '1') then
RAM(conv_integer(addr)) <= di;
do <= di;
else
do <= RAM(conv_integer(addr));
end if;
end if;
end if;
end process;
38
Block RAM with Sync. Read (No-Change
Mode)
39
Block RAM with Sync. Read (No-Change
Mode)
process (clk)
begin
if rising_edge(clk) then
if (en = '1') then
if (we = '1') then
RAM(conv_integer(addr)) <= di;
else
do <= RAM(conv_integer(addr));
end if;
end if;
end if;
end process;
40
Block RAM Initialization
Example 1
type ram_type is array (0 to 127) of std_logic_vector(15 downto 0);
signal RAM : ram_type := (others => ”0000111100110101”;
Example 2
type ram_type is array (0 to 127) of std_logic_vector(15 downto 0);
signal RAM : ram_type := (others => (others => ‘1’));
Example 3
type ram_type is array (0 to 127) of std_logic_vector(15 downto 0);
signal RAM : ram_type := (196 downto 100 => X”B9B5”,
others => X”3344”);
41
Block RAM Initialization from a File
VHDL Coding Example
Load the data as follows.
type RamType is array(0 to 127) of bit_vector(31 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType’range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile("rams_20c.data");
use binary or hex, not mixing them
rams_20c.data:
001011000101111011110010000100001111 number of lines in the
XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices
101011000110011010101010110101110111
UG687 (v 14.5) March 20, 2013
…
128 file must match the
www.xilinx.com
number of rows in
101011110111001011111000110001010000 memory
42
Block RAM Interface
CASCADEOUTA CASCADEOUTB
36-Kbit Block RAM
True Dual Port 32
4
DIA
DIPA
16 Port A
ADDRA
Ports A and B are fully 4
WEA
independent. ENA
RSTREGA
32
RSTRAMA DOA
Each port has its own CLKA
REGCEA
DOPA 4
address, data in/out, 36 Kb
Memory
Array
clock, and WR enable. 32 32
DIB DOB
4 4
Both read/write are 16
DIPB
ADDRB
DOPB
4
synchronous. WEB
ENB Port B
RSTREGB
Simultaneously writing to RSTRAMB
the same address causes CLKB
REGCEB
data uncertainty.
CASCADEINA CASCADEINB
43
-- Correct Modelization with a Shared Variable
--
Dual-Port Block RAM
-- Download: http://www.xilinx.com/txpatches/pub/document
-- File: HDL_Coding_Techniques/rams/rams_16b.vhd
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity rams_16b is
port(clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
addra : in std_logic_vector(6 downto 0);
addrb : in std_logic_vector(6 downto 0);
dia : in std_logic_vector(15 downto 0);
dib : in std_logic_vector(15 downto 0);
doa : out std_logic_vector(15 downto 0);
dob : out std_logic_vector(15 downto 0));
end rams_16b;
architecture syn of rams_16b is 44
doa : out std_logic_vector(15 downto 0);
Dual-Port Block RAM
dob : out std_logic_vector(15 downto 0));
end rams_16b;
architecture syn of rams_16b is
type ram_type is array (127 downto 0) of std_logic_vector(15 downto 0);
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if CLKA’event and CLKA = ’1’ then
if ENA = ’1’ then
DOA <= RAM(conv_integer(ADDRA));
if WEA = ’1’ then
RAM(conv_integer(ADDRA)) := DIA;
Port A
end if;
end if;
end if;
end process;
process (CLKB)
begin
if CLKB’event and CLKB = ’1’ then
if ENB = ’1’ then
DOB <= RAM(conv_integer(ADDRB));
if WEB = ’1’ then
RAM(conv_integer(ADDRB)) := DIB; Port B
end if;
end if;
end if;
end process;
end syn;
45
Simple Dual-Port BRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_rw_port_ram is
generic( ADDR_WIDTH : integer := 10;
DATA_WIDTH : integer := 12);
port (clk : in std_logic;
we : in std_logic;
addr_w, addr_r : in
std_logic_vector(ADDR_WIDTH-1 downto 0);
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
end sync_rw_port_ram;
46
Simple Dual-Port BRAM
architecture beh_arch of sync_rw_port_ram is
type ram_type i s array (0 to 2** ADDR_WIDTH -1) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal ram : ram_type;
begin
process(clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
ram(to_integer(unsigned(addr_w))) <= din;
end if;
dout <= ram(to_integer(unsigned(addr_r)));
end if;
end process;
end beh_arch ;
47
Single-Port RAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_rw_port_ram is
generic( ADDR_WIDTH : integer := 10;
DATA_WIDTH : integer := 12);
port ( clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
end sync_rw_port_ram;
48
Single-Port BRAM
architecture beh_arch of sync_rw_port_ram is
type ram_type i s array (0 to 2** ADDR_WIDTH -1) of
std_logic_vector(DATA_WIDTH-1 downto 0);
signal ram : ram_type;
begin
process(clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
ram(to_integer(unsigned(addr))) <= din;
end if;
dout <= ram(to_integer(unsigned(addr)));
end if;
end process;
end beh_arch ;
49
Design Example - FIFO
FIFO BUFFE
Figure 7.2 Conceptual diagram of a FIFO buffer.
. array (2** ADDR_WIDTH -1 downto 0) o f ...
OM is synthesized as a combinational circuit with the logic cells.50 T
using a
Wiley & Sons, Incorporated. All rights reserved.
FIFO Design
circular buffer
51
