CSC 308 LECTURE NOTE

1.0 CONTROL UNIT TYPES

The control unit is the main component of a central processing unit (CPU) in computers that can
direct the operations during the execution of a program by the processor/computer. It is included
as a part of Von Neumann architecture.

The control unit has the following functions:

 It fetches and executes instructions from the memory of a computer.
 It receives the input instruction/information from the user and converts it into control
signals, which are then given to the CPU for further execution.
 It is responsible for providing the timing signals, and control signals and directs the
execution of a program by the CPU.
 It is included as an internal part of the CPU in modern computers.

There are two types of control unit: the hardwired control unit and the micro programmed control
unit. Instructions are executed with the help of these two control units.

In the hardwired control unit, the execution of operations is much faster, but the implementation,
modification, and decoding are difficult. In contrast, implementing, modifying, decoding micro-
programmed control units is very easy. The micro-programmed control unit is also able to handle
complex instructions. With the help of control signals generated by micro-programmed and
hardwired control units, fetching and execution of instructions are done.

Control Signals
The functionality of a processor's hardware is operated with the help of control signals. The control
signals function as described below:
 Control signals are used to know what operation is going to be performed.
 They are used to know about the sequence of operations that are performed by the
processor.
 They are used to know about the timing at which an operation must be executed and
many other types of things.

1.1 Hardwired Control Unit (HCU)

A hardwired control is a mechanism of producing control signals using Finite State machines
(FSM) appropriately. It is designed as a sequential logic circuit. The final circuit is constructed by
physically connecting the components such as gates, flip flops, and drums. Hence, it is named a
hardwired controller. With the help of generating control signals, the hardwired control unit is able
to execute the instructions at a correct time and proper sequence. The control signals are generated
with the help of PLA (programmable Logic Array) circuit and state counter. Here the Central
processing unit requires all these control signals. With the help of hardware, the hardwired control
signals are generated, and it basically uses the circuitry approach.
The hardwired control unit contains various components in the form of circuitry which will be
discussed one by one for proper understanding of the "generation of control signals". The
components of the hardwired CU are:
 Instruction register
 Instruction decoder
 Step Counter
 Clock
 Condition Signals
 External input

The Instruction Register is a type of processor register used to contain an instruction that is
currently in execution. The instruction register is used to generate the OP-code bits respective of
the operation as well as the addressing mode of operands.
The above generated Op-code bits are received in the field of an instruction decoder. The
instruction decoder interprets the operation and instruction's addressing mode. Now on the basis
of the addressing mode of instruction and operation which exists in the instruction register, the
instruction decoder sets the corresponding Instruction signal INSi to 1. Some steps are used to
execute each instruction, i.e., instruction,
fetch, decode, operand fetch, Arithmetic and logical unit, and memory store. In general, these
five steps are used to execute an instruction.
The information about the current step of instruction must be known by the control unit. The Step
Counter is implemented, which is used to contain the signals. For the step counter to know about
the current step of instruction, a Clock is implemented. The one-clock cycle of the clock will be
completed for each step.

When the execution in current step is completed, the Counter Enable will "disable" the Step
Counter so that it will stop, then increment to the next step signal.

The Condition Signals is used if the execution of instruction depends on some conditions. There
are various conditions in which the signals are generated with the help of control signals that can
be less than, greater than, less than equal, greater than equal, and many more.

The external input is the last one. It is used to tell the Control Signal Generator about the
interrupts, which will affect the execution of an instruction.

So, on the basis of the input obtained by the conditional signals, step counter, external inputs, and
instruction register, the control signals will be generated with the help of Control signal
Generator.
1.2 Micro-programmed Control Unit (MCU)
A micro-programmed control unit is a control unit whose binary control values are saved as words
in memory. A micro-programmed control unit is a simple logic circuit, useful in two ways, i.e., it
is able to execute each instruction with the help of generating control signals, and it is also able to
do sequencing through microinstructions. It will generate the control signals with the help of
programs. The program which is used to create the control signals is known as the "Micro-
program". The micro-program is placed on the processor chip, which is a type of fast memory.
This memory is also known as the control store or control memory.

A micro-program is used to contain a set of microinstructions (or control word), each of which
contains different bit patterns. The n bit words are contained by each microinstruction. On the
basis of the bit pattern of a control word, every control signals differ from each other.

The instruction execution in a micro-programmed control unit is also performed in steps, as in the
hardwired CU. So for each step, the micro-program contains a control word/ microinstruction. To
execute a particular instruction, a sequence of microinstructions is needed. This process is known
as the micro-routine.

1.2.1 Micro-programmed Control Unit cycle

Instruction fetch is the first step. In this step, the instruction is fetched from the Instruction
Register (IR) with the help of a Microinstruction address register.
Decode is the second step. In this step, the instructions obtained from the instruction register will
be decoded with the help of a microinstruction address generator. Here, the starting address of a
micro-routine is obtained, which enables an easy performance of the operation, which is mentioned
in the instruction. It will also load the starting address into the micro-program counter.
Increment is the third step. In this step, the control word, which corresponds to the starting
address of a micro-program, will be read. When the execution proceeds, the value of the micro-
program counter will be increased so that it can read the successive control words of a micro-
routine.
End bit is the fourth step. In this step, the microinstruction of a micro-routine contains a bit,
which is known as the end bit. The execution of the microinstruction will be successfully
completed when the end bit is set to 1.
This is the last step, and in this step, the micro-program address generator will again go back
to Step 1 so that we can fetch a new instruction, and this process or cycle goes on.
So in the micro-programmed control unit, the micro-programs are stored with the help of Control
memory or Control store. The implementation of this CU is very easy and flexible, but it is slower
as compared to the Hardwired control unit.
1.3 Differences Between Hardwired and Microprogrammed Control Unit

1.4 Advantages and Disadvantages of HCU and MCU

Advantages of Hardwired Control Unit

The following are the advantages of Hardwired control unit:
 Because of the use of combinational circuits to generate signals, Hardwired CU is
fast.
 It depends on number of gates and how much delay can occur in generation of
control signals.
 It can be optimized to produce the fast mode of operation.
 Faster than micro- programmed control unit.

Disadvantages
The following are the disadvantages of Hardwired control unit:
 The complexity of the design increases as it requires more control signals to be
generated (need of more encoders & decoders)
 Modifications in the control signals are very difficult because it requires
rearranging of wires in the hardware circuit.
 Adding a new feature is difficult & complex.
 Difficult to test & correct mistakes in the original design.
  It is Expensive.

Advantages of Micro programmed Control Unit

The following are the advantages of microprogrammed control unit:
 It is a more systematic design of the control unit.
 It is simpler to debug and change.
 It can retain the underlying structure of the control function.
 It can make the design of the control unit much simpler. Hence, it is inexpensive
and less error-prone.
 It is an orderly and systematic design process.
 It is used to control functions implemented in software and not hardware.
 It is more flexible.
Disadvantages
The following are the disadvantages of microprogrammed control unit:
 Adaptability is obtained at more cost.
 It is slower than a hardwired control unit.

2.0 MULTIPROCESSOR ARCHITECTURES

The performance of the computers has drastically increased when the technology has drifted from
uniprocessor systems to multiprocessor system. As the core computing units were made more
powerful, the performance of the processors also increased significantly. Uniprocessor system is
a type of architecture that is based on a single computing unit. All the operations were done
sequentially on the same unit. Multiprocessor systems are based on executing instructions on
multiple computing units. The multiprocessor architectures, is based on Flynn Taxonomy.
Flynn’s taxonomy is a classification of parallel computer architectures that are based on the
number of concurrent instruction and data streams available in the architecture. He proposed a
four-way classification of computer systems based on the notions of instruction streams and data
streams.

1. Single Instruction, Single Data (SISD)

2. Single Instruction, Multiple Data (SIMD)
3. Multiple Instruction, Single Data (MISD)
4. Multiple Instruction, Multiple Data (MIMD)

2.1 Single Instruction, Single Data (SISD):

This is a uniprocessor machine which is capable of executing a single instruction, operating on a
single data stream.
The machine instructions are processed in a sequential manner and computers adopting this model
are popularly called sequential computers.
Most conventional computers have SISD architecture.
All the instructions and data to be processed have to be stored in primary memory.

The speed of the processing element in the SISD model is limited by the rate at which the computer
can transfer information internally. SISD architectures are often found in:

 Early personal computers

 Simple embedded systems
 Basic calculators and devices that don't require high processing power

Characteristics:
i. Single Instruction Stream: SISD systems follow a single sequence of instructions.
This means that only one instruction is fetched, decoded, and executed at a time by the
processor.
ii. Single Data Stream: Only one data element is processed per instruction. Unlike more
advanced architectures like SIMD (Single Instruction, Multiple Data) or MIMD
(Multiple Instruction, Multiple Data), SISD processes one piece of data with each
instruction.
iii. Sequential Processing: Since only one instruction and one data element are involved,
SISD systems work sequentially. There’s no parallelism, meaning the processor can
only execute one operation at a time.
iv. Traditional Processor Design: SISD is found in older, simpler microprocessor
designs. Early computers, like those based on the von Neumann architecture, followed
the SISD model.

Advantages:
i. Simplicity: SISD systems are simple to design and implement since there’s no need for
parallel processing mechanisms or complex hardware.
ii. Cost-Effective: Due to their simplicity, SISD systems are typically less expensive to
manufacture, making them ideal for basic computing tasks.

Disadvantages:
i. Limited Performance: SISD systems are inherently slower than systems with parallelism
(like SIMD or MIMD) because each instruction works on only one piece of data at a time.
This makes SISD less efficient for tasks requiring large-scale computation.
ii. No Parallelism: There is no way to perform multiple operations simultaneously, which
limits its performance on modern, data-intensive applications like scientific computing or
large-scale simulations.

2.2 Single Instruction, Multiple Data (SIMD):

SIMD is another classification in Flynn’s taxonomy of computer architectures.
It is a type of parallel computing architecture where a single instruction is executed simultaneously
on multiple data elements.

This approach is highly efficient for operations involving large datasets, where the same operation
needs to be performed repeatedly across many data elements.

SIMD is commonly used in multimedia processing (like image, video, and audio processing),
scientific computations, and machine learning.

Characteristics of SIMD:
i. Single Instruction Stream: One instruction operates on multiple data elements at the same
time.
ii. Multiple Data Streams: SIMD allows multiple data elements to be processed at the same
time. For example, an instruction that adds a constant to an entire array of values would
apply the addition operation to each element of the array concurrently.
iii. Parallelism: The core strength of SIMD lies in its ability to perform operations in parallel.
By applying the same instruction to multiple data elements, SIMD processors can
dramatically improve performance for data-heavy tasks, especially those that involve
repetitive calculations.
iv. Vector Processors and GPUs: Often found in vector processors and graphical processing
units (GPUs), where large datasets (like pixel data, matrix operations, or vectors) can be
processed efficiently in parallel.

SIMD is commonly used in:

i. Multimedia Processing: Applications like image and video processing benefit greatly
from SIMD.
ii. Scientific Computation: SIMD architectures are used in simulations, numerical analysis,
and scientific computing where many data points can be processed in parallel.
iii. Graphics Processing: Graphical Processing Units (GPUs) are heavily based on SIMD
principles, enabling them to handle tasks like rendering, transformations, and shading
where many pixels or vertices need to be processed simultaneously.
iv. Machine Learning and AI: SIMD is effective in accelerating tasks like matrix
multiplications, which are common in deep learning algorithms.

Advantages:
i. Increased Performance: SIMD significantly improves performance for tasks that involve
large-scale repetitive computations.
ii. Efficient Use of Resources: SIMD allows processors to maximize their hardware
capabilities, making it more efficient than sequential execution.
iii. Energy Efficiency: By reducing the number of instructions required to process multiple
data elements, SIMD architectures can also help reduce energy consumption compared to
traditional SISD systems.
Disadvantages:
i. Limited Flexibility: SIMD is not suitable for tasks that involve operations on different
kinds of data or require complex decision-making for each element.
 ii. Data Alignment and Memory Access: SIMD systems typically require that data be
organized and aligned in specific ways for optimal performance. Misalignment can lead to
inefficiencies or slowdowns in execution.
iii. Software Complexity: Writing software to take full advantage of SIMD may require
specialized knowledge, as developers need to ensure that the data is structured properly.

2.3 Multiple Instruction, Single Data (MISD)

MISD is a relatively rare and less commonly implemented computer architecture in Flynn’s
taxonomy. In the MISD model, multiple instructions are applied to a single data element. This
means that different operations are performed on the same piece of data, often simultaneously, as
part of the architecture's design.
Characteristics:
i. Multiple Instruction Streams: MISD involves multiple instructions being applied to a
single piece of data. This means that the architecture processes different operations on the
same data element in parallel, or in a sequence that can overlap.
ii. Single Data Stream: Despite multiple instructions being executed, only one piece of data
is being processed. The data is passed through multiple functional units, each performing
a distinct operation, potentially in parallel.
iii. Specialized Applications: MISD is not commonly used in mainstream computing systems
because the need to perform multiple operations on a single data element at the same time
is relatively rare. However, it can be useful in specialized applications where the same data
needs to be subjected to various operations.
iv. Redundancy and Reliability: In some cases, MISD architectures might be used to ensure
redundancy or fault tolerance by applying different instructions to the same data and
comparing the results to detect errors.
Advantages:
i. Fault Tolerance: One of the primary advantages of MISD is its potential for redundancy
and error checking. By applying multiple different operations to the same data, systems
can cross-check the results to ensure accuracy and integrity, making it useful in
applications where reliability is critical.
ii. Redundant Processing for High Reliability: MISD architectures may be applied to
systems where redundant operations on a single piece of data can help detect and correct
errors, similar to voting mechanisms used in systems that require high reliability (like
space systems or high-security applications).
iii. Specialized Processing Tasks: In certain scenarios, applying different instructions to a
single data element simultaneously or sequentially might be useful. This could apply in
real-time systems where multiple operations need to be done in parallel for a specific type
of analysis.

Disadvantages:
i. Complexity and Efficiency: MISD is rarely used in practice because the requirement for
multiple instructions on a single data stream is not common. Most problems in computing
can be more effectively solved using other paradigms like SIMD or MIMD, where
parallelism is applied across multiple data points rather than focusing on a single data
element.
 ii. Limited Applicability: The types of applications where MISD would be useful are few.
Most tasks in modern computing involve processing multiple data elements at once, rather
than applying many instructions to one piece of data.
iii. Increased Hardware Requirements: Implementing MISD would require specialized
hardware to handle multiple instructions at the same time for a single data stream, which
increases the complexity and cost of the system.

MISD might be applicable in the following areas:

 Fault Tolerant Systems: In systems where data integrity and reliability are paramount
(e.g., space systems, critical military applications, or nuclear reactors), MISD architectures
could be used to apply multiple checks or operations to the same data for reliability
purposes.
 High-Security Applications: In environments where high-security encryption or
processing of sensitive data is required, MISD might be used to apply multiple security
protocols to the same data in parallel to ensure robustness.
 Error Detection and Correction: MISD can be used in systems designed to detect errors
in critical data by applying multiple distinct operations to ensure correctness. This could
be relevant in contexts where precision and failure prevention are more important than
speed.

2.4 Multiple Instruction, Multiple Data (MIMD)

MIMD refers to a parallel computing architecture where multiple processors can execute different
instructions on different data simultaneously. This is more flexible than SIMD, as each processor
can perform a different task at the same time. MIMD systems are ideal for general-purpose
computing and can handle more diverse workloads compared to SIMD.
Characteristics of MIMD:
i. Multiple processors work on different instructions, on different pieces of data.
ii. More complex than SIMD because it requires coordination between processors.
iii. Suitable for a variety of tasks like database processing, large-scale simulations, or
distributed computing.

3.0 INSTRUCTION PIPELINING

Pipelining refers to the technique in which a given task is divided into a number of subtasks that
need to be performed in sequence. Each subtask is performed by a given functional unit. The
units are connected in a serial fashion and all of them operate simultaneously.

Types of Pipeline:
It is divided into 2 categories:
i. Arithmetic Pipeline- Arithmetic pipelines are usually found in most of the computers.
They are used for floating point operations, multiplication of fixed point numbers etc.
ii. Instruction Pipeline- This is discussed further below.
Instruction pipelining is a technique used in modern processors to improve their performance by
overlapping the execution of multiple instructions. A stream of instructions can be executed by
overlapping fetch, decode and execute phases of an instruction cycle.
It allows the processor to work on several instructions at the same time, each at different stages of
execution, rather than executing one instruction completely before moving on to the next. This
process can increase throughput and overall performance of the computer system. The pipeline
will be more efficient if the instruction cycle is divided into segments of equal duration.

3.1 Stages of Instruction Pipelining

A typical pipeline consists of several stages, with each stage responsible for a specific part of the
instruction cycle. A simple five-stage pipeline might look like this:

1. Instruction Fetch (IF):

o The instruction is fetched from memory.
2. Instruction Decode (ID):
o The instruction is decoded, and the necessary operands are fetched from registers
or memory.
3. Execute (EX):
o The arithmetic or logical operation is performed, or an address is calculated for
memory access.
4. Memory Access (MEM):
o If the instruction involves memory (load or store), memory is accessed at this
stage.
5. Write Back (WB):
o The result of the operation is written back to a register or memory.

Example of Pipelining:

Imagine having 3 instructions:

1. ADD R1, R2, R3 (R1 = R2 + R3)

2. SUB R4, R5, R6 (R4 = R5 - R6)
3. MUL R7, R8, R9 (R7 = R8 * R9)

Without pipelining, the processor would execute them one by one, completing the ADD before
starting the SUB, and completing the SUB before starting the MUL.

With pipelining, while the ADD instruction is being executed, the SUB can be decoded and the
MUL can be fetched, effectively utilizing the CPU's resources more efficiently.

3.2 Advantages and disadvantages of Instruction Pipelining

Advantages:
 Increased throughput: More instructions can be completed in a given period, improving
overall performance.
  Reduced execution time: Pipelining enables faster execution because different stages of
multiple instructions can occur simultaneously.

Disadvantages
 The design of pipelined processor is complex and costly to manufacture.
 The instruction latency (the time it takes for an instruction to complete in a pipelined
processor) is more.

3.3 Pipeline Conflicts

There are some factors that cause the pipeline to deviate from its normal performance. Some of
these factors are given below:
 Timing Variations: All stages cannot take same amount of time. This problem generally
occurs in instruction processing where different instructions have different operand
requirements and thus different processing time.
 Data Hazards: When several instructions are in partial execution, and if they reference
same data then the problem arises. We must ensure that next instruction does not attempt
to access data before the current instruction, because this will lead to incorrect results.
 Interrupts: Interrupts set unwanted instruction into the instruction stream. Interrupts
effect the execution of instruction.
 Data Dependency: It arises when an instruction depends upon the result of a previous
instruction but this result is not yet available.

3.4 Challenges of Instruction Pipelining

 Hazards: Potential problems may arise when instructions depend on the results of
previous instructions, leading to pipeline stalls or delays.
o Data hazards: Occur when an instruction depends on the result of a previous
instruction.
o Control hazards: Occur when the flow of control changes (like in branches),
affecting the instruction pipeline.
o Structural hazards: Occur when two instructions need the same hardware
resource at the same time.
 Pipeline stalls: These are delays caused by hazards. For example, a data hazard might
require the pipeline to wait for a result before proceeding.

3.5 Solutions to Pipeline Hazards

 Forwarding (Data Forwarding): This allows data to be passed directly from one
pipeline stage to another without needing to wait for the data to be written back to
registers.
 Branch Prediction: Used to predict the outcome of branches to avoid control hazards.
 Stall Cycles: Sometimes the pipeline may intentionally pause execution (stall) to resolve
a hazard.
4.0 DATA TRANSFER MODES
In computer architecture, Input/Output (I/O) operations are essential for enabling communication
between the central processing unit (CPU) and external devices such as keyboards, displays, hard
drives, printers, and network interfaces. There are several mechanisms for managing how the CPU
interacts with I/O devices. These include:
 Handshaking
 Buffering
 Programmed I/O
 Interrupt- initiated I/O
 Direct memory access (DMA)

4.1 Handshaking

Handshaking is a method used for communication between the CPU and an I/O device in which
both parties signal each other to indicate readiness for data transfer. This ensures synchronization
between the two devices, avoiding issues such as data loss or corruption. In the context of I/O,
handshaking usually involves the use of control signals (e.g., Ready, Busy, Data Valid) between
the CPU and the I/O device. For instance, the CPU may send a signal to an I/O device indicating
that data is ready to be transmitted, and the device responds by signaling that it is prepared to
receive the data. Handshake protocols can be seen in serial communication, where two devices
exchange data one bit at a time, synchronizing their operations through a series of control signals.

4.2 Buffering

Buffering is a technique used to temporarily hold data in memory (the "buffer") during I/O
operations. Buffers act as temporary storage between the CPU and I/O devices, allowing for
smooth, efficient data transfer even when there is a difference in the speed of processing between
the two. Buffering allows asynchronous communication, for example, if the CPU is faster than
an I/O device (such as a printer), it can continue processing while the device slowly processes the
data in the buffer. It also helps manage differences in the data transfer rates of the CPU and I/O
devices. For example, when a keyboard inputs data faster than it can be processed, the data can be
buffered until the CPU is ready to process it.

Buffering can take place in memory (e.g., using RAM) or dedicated hardware buffers on I/O
devices, helping to prevent data loss or delays.

4.3 Programmed I/O (Polling)

Programmed I/O is a method where the CPU actively monitors and controls I/O operations by
checking the status of an I/O device in a loop. This method involves the CPU continuously
checking the device’s status register to see if it is ready to send or receive data. This is called
Polling. The CPU keeps checking until it gets a response.
Advantages: Simplicity and ease of implementation, as the CPU directly controls the I/O
operation.

Disadvantages: Inefficiency, as the CPU spends time checking the device even when it is not
ready, which can waste valuable processing time. The CPU can't do other tasks while it is polling,
For example, when polling a keyboard, the CPU may continuously check if a key has been pressed,
and when it detects the key press, it will process the input. This situation can be avoided by using
an interrupt facility.

4.4 Interrupt-Driven I/O

Interrupt-driven I/O is an improvement over programmed I/O where the CPU does not have to
actively poll the device. Instead, the I/O device generates an interrupt signal to notify the CPU
when it is ready to perform I/O operations. Interrupts are hardware signals sent by I/O devices to
alert the CPU that the device needs attention (e.g., data is available for reading or space is available
for writing).

When the CPU receives an interrupt, it temporarily stops its current tasks (this is called context
switching) and executes a special function called an interrupt service routine (ISR). After the
ISR finishes, the CPU resumes its previous work. For instance, in a system where an I/O device
(like a disk) sends data, the CPU will only process the data when the device interrupts it, instead
of constantly polling the device.

Advantages: More efficient than programmed I/O, as the CPU is free to perform other tasks while
waiting for the interrupt. The CPU is only interrupted when it is actually needed, reducing
unnecessary resource consumption.

Disadvantages: Interrupt handling adds overhead, as managing interrupts and context switching
requires additional resources.

4.5 Strengths and weaknesses

1. Handshaking

Strengths:

 Synchronization: Handshaking ensures that both the CPU and I/O device are synchronized
in their operations. The devices exchange signals to confirm that they are ready to
send/receive data, reducing the chance of data corruption.
 Simple to implement: The control signals used for handshaking are typically
straightforward, making it easy to implement for simple devices like keyboards or serial
communication.

Weaknesses:
  Overhead: Handshaking introduces some overhead in terms of time, as both devices must
exchange signals to confirm readiness, leading to delays in data transfer.
 Complexity in high-speed systems: As the speed of communication increases,
handshaking can become cumbersome, requiring more control lines or more complex
timing mechanisms.
 Limited scalability: Handshaking may not scale well when multiple devices need to
communicate with the CPU simultaneously, as each device would require individual
signaling.

2. Buffering

Strengths:

 Smooth data transfer: Buffering allows devices with differing speeds (such as the CPU
and a slow peripheral) to communicate without data loss. The buffer temporarily holds
data until the CPU is ready to process it.
 Improves efficiency: By storing data temporarily in the buffer, the CPU is not forced to
wait for every I/O operation to complete before continuing its tasks.
 Handles burst data: Buffering can effectively manage data bursts, such as a rapid stream
of data from a network interface, allowing the CPU to process data at its own pace.

Weaknesses:

 Memory usage: Buffers consume memory space, and depending on the system design,
this can become a significant overhead.
 Latency: Buffering introduces a delay because data must first be stored in the buffer
before it can be processed or sent to the destination. This may not be ideal for time-
sensitive applications.
 Complexity: Managing buffers (especially in cases with multiple I/O devices) can
introduce complexity in both hardware design and software.

3. Programmed I/O (Polling)

Strengths:

 Simple implementation: Programmed I/O is straightforward and easy to implement

since it involves the CPU checking device status in a loop.
 No extra hardware needed: Polling doesn't require additional interrupt-handling
hardware or complex mechanisms, making it cheaper in terms of hardware resources.
 Fine control: The CPU has direct control over when and how it interacts with the device,
which might be useful in some low-level or custom systems.

Weaknesses:
  Inefficient CPU usage: Polling wastes CPU time because it constantly checks the status
of a device even when the device isn't ready to communicate. This can significantly
reduce overall system performance, especially in systems with many I/O devices.
 CPU stalls: The CPU is idle or waiting, unable to perform other useful tasks while
polling. This can lead to poor utilization of processing power.
 Slow response times: Since polling is based on checking status periodically, there may
be a noticeable delay between when a device becomes ready and when the CPU actually
performs the I/O operation.

4. Interrupt-Driven I/O

Strengths:

 Efficient CPU usage: The CPU is free to perform other tasks until it is interrupted by an
I/O device, allowing the system to make better use of processing power.
 Immediate response: Interrupts provide quick reactions to events, allowing the CPU to
handle I/O operations as soon as the device is ready without unnecessary delays.
 Scalable: Interrupt-driven I/O can scale well in systems with multiple devices. The CPU
only needs to respond when an interrupt is received, instead of constantly checking the
status of each device.
 Real-time processing: Interrupts enable real-time handling of events, such as user inputs
or incoming network packets, making them suitable for systems requiring quick
responses.

Weaknesses:

 Complexity: Managing interrupts requires more complex hardware and software

systems, such as interrupt controllers and interrupt service routines (ISRs). Handling
multiple interrupts can also be challenging.
 Interrupt overhead: The need to stop the current execution and jump to the ISR can
introduce overhead. Context switching between tasks, especially in systems with frequent
interrupts, can impact performance.
 Interrupt storms: If too many interrupts occur in a short period, the system might
become overwhelmed. This can lead to missed interrupts or system delays if not properly
managed.

Summary of Comparison

Programmed I/O Interrupt-

Feature Handshaking Buffering
(Polling) Driven I/O
High (CPU is free
Low (waits for Moderate (depends Low (constantly
CPU Efficiency until an interrupt
signals) on buffer size) polling)
occurs)
 Programmed I/O Interrupt-
Feature Handshaking Buffering
(Polling) Driven I/O
Implementation Moderate (buffer High (interrupt
Simple Simple
Complexity management) handling needed)
Moderate
High (constant Moderate High (CPU checks (context
Overhead
signal exchange) (buffering delay) device repeatedly) switching
overhead)
High (immediate
Real-Time Low (depends on Low (waits for
Moderate response when
Responsiveness buffer size) polling)
interrupted)
Low (needs Moderate (depends High (easily
Low (one device
Scalability dedicated on buffer handles multiple
at a time)
signaling) management) devices)

5.0 FAULT TOLERANCE COMPUTING

INTRODUCTION
Technology scaling allows realization of more and more complex system on a single chip. This
high level of integration leads to increased current and power densities and causes early device
and interconnect wear-out. In addition, there are failures not caused by wear-out nor escaped
manufacturing defects, but due to increased susceptibility of transistors to high energy particles
from atmosphere or from within the packaging.
Fault tolerance refers to the property that enables the system to continue to function correctly even
when some of its components fail. In other words, fault tolerance means how an operating system
(OS) responds and allows hardware or software malfunctions and fails. The ability of OS to recover
and tolerate faults can be handled through software, hardware, or a combination solution that
leverages load balancers. Some computer systems use multiple duplicate fault tolerance systems
to handle faults, this is called a fault-tolerant network. Fault-tolerant systems use backup
components that automatically replace failed components to ensure that no break occurs in service.
Fault Tolerance in software is a phenomenon where the software is capable of fixing itself or
continuing the normal operations in the occurrence of any glitches or error in the system. The
reasons behind these faults in the software system can be a fault from within, fault from other
integrated systems, fault from the downstream application, or fault from any other external aspects
like the system hardware, network, etc. This is one of the factors based on which software is
estimated to be a quality one or not. Hence it is important that every software program consists of
fault tolerance.
Fault-tolerant computing is the art and science of building computing systems that continue to
operate satisfactorily in the presence of faults.
A fault tolerant system may be able to tolerate one or more fault-types including –
i) transient, intermittent or permanent hardware faults,
ii) software and hardware design errors,
iii) operator errors, or
iv) externally induced upsets or physical damage.

An operating system that offers a solid definition for faults cannot be disrupted by a single point
of failure. It ensures business continuity and the high availability of crucial applications and
systems regardless of any failures.
Fault tolerance and dependable systems research covers a wide spectrum of applications ranging
across:
 embedded real-time systems,
 commercial transaction systems,
 transportation systems,
 military and space systems, etc.
The supporting research for fault tolerance includes:
 system architecture,
 design techniques,
 coding theory,
 testing,
 validation,
 proof of correctness,
 modeling,
 software reliability,
 operating systems,
 parallel processing, and
 real-time processing.
These areas often involve widely diverse core expertise ranging from formal logic, mathematics
of stochastic modeling, graph theory, hardware design and software engineering.
5.1 Basic Terms of Fault Tolerance Computing
Fault tolerance can be built into a system to remove the risk of it having a single point of failure.
To do so, the system must have no single component that, if it were to stop working effectively,
would result in the entire system failing. Fault tolerance is reliant on aspects like load balancing
and failover, which remove the risk of a single point of failure. It will typically be part of the
operating system’s interface, which enables programmers to check the performance of data
throughout a transaction.
Three central terms in fault-tolerant design are fault, error, and failure. There is a cause effect
relationship between faults, errors, and failures. Specifically, faults are the cause of errors, and
errors are the cause of failures. Often the term failure is used interchangeably with the term
malfunction, however, the term failure is rapidly becoming the more commonly accepted one.
A fault is a physical defect, imperfection, or flaw that occurs within some hardware or software
component.
An error is the manifestation of a fault. Specifically, an error is a deviation from accuracy or
correctness. Finally, if the error results in the system performing one of its functions incorrectly
then a system failure has occurred.
A failure is the nonperformance of some action that is due or expected or the performance of some
function in a subnormal quantity or quality.
The concepts of faults, errors, and failures can be best presented by the use of a three-universe
model that is an adaptation of the four-universe models;
 the first universe is the physical universe in which faults occur. The physical universe
contains the semiconductor devices, mechanical elements, displays, printers, power
supplies, and other physical entities that make up a system. A fault is a physical defect or
alteration of some component within the physical universe.
 the second universe is the informational universe. The informational universe is where the
error occurs. Errors affect units of information such as data words within a computer or
digital voice or image information. An error has occurred when some unit of information
becomes incorrect.
 the final universe is the external or user’s universe. The external universe is where the user
of a system ultimately sees the effect of faults and errors. The external universe is where
failures occur. The failure is any deviation that occurs from the desired or expected
behavior of a system. In summary, faults are physical events that occur in the physical
universe. Faults can result in errors in the informational universe, and errors can ultimately
lead to failures that are witnessed in the external universe of the system.
The cause-effect relationship implied in the three-universe model leads to the definition of two
important parameters; fault latency and error latency.
 Fault latency is the length of time between the occurrence of a fault and the appearance of
an error due to that fault.
 Error latency is the length of time between the occurrence of an error and the appearance
of the resulting failure. Based on the three-universe model, the total time between the
occurrence of a physical fault and the appearance of a failure will be the sum of the fault
latency and the error latency.
5.2 Characteristics of Faults
Faults could be classified based on the following parameters
 a) Causes/Source of Faults
b) Nature of Faults
c) Fault Duration
d) Extent of Faults
e) Value of faults
a. Sources of faults: Faults can be the result of a variety of things that occur within electronic
components, external to the components, or during the component or system design process.
Problems at any of several points within the design process can result in faults within the system.
 Specification mistakes, which include incorrect algorithms, architectures, or
hardware and software design specifications.
 Implementation mistakes. Implementation, as defined here, is the process of
transforming hardware and software specifications into the physical hardware and
the actual software. The implementation can introduce faults because of poor
design, poor component selection, poor construction, or software coding mistakes.
 Component defects. Manufacturing imperfections, random device defects, and
component wear-out are typical examples of component defects. Electronic
components simply become defective sometimes. The defect can be the result of
bonds breaking within the circuit or corrosion of the metal. Component defects are
the most commonly considered cause of faults.
 External disturbance; for example, radiation, electromagnetic interference, battle
damage, operator mistakes, and environmental extremes.

b. Nature of faults: This specifies the type of fault; for example, whether it is a hardware
fault, a software fault, a fault in the analog circuitry, or a fault in the digital circuitry.
c. Fault Duration: The duration specifies the length of time that a fault is active.
 Permanent fault, that remains in existence indefinitely if no corrective action is
taken.
 Transient fault, which can appear and disappear within a very short period of time.
 Intermittent fault that appears, disappears, and then reappears repeatedly.

d. Fault Extent: The extent of a fault specifies whether the fault is localized to a given
hardware or software module or globally affects the hardware, the software, or both.

e. Fault value: The fault value of a fault can be either determinate or indeterminate. A
determinate fault is one whose status remains unchanged throughout time unless externally
acted upon. An indeterminate fault is one whose status at some time, T, may be different
from its status at some increment of time greater than or less than T.
Three primary techniques for maintaining a system’s normal performance in an environment
where faults are of concern are: fault avoidance, fault masking, and fault tolerance.
 Fault avoidance is a technique that is used in an attempt to prevent the occurrence
of faults. Fault avoidance can include such things as design reviews, component
screening, testing, and other quality control methods.
 Fault masking is any process that prevents faults in a system from introducing errors
into the informational structure of that system.
 Fault tolerance is the ability of a system to continue to perform its tasks after the
occurrence of faults. The ultimate goal of fault tolerance is to prevent system
failures from occurring. Since failures are directly caused by errors, the terms fault
tolerance and error tolerance are often used interchangeably.
Approaches for Fault Tolerance
 Fault masking is one approach to tolerating faults.
 Reconfiguration is the process of eliminating a faulty entity from a system and
restoring the system to some operational condition or state. If the reconfiguration
technique is used then the designer must be concerned with fault detection, fault
location, fault containment, and fault recovery.
 Fault detection is the process of recognizing that a fault has occurred. Fault
detection is often required before any recovery procedure can be implemented.
 Fault location is the process of determining where a fault has occurred so that an
appropriate recovery can be implemented.
 Fault containment is the process of isolating a fault and preventing the effects of
that fault from propagating throughout a system. Fault containment is required in
all fault-tolerant designs.
 Fault recovery is the process of remaining operational or regaining operational
status via reconfiguration even in the presence of faults.
Goals of Fault Tolerance
Fault tolerance is an attribute that is designed into a system to achieve some design goals such as;
dependability, reliability, availability, safety, performability, maintainability, and testability; fault
tolerance is one stem attribute capable of fulfilling such requirements.