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P-Channel Power MOSFETs Data Sheet

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0% found this document useful (0 votes)
73 views8 pages

P-Channel Power MOSFETs Data Sheet

Uploaded by

Thanh Le
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

RFD8P06E, RFD8P06ESM, RFP8P06E

Data Sheet July 1999 File Number 3937.5

8A, 60V, 0.300 Ohm, P-Channel Power Features


MOSFETs • 8A, 60V
These are P-Channel power MOSFETs manufactured using
• rDS(ON) = 0.300Ω
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives • Temperature Compensating PSPICE® Model
optimum utilization of silicon, resulting in outstanding • 2kV ESD Protected
performance. They were designed for use in applications
such as switching regulators, switching converters, motor • Peak Current vs Pulse Width Curve
drivers, relay drivers and emitter switches for bipolar • UIS Rating Curve
transistors. These transistors can be operated directly from
• 175oC Operating Temperature
integrated circuits.
• Related Literature
The RFD8P06E, RFD8P06ESM and RFP8P06E incorporate
- TB334 “Guidelines for Soldering Surface Mount
ESD protection and are designed to withstand 2kV (Human
Components to PC Boards”
Body Model) of ESD.

Formerly developmental type TA49044. Symbol


D
Ordering Information
PART NUMBER PACKAGE BRAND
G
RFP8P06E TO-220AB RFP8P06E

RFD8P06ESM TO-252AA D8P06E

RFD8P06E TO-251AA D8P06E


S
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e.
RFD8P06ESM9A.

Packaging
JEDEC TO-220AB JEDEC TO-251AA

SOURCE SOURCE
DRAIN DRAIN
GATE GATE
DRAIN (FLANGE)

DRAIN (FLANGE)

JEDEC TO-252AA

DRAIN (FLANGE)

GATE
SOURCE

4-117 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
[Link] or 407-727-9207 | Copyright © Intersil Corporation 1999.
RFD8P06E, RFD8P06ESM, RFP8P06E

Absolute Maximum Ratings TC = 25oC


RFD8P06E, RFD8P06ESM, RFP8P06E UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS -60 V
Drain to Gate Voltage (RGS = 20KΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 8 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Refer to Peak Current Curve A
Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 48 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.32 W/oC
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . .ESD 2 kV
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC

Maximum Temperature for Soldering


Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V -60 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA -2.0 - -4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - -1.0 µA
VDS = 0.8 x Rated BVDSS, TC = 150oC - - -25 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±10 µA
Drain to Source On Resistance (Note 3) rDS(ON) ID = 8A, VGS = -10V - - 0.300 Ω
Turn-On Time tON VDD = -30V, ID ≈ 8A, - - 70 ns
RL = 3.75Ω, VGS = -10V, RG = 2.5Ω
Turn-On Delay Time td(ON) - 15 - ns
(Figure 13)
Rise Time tr - 30 - ns
Turn-Off Delay Time td(OFF) - 40 - ns
Fall Time tf - 25 - ns
Turn-Off Time tOFF - - 100 ns
Total Gate Charge Qg(TOT) VGS = 0 to -20V VDD = -48V, ID = 8A, - 30 36 nC
Gate Charge at 5V Qg(-10) VGS = 0 to -10V RL = 6Ω - 15 18 nC
Ig(REF) = -1.45mA
Threshold Gate Charge Qg(TH) VGS = 0 to -2V - 1.15 1.5 nC
Input Capacitance CISS VDS = -25V, VGS = 0V, - 600 - pF
f = 1MHz
Output Capacitance COSS - 160 - pF
Reverse Transfer Capacitance CRSS - 35 - pF
Thermal Resistance Junction to Case RθJC Figure 12 - - 3.125 oC/W

Thermal Resistance Junction to Ambient RθJA TO-220 - - 62 oC/W

TO-251, TO-252 - - 100 oC/W

Source to Drain Diode Specifications


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = -8A - - -1.5 V
Diode Reverse Recovery Time trr ISD = -8A, dISD/dt = -100A/µs - - 125 ns
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

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RFD8P06E, RFD8P06ESM, RFP8P06E

Typical Performance Curves Unless Otherwise Specified

1.2 -10
POWER DISSIPATION MULTIPLIER

1.0
-8

ID , DRAIN CURRENT (A)


0.8
-6
0.6

-4
0.4

0.2 -2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

0.5
THERMAL IMPEDANCE
ZθJC , NORMALIZED

0.2
PDM
0.1
0.1
0.05
t1
0.02 t2
0.01
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t 1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE

-100 -102
TC = 25oC, TJ = MAX RATED
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
IDM , PEAK CURRENT (A)
ID , DRAIN CURRENT (A)

100µs
-10
 175 – T C
VGS = -20V I = I 25  ----------------------
 150 
1ms

10ms VGS = -10V TC = 25oC


-1 100ms
OPERATION IN THIS DC
-10
AREA MAY BE TRANSCONDUCTANCE
LIMITED BY rDS(ON) MAY LIMIT CURRENT
IN THIS REGION
-0.1 -5
-1 -10 -100 10-6 10-5 10-4 10-3 10-2 10-1 100 101
VDS , DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

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RFD8P06E, RFD8P06ESM, RFP8P06E

Typical Performance Curves Unless Otherwise Specified (Continued)

-30 -20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
IAS , AVALANCHE CURRENT (A)

STARTING TJ = 25oC VGS = -10V


TC = 25oC

ID , DRAIN CURRENT (A)


-15 VGS = -8V
-10 VGS = -20V

-10 VGS = -7V

STARTING TJ = 150oC
VGS = -6V

If R = 0 -5
tAV = (L) (IAS) / (1.3RATED BVDSS - VDD) VGS = -4.5V VGS = -5V
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
-1 0
0.01 0.1 1 10 0 -1.5 -3.0 -4.5 -6.0 -7.5
tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS


IDs(ON) , DRAIN TO SOURCE CURRENT (A)

-20 2.5
VDD = -15V -55oC PULSE DURATION = 80µs

NORMALIZED DRAIN TO SOURCE


PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX 2.0 VGS = -10V, ID = 8A
-15
25oC
ON RESISTANCE

1.5
-10

175oC 1.0

-5
0.5

0 0
0 -2 -4 -6 -8 -10 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON


RESISTANCE vs JUNCTION TEMPERATURE

2.0 2.0
VGS = VDS, ID = 250µA ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE

1.5
THRESHOLD VOLTAGE

1.5
NORMALIZED GATE

1.0 1.0

0.5 0.5

0 0
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ , JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
TEMPERATURE VOLTAGE vs TEMPERATURE

4-120
RFD8P06E, RFD8P06ESM, RFP8P06E

Typical Performance Curves Unless Otherwise Specified (Continued)

1000 -60 -10.0


VGS = 0V, f = 1MHz

VDS , DRAIN TO SOURCE VOLTAGE (V)


VGS = 0V, f = 1MHz

VGS , GATE TO SOURCE VOLTAGE (V)


CISS = CGS + CGD VDD = BVDSS VDD = BVDSS
800 CRSS = CGD
COSS ≈ CDS + CGS -45 -7.5
C, CAPACITANCE (pF)

CISS
RL = 1.2Ω
600
IG(REF) = 1.45mA
-30 -5.0
0.75 BVDSS 0.75 BVDSS
400 0.50 BVDSS 0.50 BVDSS
COSS 0.25 BVDSS 0.25 BVDSS
-15 -2.5
200 VGS = -10V
CRSS

0 0 0.0
IG(REF) IG(REF)
0 -5 -10 -15 -20 -25 t, TIME (µs)
20 80
VDS , DRAIN TO SOURCE VOLTAGE (V) IG(ACT) IG(ACT)

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.


FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT

Test Circuits and Waveforms

VDS
tAV

L 0

VARY tP TO OBTAIN
-
REQUIRED PEAK IAS RG
VDD
+

0V DUT VDD
IAS
tP VDS
IAS tP
-VGS 0.01Ω
BVDSS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
RL 0
10% 10%
VDS -

VGS +
VDS
90% 90%

0V 0
10%
RGS DUT
50% 50%
-VGS PULSE WIDTH
VGS
90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

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RFD8P06E, RFD8P06ESM, RFP8P06E

Test Circuits and Waveforms (Continued)

VDS
Qg(TH)
VDS
0
RL
VGS = -2V

-VGS VGS = -10V


VGS
- Qg(-10)
VDD
+ VGS = -20V
VDD
DUT
Ig(REF) Qg(TOT)

0
Ig(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

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RFD8P06E, RFD8P06ESM, RFP8P06E

PSPICE Electrical Model


.SUBCKT RFP8P06E 2 1 3 REV 6/23/94
LDRAIN
CA 12 8 7.24e-10 5
CB 15 14 8.04e-10 10 2
CIN 6 8 6.00e-10 DPLCAP DRAIN
RSCL1
RSCL2
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD 5
51 ESCL
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD +
17
DPLCAP 10 6 DPLCAPMOD EBREAK
18
- 6 RDRAIN -
ESG 8
EBREAK 5 11 17 18 -79.2 + 16
VTO
EDS 14 8 5 8 1 - DBODY

+
EGS 13 8 6 8 1 EVTO MOS2
GATE RGATE 21
-

+
ESG 5 10 6 8 1 9 18 11
EVTO 20 6 8 18 1 1 20 8 MOS1
LGATE 6

DESD1 RIN CIN DBREAK


IT 8 17 1
91
DESD2 RSOURCE LSOURCE
8 3
LDRAIN 2 5 1e-10
LGATE 1 9 2.92e-9 7 SOURCE
LSOURCE 3 7 2.92e-9

MOS1 16 6 8 8 MOSMOD M=0.99 S1A S2A RBREAK


12 13 14 15
MOS2 16 21 8 8 MOSMOD M=0.01 17 18
8 13
RBREAK 17 18 RBKMOD 1 S1B S2B
13 RVTO
RDRAIN 50 16 RDSMOD 95.2e-3
RGATE 9 20 3.95 CA CB IT 19
RIN 6 8 1e9 + + 14 -
6 5 VBAT
RSCL1 5 51 RSCLMOD 1e6 EGS EDS 8
RSCL2 5 50 1e3 - 8 - +
RSOURCE 8 7 RDSMOD 143.6e-3
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 -0.804

ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/22,9))}

.MODEL DBDMOD D (IS=4.15e-15 RS=5.54e-2 TRS1=-1.32e-3 TRS2=-2.48e-6 CJO=6.06e-10 TT=7.50e-8)


.MODEL DBKMOD D (RS=4.66e-1 TRS1=1.58e-3 TRS2=-7.49e-6)
.MODEL DESD1MOD D (BV=20.2 TBV1=-1.25e-3 TBV2=5.79e-7 RS=36 NBV=50 IBV=7e-6)
.MODEL DESD2MOD D (BV=25.4 TBV1=-8.3e-4 TBV2=8.9e-7 NBV=50 IBV=7e-6)
.MODEL DPLCAPMOD D (CJO=2.49e-10 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.824 KP=5.163 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=9.48e-4 TC2=-1.42e-7)
.MODEL RDSMOD RES (TC1=5.40e-3 TC2=1.25e-5)
.MODEL RSCLMOD RES (TC1=1.75e-3 TC2=3.90e-6)
.MODEL RVTOMOD RES (TC1=-3.55e-3 TC2=-3.43e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=5.10 VOFF=3.10)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.10 VOFF=5.10)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.1 VOFF=-2.9)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.9 VOFF=2.1)

.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options;
written by William J. Hepp and C. Frank Wheatley.

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RFD8P06E, RFD8P06ESM, RFP8P06E

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site [Link]

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