Single Stage Integrated Circuit Amplifier
ECD203 – Electronic Circuits and Devices II
Lecture II
Tutor: Kamal Kumar Chapagai
Lecturer/Head of ECED and PL of ICE
Co- Tutors: Sonam Tshomo
Lab Assistant ECED
Contents
1.IC Design Philosophy
2.Comparison of the MOSFET and the BJT
3.The Basic Gain Cell
4.IC Biasing- Current Source, Current-Mirrors, and Current-
Steering Circuits
5.High-Frequency Response-General Considerations
6.The common-Source and common-emitter Amplifier with
active loads
7.High-Frequency Response of the CS and CE Amplifier
8.The common-Gate and common-base Amplifiers with active
loads
9.The Cascode Amplifier
Assignment – I (5%)
• In this assessment, students will be assessed on their ability to clearly state the
characteristics of different electronic devices and report on the difference in the
characteristics.
• This assignment will be completed individually.
• 1 Introduction (Stating the general description that highlights the purpose of
this assignment)
• 2 Content (Theory, principles, diagram, and analysis)
• 1 Layout (Font, cover page, justification, table of content, reference)
• 1 Originality (Plagiarism will be checked on Turnitin)
• Hand Written
• Maximum of 5 Pages (back and front)
• Submission Date:
• 6th March 2025 10:00AM to be collected by CRs and submitted
in my office
IC Biasing- Current Source
• Biasing in integrated-circuit design is based on the use of constant-current
sources
• On an IC chip with a number of amplifier stages, a constant dc current
(called a reference current) is generated at one location and is then
replicated at various other locations for biasing the various amplifier stages
through a process known as current steering.
• Advantage:
• The effort expended on generating a predictable and stable reference
current, usually utilizing a precision resistor external to the chip or a
special circuit on the chip, need not be repeated for every amplifier stage
• The bias currents of the various stages track each other in case of
changes in power-supply voltage or in temperature
IC Biasing- Current Source
• The Basic MOSFET Current Source (1)
• The drain of Q1 is shorted to its gate, thereby forcing
it to operate in the saturation mode with
-----(1)
The drain current of Q1 is supplied by VDD through
resistor R, which in most cases would be outside
the IC chip
-----(2)
where the current through R is considered the reference current of the current source and is
denoted IREF. Equations above can be used together to determine the value required for R to
generate a given IREF.
IC Biasing- Current Source
• The Basic MOSFET Current Source (2)
• Now consider transistor Q2: It has the same VGS as
Q1 ; thus, if we assume that it is operating in
saturation, its drain current, which is the output
current I0 of the current source, will be
-----(3)
Equations (1) and (3) enable us to relate the output
current I0 to the reference current IREF as follows:
-----(4) Current Mirror: I0 = IREF
For same aspect ratio
The special connection of Q1 and Q2 provides an output current I0 that is related
to the reference current IREF by the aspect ratios of the transistors.
IC Biasing- Current Mirror
• The MOS Current Mirror (1)
• Input reference current shown as being supplied by a
current source for both simplicity and generality.
• The current gain or current transfer ratio of the current
mirror is given by:
-----(4)
• Lets consider the effect of V0 on I0
• We assumed Q2 to be operating in saturation for it to work
as current source (constant current)
• Condition for Saturation: Or
IC Biasing- Current Mirror
• The MOS Current Mirror (2)
• For the current sources and the current mirror
above in VCSmin is equal to Vov of Q1 and Q2.
• Channel-length modulation can have a
significant effect on the operation of the
current mirror
• The output current will be at its nominal
value of
i.e Vo = VDS = VGS
• As Vo deviates from this value, lo will
deviate from the nominal value by ∆I0,
where r02is the output resistance of Q2,
IC Biasing- Current Mirror
• The MOS Current Mirror (3)
where VA2 is the Early voltage of Q2
• Equations above can be used to find I0 at an
arbitrary V0 (that is greater than Vov) as
Example: Current Source
• Given VDD = 3 V and using IREF = 100µA, design a
constant current source circuit to obtain an output
current whose nominal value is 100µA. Find R if Q1
and Q2 are matched and have channel lengths of 1µm,
channel widths of 10µm, Vt = 0.7 V, and k'n =200
µA/V2.
• What is the lowest possible value of V0? Assuming that
for this process technology, the Early voltage VA = 20
V/µm, find the output resistance of the current source.
Also, find the change in output current resulting from a
+1V change in V0.
Solution
Exercise: Current Source
• In the current source example, it is required to
reduce the change in output current, ∆I0,
corresponding to a change in output voltage,
∆V0, of 1V to 1% of I0. What should the
dimensions of Q1 and Q2 be changed to?
• Assume that Q1 and Q2 are to remain matched.
Solution
• I0 corresponding to a 1V change in • To keep V0V of the matched
output voltage, V0,to 1% of I0 transistors the same, W/L of the
• That is, I0 = V0/ro2. = 0.01I0 transistors should remain same
1V/r02 = 0.01 x 100µA • Therefore:
r02 = 1V/1µA = 1MΩ • W/5µm = 10µm / 1µm
• W = 50µm
r02 = VA x L / I0 • So the dimension of the matched
transistors Q1 and Q2 should
1MΩ = 20 x L / 100µA change to
L = 100V / 20V/µm = 5µm • W = 50µm and L = 5µm
Thank You
Questions ?
