LTC3859A

Low IQ, Triple Output,

Buck/Buck/Boost Synchronous Controller
with Improved Burst Mode Operation
Features Description
n Dual Buck Plus Single Boost Synchronous Controllers The LTC®3859A is a high performance triple output (buck/
n Outputs Remain in Regulation Through Cold Crank buck/boost) synchronous DC/DC switching regulator
Down to 2.5V controller that drives all N-channel power MOSFET stages.
n Low Operating IQ: 55μA (One Channel On) Constant frequency current mode architecture allows
n Wide Bias Input Voltage Range: 4.5V to 38V a phase-lockable switching frequency of up to 850kHz.
n Buck Output Voltage Range: 0.8V ≤ VOUT ≤ 24V The LTC3859A operates from a wide 4.5V to 38V input
n Boost Output Voltage Up to 60V supply range. When biased from the output of the boost
n RSENSE or DCR Current Sensing converter or another auxiliary supply, the LTC3859A can
operate from an input supply as low as 2.5V after start-up.
n 100% Duty Cycle for Boost Synchronous MOSFET
Even in Burst Mode® Operation The 55μA no-load quiescent current extends operating
n Phase-Lockable Frequency (75kHz to 850kHz) runtime in battery powered systems. OPTI-LOOP com-
n Programmable Fixed Frequency (50kHz to 900kHz) pensation allows the transient response to be optimized
n Selectable Continuous, Pulse-Skipping or Low Ripple over a wide range of output capacitance and ESR values.
Burst Mode Operation at Light Loads The LTC3859A features a precision 0.8V reference for the
n Very Low Buck Dropout Operation: 99% Duty Cycle bucks, 1.2V reference for the boost and a power good
n Adjustable Output Voltage Soft-Start or Tracking output indicator. The PLLIN/MODE pin selects among
Burst Mode operation, pulse-skipping mode, or continu-
n Low Shutdown IQ: 14μA
ous inductor current mode at light loads.
n Small 38-Pin 5mm × 7mm QFN and TSSOP Packages
Compared to the LTC3859, the LTC3859A's boost controller
Applications has improved performance in Burst Mode operation when
n Automotive Always-On and Start-Stop Systems the input voltage is higher than the regulated output voltage.
n Battery Operated Digital Devices L, LT, LTC, LTM, Burst Mode, OPTI-LOOP and µModule are registered trademarks and
n Distributed DC Power Systems No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5481178, 5705919,
n Multioutput Buck-Boost Applications 5929620, 6144194, 6177787, 6580258.

Typical Application
VOUT3
REGULATED AT 10V WHEN VIN < 10V 220µF 1µF
FOLLOWS VIN WHEN VIN > 10V
499k
VFB3 VBIAS Efficiency vs Input Voltage
68.1k TG1 100
4.9µH 6mΩ VOUT1 95 VOUT2 = 8.5V
1.2µH TG3 SW1 5V
VIN 2mΩ 90 VOUT1 = 5V
5A
2.5V TO 38V SW3 BG1
(START-UP ABOVE 5V) LTC3859A 85
220µF
EFFICIENCY (%)

BG3 80
SENSE1+
75
SENSE3– SENSE1–
SENSE3+ VFB1 70
INTVCC 357k 65
68.1k 220µF
4.7µF RUN1, 2, 3
60
BOOST1, 2, 3 EXTVCC VOUT1
0.1µF 55 FIGURE 12 CIRCUIT
SW1, 2, 3 ILOAD = 2A
TG2 6.5µH 8mΩ VOUT2 50
ITH1, 2, 3 SW2 8.5V 0 5 10 15 20 25 30 35 40
BG2 3A INPUT VOLTAGE (V)
3859A TA01b

SENSE2+
TRACK/SS1, 2 SENSE2–
0.1µF SS3 VFB2
PGND SGND 68.1k 649k 68µF
3859 TA01a

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LTC3859A
Absolute Maximum Ratings (Notes 1, 3)

Bias Input Supply Voltage (VBIAS)............... –0.3V to 40V SENSE1+, SENSE2 +, SENSE1–
Buck Top Side Driver Voltages SENSE2 – Voltages...................................... –0.3V to 28V
(BOOST1, BOOST2) .............................. –0.3V to 46V SENSE3 +, SENSE3– Voltages...................... –0.3V to 40V
Boost Top Side Driver Voltages FREQ Voltages....................................... –0.3V to INTVCC
(BOOST3) ............................................. –0.3V to 76V EXTVCC........................................................ –0.3V to 14V
Buck Switch Voltage (SW1, SW2) ................. –5V to 40V ITH1, ITH2, ITH3, VFB1, VFB2, VFB3 Voltages..... –0.3V to 6V
Boost Switch Voltage (SW3) ......................... –5V to 70V PLLIN/MODE, PGOOD1, OV3 Voltages ........ –0.3V to 6V
INTVCC, (BOOST1–SW1), TRACK/SS1, TRACK/SS2, SS3 Voltages ...... –0.3V to 6V
(BOOST2–SW2), (BOOST3–SW3),........... –0.3V to 6V Operating Junction Temperature Range (Note 2)
RUN1, RUN2, RUN3 ..................................... –0.3V to 8V LTC3859AE, LTC3859AI...................... –40°C to 125°C
Maximum Current Sourced Into Pin LTC3859AH......................................... –40°C to 150°C
from Source >8V...............................................100µA LTC3859AMP...................................... –55°C to 150°C
Storage Temperature Range...............–65°C to 150°C

Pin Configuration
TOP VIEW
TOP VIEW
ITH1 1 38 TRACK/SS1

TRACK/SS1
SENSE1–
SENSE1+

PGOOD1
VFB1 2 37 PGOOD1

VFB1
ITH1

TG1
SENSE1+ 3 36 TG1
SENSE1– 4 35 SW1 38 37 36 35 34 33 32

FREQ 5 34 BOOST1 FREQ 1 31 SW1

PLLIN/MODE 6 33 BG1 PLLIN/MODE 2 30 BOOST1

7 32 SW3 SS3 3 29 BG1

SS3
SENSE3+ 4 28 SW3
SENSE3+ 8 31 TG3
SENSE3– 5 27 TG3
SENSE3– 9 30 BOOST3
39 VFB3 6 39 26 BOOST3
VFB3 10 29 BG3
PGND ITH3 7 PGND 25 BG3
ITH3 11 28 VBIAS
SGND 8 24 VBIAS
SGND 12 27 EXTVCC
RUN1 9 23 EXTVCC
RUN1 13 26 INTVCC
RUN2 10 22 INTVCC
RUN2 14 25 BG2 RUN3 11 21 BG2
RUN3 15 24 BOOST2 SENSE2– 12 20 BOOST2
SENSE2– 16 23 SW2 13 14 15 16 17 18 19
SENSE2+ 17 22 TG2
SENSE2+
VFB2
ITH2
TRACK/SS2
OV3
TG2
SW2

VFB2 18 21 OV3
ITH2 19 20 TRACK/SS2
UHF PACKAGE
FE PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN
38-LEAD PLASTIC TSSOP
TJMAX = 150°C, qJA = 34.7°C/W
TJMAX = 150°C, qJA = 25°C/W EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

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 LTC3859A
Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3859AEFE#PBF LTC3859AEFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3859AIFE#PBF LTC3859AIFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3859AHFE#PBF LTC3859AHFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –40°C to 150°C
LTC3859AMPFE#PBF LTC3859AMPFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –55°C to 150°C
LTC3859AEUHF#PBF LTC3859AEUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3859AIUHF#PBF LTC3859AIUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3859AHUHF#PBF LTC3859AHUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 150°C
LTC3859AMPUHF#PBF LTC3859AMPUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VBIAS Bias Input Supply Operating Voltage 4.5 38 V
Range
VFB1,2 Buck Regulated Feedback Voltage (Note 4); ITH1,2 Voltage = 1.2V
–40°C to 85°C, All Grades 0.792 0.800 0.808 V
LTC3859AE, LTC3859AI l 0.788 0.800 0.812 V
LTC3859AH, LTC3859AMP l 0.786 0.800 0.812 V
VFB3 Boost Regulated Feedback Voltage (Note 4); ITH3 Voltage = 1.2V
–40°C to 85°C, All Grades 1.188 1.200 1.212 V
LTC3859AE, LTC3859AI l 1.182 1.200 1.218 V
LTC3859AH, LTC3859AMP l 1.179 1.200 1.218 V
IFB1,2,3 Feedback Current (Note 4) –10 ±50 nA
VREFLNREG Reference Voltage Line Regulation (Note 4); VIN = 4V to 38V 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop; l 0.01 0.1 %
DITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; l –0.01 –0.1 %
DITH Voltage = 1.2V to 2V
gm1,2,3 Transconductance Amplifier gm (Note 4); ITH1,2,3 = 1.2V; 2 mmho
Sink/Source 5µA

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LTC3859A
Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQ Input DC Supply Current (Note 5)
Pulse-Skipping or RUN1 = 5V and RUN2,3 = 0V or 1.5 mA
Forced Continuous Mode RUN2 = 5V and RUN1,3 = 0V or
(One Channel On) RUN3 = 5V and RUN1,2 = 0V
VFB1, 2 ON = 0.83V (No Load)
VFB3 = 1.25V
Pulse-Skipping or RUN1,2,3 = 5V, 3 mA
Forced Continuous Mode VFB1,2 = 0.83V (No Load)
(All Channels On) VFB3 = 1.25V
Sleep Mode RUN1 = 5V and RUN2,3 = 0V or 55 80 µA
(One Channel On, Buck) RUN2 = 5V and RUN1,3 = 0V
VFB,ON = 0.83V (No Load)
Sleep Mode RUN3 = 5V and RUN1,2 = 0V 55 80 µA
(One Channel On, Boost) VFB3 = 1.25V
Sleep Mode RUN1 = 5V and RUN2 = 0V or 65 100 µA
(Buck and Boost Channel On) RUN2 = 5V and RUN1 = 0V
RUN3 = 5V
VFB1,2 = 0.83V (No Load)
VFB3 = 1.25V
Sleep Mode RUN1,2,3 = 5V, 80 120 µA
(All Three Channels On) VFB1,2 = 0.83V (No Load)
VFB3 = 1.25V
Shutdown RUN1,2,3 = 0V 14 30 µA
UVLO Undervoltage Lockout INTVCC Ramping Up l 4.15 4.5 V
INTVCC Ramping Down l 3.5 3.8 4.0 V
VOVL1,2 Buck Feedback Overvoltage Protection Measured at VFB1,2 Relative to 7 10 13 %
Regulated VFB1,2
ISENSE1,2+ SENSE+ Pin Current Bucks (Channels 1 and 2) ±1 µA
ISENSE3+ SENSE+ Pin Current Boost (Channel 3) 170 µA
ISENSE1,2– SENSE– Pin Current Bucks (Channels 1 and 2)
VOUT1,2 < VINTVCC – 0.5V ±2 µA
VOUT1,2 > VINTVCC + 0.5V 700 µA
ISENSE3 – SENSE– Pin Current Boost (Channel 3) ±1 µA
VSENSE3+, VSENSE3 – = 12V
DFMAX,TG Maximum Duty Factor for TG Bucks (Channels 1,2) in Dropout, FREQ = 0V 98 99 %
Boost (Channel 3) in Overvoltage 100 %
DFMAX,BG Maximum Duty Factor for BG Bucks (Channels 1,2) in Overvoltage 100 %
Boost (Channel 3) 96 %
ITRACK/SS1,2 Soft-Start Charge Current VTRACK/SS1,2 = 0V 0.7 1.0 1.4 µA
ISS3 Soft-Start Charge Current VSS3 = 0V 0.7 1.0 1.4 µA
VRUN1 ON RUN1 Pin Threshold VRUN1 Rising l 1.19 1.25 1.31 V
VRUN2,3 ON RUN2,3 Pin Threshold VRUN2,3 Rising l 1.23 1.28 1.33 V
VRUN1,2,3 Hyst RUN Pin Hysteresis 80 mV
VSENSE1,2,3(MAX) Maximum Current Sense Threshold VFB1,2 = 0.7V, VSENSE1,2– = 3.3V l 43 50 57 mV
VFB1,2,3 = 1.1V, VSENSE3 + = 12V
VSENSE3(CM) SENSE3 Pins Common Mode Range 2.5 38 V
(BOOST Converter Input Supply Voltage)

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 LTC3859A
Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Driver
TG1,2 Pull-Up On-Resistance 2.5 Ω
Pull-Down On-Resistance 1.5 Ω
BG1,2 Pull-Up On-Resistance 2.4 Ω
Pull-Down On-Resistance 1.1 Ω
TG3 Pull-Up On-Resistance 1.2 Ω
Pull-Down On-Resistance 1.0 Ω
BG3 Pull-Up On-Resistance 1.2 Ω
Pull-Down On-Resistance 1.0 Ω
TG Transition Time: (Note 6)
TG1,2,3 tr Rise Time CLOAD = 3300pF 25 ns
TG1,2,3 tf Fall Time CLOAD = 3300pF 16 ns
BG Transition Time: (Note 6)
BG1,2,3 tr Rise Time CLOAD = 3300pF 28 ns
BG1,2,3 tf Fall Time CLOAD = 3300pF 13 ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver Bucks (Channels 1, 2) 30 ns
Synchronous Switch-On Delay Time Boost (Channel 3) 70 ns
BG/TG t1D Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver Bucks (Channels 1, 2) 30 ns
Top Switch-On Delay Time Boost (Channel 3) 70 ns
tON(MIN)1,2 Buck Minimum On-Time (Note 7) 95 ns
tON(MIN)3 Boost Minimum On-Time (Note 7) 120 ns
INTVCC Linear Regulator
VINTVCCVBIAS Internal VCC Voltage 6V < VBIAS < 38V, VEXTVCC = 0V, IINTVCC = 0mA 5.0 5.4 5.6 V
VLDOVBIAS INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 0V 0.7 2 %
VINTVCCEXT Internal VCC Voltage 6V < VEXTVCC < 13V, IINTVCC = 0mA 5.0 5.4 5.6 V
VLDOEXT INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 8.5V 0.7 2 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.5 4.7 V
VLDOHYS EXTVCC Hysteresis 200 mV
Oscillator and Phase-Locked Loop
f25k Programmable Frequency RFREQ = 25k; PLLIN/MODE = DC Voltage 115 kHz
f65k Programmable Frequency RFREQ = 65k; PLLIN/MODE = DC Voltage 375 440 505 kHz
f105k Programmable Frequency RFREQ = 105k; PLLIN/MODE = DC Voltage 835 kHz
fLOW Low Fixed Frequency VFREQ = 0V PLLIN/MODE = DC Voltage 320 350 380 kHz
fHIGH High Fixed Frequency VFREQ = INTVCC; PLLIN/MODE = DC Voltage 485 535 585 kHz
fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l 75 850 kHz
PGOOD1 Output
VPGL1 PGOOD1 Voltage Low IPGOOD1 = 2mA 0.2 0.4 V
IPGOOD1 PGOOD1 Leakage Current VPGOOD1 = 5V ±1 µA
VPG1 PGOOD1 Trip Level VFB1 with Respect to Set Regulated Voltage
VFB1 Ramping Negative –13 –10 –7 %
Hysteresis 2.5 %
VFB1 Ramping Positive 7 10 13 %
Hysteresis 2.5 %
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LTC3859A
Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise
noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TPG1 Delay For Reporting a Fault 20 µs
OV3 Boost Overvoltage Indicator Output
VOV3L OV3 Voltage Low IOV3 = 2mA 0.2 0.4 V
IOV3 OV3 Leakage Current VOV3 = 5V ±1 µA
VOV OV3 Trip Level VFB With Respect to Set Regulated Voltage 6 10 13 %
Hysteresis 1.5 %
BOOST3 Charge Pump
IBST3 BOOST3 Charge Pump Available Output VBOOST3 = 16V; VSW3 = 12V; 65 µA
Current Forced Continuous Mode

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: This IC includes overtermperature protection that is intended to
may cause permanent damage to the device. Exposure to any Absolute protect the device during momentary overload conditions. The maximum
Maximum Rating condition for extended periods may affect device rated junction temperature will be exceeded when this protection is active.
reliability and lifetime. Continuous operation above the specified absolute maximum operating
Note 2: The LTC3859A is tested under pulsed load conditions such that junction temperature may impair device reliability or permanently damage
TJ ≈ TA. The LTC3859AE is guaranteed to meet performance specifications the device.
from 0°C to 85°C. Specifications over the –40°C to 125°C operating Note 4: The LTC3859A is tested in a feedback loop that servos VITH1,2,3
junction temperature range are assured by design, characterization and to a specified voltage and measures the resultant VFB. The specification at
correlation with statistical process controls. The LTC3859AI is guaranteed 85°C is not tested in production and is assured by design, characterization
over the –40°C to 125°C operating junction temperature range, the and correlation to production testing at other temperatures (125°C for the
LTC3859AH is guaranteed over the –40°C to 150°C operating junction LTC3859AE/LTC3859AI, 150°C for the LTC3859AH/LTC3859AMP). For the
temperature range and the LTC3859AMP is tested and guaranteed over LTC3859AMP, the specification at –40°C is not tested in production and is
the –55°C to 150°C operating junction temperature range. High junction assured by design, characterization and correlation to production testing
temperatures degrade operating lifetimes; operating lifetime is derated for at –55°C.
junction temperatures greater than 125°C. Note that the maximum ambient Note 5: Dynamic supply current is higher due to the gate charge being
temperature consistent with these specifications is determined by specific delivered at the switching frequency. See the Applications Information
operating conditions in conjunction with board layout, the rated package section.
thermal impedance and other environmental factors. TJ is calculated from Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
the ambient temperature TA and power dissipation PD according to the times are measured using 50% levels.
following formula: TJ = TA + (PD • θJA), where θJA = 34°C/W for the QFN
Note 7: The minimum on-time condition is specified for an inductor
package and θJA = 25°C/W for the TSSOP package.
peak-to-peak ripple current ≥ 40% of IMAX (See the Minimum On-Time
Considerations in the Applications Information section).

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Typical Performance Characteristics
Efficiency and Power Loss Efficiency
vs Output Current (Buck) vs Output Current (Buck) Efficiency vs Input Voltage (Buck)
100 10000 100 100
FIGURE 12 CIRCUIT
VIN = 10V
90 90 99 VOUT = 5V
ILOAD = 4A
80 1000 80 VIN = 20V
98
70 70

POWER LOSS (mW)

EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
60 100 60 97

50 50 96
40 FCM EFFICIENCY 10 40
PULSE-SKIPPING 95
30 EFFICIENCY 30
BURST LOSS 94
20 BURST EFFICIENCY 1 20
FCM LOSS 93
10 PULSE-SKIPPING 10 FIGURE 12 CIRCUIT
LOSS VOUT = 5V
0 0.1 0 92
0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 35 40
OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V)
3859A G01 3859A G02 3859A G03
FIGURE 12 CIRCUIT
VIN = 10V, VOUT = 5V

Load Step (Buck) Load Step (Buck) Load Step (Buck)

Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode

VOUT VOUT VOUT

100mV/DIV 100mV/DIV 100mV/DIV
AC-COUPLED AC-COUPLED AC-COUPLED

IL IL IL
2A//DIV 2A//DIV 2A//DIV

50µs/DIV 3859A G04 50µs/DIV 3859A G05

50µs/DIV 3859A G06

VIN = 12V VIN = 12V VIN = 12V

VOUT = 5V VOUT = 5V VOUT = 5V
FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT

Inductor Current at Light Load Buck Regulated Feedback Voltage

(Buck) Soft Start-Up vs Temperature
808

FORCED
REGULATED FEEDBACK VOLTAGE (mV)

806
CONTINUOUS
MODE VOUT2
804
2V/DIV
Burst Mode 802
OPERATION VOUT1
1A/DIV 2V/DIV 800

798
PULSE-
SKIPPING
MODE 796

2µs/DIV 3859A G07

20ms/DIV 3859A G08
794
VIN = 10V
FIGURE 12 CIRCUIT
VOUT = 5V 792
ILOAD = 1mA –75 –50 –25 0 25 50 75 100 125 150
FIGURE 12 CIRCUIT
TEMPERATURE (°C)
3859A G09

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LTC3859A
Typical Performance Characteristics
Efficiency and Power Loss Efficiency
vs Output Current (Boost) vs Output Current (Boost) Efficiency vs Input Voltage (Boost)
100 10000 100 100
VIN = 8V FIGURE 12 CIRCUIT
90 90 VIN = 5V 99 VBIAS = VIN
V = 10V
80 1000 80 98 OUT
ILOAD = 2A
70 70 97

POWER LOSS (mW)

EFFICIENCY (%)
EFFICIENCY (%)

EFFICIENCY (%)
60 100 60 96
50 50 95
FCM EFFICIENCY
40 PULSE-SKIPPING 10 40 94
EFFICIENCY
30 BURST LOSS 30 93
BURST
20 EFFICIENCY 1 20 92
FCM LOSS FIGURE 12 CIRCUIT
10 PULSE-SKIPPING 10 VBIAS = VIN 91
LOSS VOUT = 10V
0 0.1 0 90
0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 2 3 4 5 6 7 8 9 10
OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V)
3859A G10 3859A G11 3859A G12
FIGURE 12 CIRCUIT
VIN = 5V, VOUT = 10V, VBIAS = VIN

Load Step (Boost) Load Step (Boost) Load Step (Boost)

Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode

VOUT VOUT VOUT

100mV/ 100mV/DIV 100mV/DIV
DIV AC-COUPLED AC-COUPLED
AC-
COUPLED

IL IL IL
5A/DIV 5A/DIV 5A/DIV

200µs/DIV 3859A G13 200µs/DIV 3859A G14

200µs/DIV 3859A G15

VOUT = 10V VOUT = 10V VOUT = 10V

VIN = 5V VIN = 5V VIN = 5V
FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT

Inductor Current at Light Load Boost Regulated Feedback

(Boost) Soft Start-Up (Boost) Voltage vs Temperature
1.212

FORCED 1.209
REGULATED FEEDBACK VOLTAGE (V)

CONTINUOUS
MODE 1.206

1.203
Burst Mode VOUT3
OPERATION 2V/DIV 1.200
5A/DIV

PULSE- 1.197
SKIPPING GND
MODE 1.194

2µs/DIV 3859A G16 20ms/DIV 3859A G17

1.191
VOUT = 10V VIN = 5V
VIN = 7V FIGURE 12 CIRCUIT
1.188
ILOAD = 1mA –75 –50 –25 0 25 50 75 100 120 150
FIGURE 12 CIRCUIT TEMPERATURE (°C)
3859A G18

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 LTC3859A
Typical Performance Characteristics
INTVCC and EXTVCC EXTVCC Switchover and INTVCC
INTVCC Line Regulation vs Load Current Voltages vs Temperature
5.5 5.6 6.0
EXTVCC = 0V 5.8
5.4

EXTVCC AND INTVCC VOLTAGE (V)

5.4 EXTVCC = 8.5V 5.6
5.2 INTVCC
5.4
INTVCC VOLTAGE (V)

INTVCC VOLTAGE (V)

5.3 5.0 5.2
4.8 5.0
EXTVCC = 5V EXTVCC RISING
5.2 4.8
4.6
4.6
4.4
5.1 4.4 EXTVCC FALLING
4.2 4.2
VBIAS = 12V
5.0 4.0 4.0
0 5 10 15 20 25 30 35 40 0 20 40 60 80 100 –75 –50 –25 0 25 50 75 100 125 150
INPUT VOLTAGE (V) LOAD CURRENT (mA) TEMPERATURE (°C)
3859A G19 3859A G20 3859A G21

SENSE Pins Total Input Current Buck SENSE– Pin Input Bias Boost SENSE Pin Total Input
vs VSENSE Voltage Current vs Temperature Current vs Temperature
800 900 200
VIN = 12V
800 180
700 SENSE1, 2 PINS
VOUT > INTVCC + 0.5V SENSE3+ PIN
160
700
600

SENSE CURRENT (µA)

140
SENSE CURRENT (µA)

SENSE CURRENT (µA)

600
500 120
500
400 100
400
80
300
300 60
200 SENSE3 PIN
200 40
100 100 20
VOUT < INTVCC – 0.5V SENSE3– PIN
0 0 0
0 5 10 15 20 25 30 35 40 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
VSENSE COMMON MODE VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)
3859A G22 3859A G23 3859A G24

Maximum Current Sense Maximum Current Sense TRACK/SS Pull-Up Current

Threshold vs Duty Cycle Threshold vs ITH Voltage vs Temperature
80 60 1.20
MAXIMUM CURRENT SENSE VOLTAGE (mV)

MAXIMUM CURRENT SENSE VOLTAGE (mV)

70 50 1.15

60 40
1.10
TRACK/SS CURRENT (µA)

30
50 BOOST 1.05
BUCK 20
40 1.00
10
30 0.95
0
20 0.90
–10
PULSE-SKIPPING
10 –20 FORCED CONTINUOUS 0.85
Burst Mode OPERATION
0 –30 0.80
0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 –75 –50 –25 0 25 50 75 100 125 150
DUTY CYCLE (%) ITH (V) TEMPERATURE (°C)
3859A G25 3859A G26 3859A G27

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9
LTC3859A
Typical Performance Characteristics
Shutdown Current
Shutdown Current vs Temperature vs Input Voltage Quiescent Current vs Temperature
22 25 100
VBIAS = 12V VBIAS = 12V
20 90
20
SHUTDOWN CURRENT (µA)

SHUTDOWN CURRENT (µA)

QUIESCENT CURRENT (µA)

ALL CHANNELS ON
18
80
15
16
70
14
10
60
12
5 ONE CHANNEL ON
10 50

8 0 40
–75 –50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VBIAS INPUT VOLTAGE (V) TEMPERATURE (°C)
3859A G28 3859A G29 3859A G30

Oscillator Frequency Undervoltage Lockout Threshold

Buck Foldback Current Limit vs Temperature vs Temperature
70 600 4.4
MAXIMUM CURRENT SENSE VOLTAGE (mV)

65
4.3
60 FREQ = INTVCC
550 RISING
55 4.2
50 4.1

INTVCC VOLTAGE (V)

500
FREQUENCY (kHz)

45
4.0
40
35 450 3.9
FALLING
30
3.8
25 400
20 3.7
15 FREQ = GND
3.6
10 350
3.5
5
0 300 3.4
0 100 200 300 400 500 600 700 800 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
FEEDBACK VOLTAGE (mV) TEMPERATURE (°C) TEMPERATURE (°C)
3859A G31 3859A G32 3859A G33

Shutdown (RUN) Threshold Charge Pump Charging Current Charge Pump Charging Current
vs Temperature vs Operating Frequency vs Switch Voltage
1.40 100 100
VBOOST3 = 16V VBOOST3 – VSW3 = 4V
CHARGE PUMP CHARGING CURRENT (µA)
CHARGE PUMP CHARGING CURRENT (µA)

90 VSW3 = 12V 90
1.35
80 –55°C 80 FREQ = 0V
1.30 RUN2,3 RISING
RUN PIN VOLTAGE (V)

70 25°C 70
RUN1 RISING FREQ = INTVCC
1.25 60
60
RUN2,3 FALLING 50
1.20 50
40 40
1.15 150°C
RUN1 FALLING 30 30
1.10
20 20
1.05 10
10
1.00 0 0
–75 –50 –25 0 25 50 75 100 125 150 100 200 300 400 500 600 700 800 5 10 15 20 25 30 35 40
TEMPERATURE (°C) OPERATING FREQUENCY (kHz) SWITCH VOLTAGE (V)
3859A G34 3859A G35 3859A G36

3859af

10
 LTC3859A
Pin Functions (QFN/TSSOP)

FREQ (Pin 1/Pin 5): The Frequency Control Pin for the INTVCC (Pin 22/Pin 26): Output of the Internal Linear Low
Internal VCO. Connecting the pin to GND forces the VCO Dropout Regulator. The driver and control circuits are pow-
to a fixed low frequency of 350kHz. Connecting the pin ered from this voltage source. Must be decoupled to PGND
to INTVCC forces the VCO to a fixed high frequency of with a minimum of 4.7µF ceramic or tantalum capacitor.
535kHz. Other frequencies between 50kHz and 900kHz
EXTVCC (Pin 23/Pin 27): External Power Input to an
can be programmed using a resistor between FREQ and Internal LDO Connected to INTVCC. This LDO supplies
GND. The resistor and an internal 20µA source current INTVCC power, bypassing the internal LDO powered from
create a voltage used by the internal oscillator to set the VBIAS whenever EXTVCC is higher than 4.7V. See EXTVCC
frequency. Connection in the Applications Information section. Do
PLLIN/MODE (Pin 2/Pin 6): External Synchronization not float or exceed 14V on this pin.
Input to Phase Detector and Forced Continuous Mode VBIAS (Pin 24/Pin 28): Main Bias Input Supply Pin. A
Input. When an external clock is applied to this pin, the bypass capacitor should be tied between this pin and the
phase-locked loop will force the rising TG1 signal to be SGND pin.
synchronized with the rising edge of the external clock,
and the regulators operate in forced continuous mode. BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High
When not synchronizing to an external clock, this input, Current Gate Drives for Bottom (Synchronous) N-Channel
which acts on all three controllers, determines how the MOSFETs. Voltage swing at these pins is from ground to
LTC3859AA operates at light loads. Pulling this pin to INTVCC.
ground selects Burst Mode operation. An internal 100k BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,
resistor to ground also invokes Burst Mode operation 24, 30): Bootstrapped Supplies to the Top Side Floating
when the pin is floated. Tying this pin to INTVCC forces Drivers. Capacitors are connected between the BOOST and
continuous inductor current operation. Tying this pin to SW pins and Schottky diodes are tied between the BOOST
a voltage greater than 1.2V and less than INTVCC – 1.3V and INTVCC pins. Voltage swing at the BOOST pins is from
selects pulse-skipping operation. This can be done by INTVCC to (VIN + INTVCC).
connecting a 100k resistor from this pin to INTVCC.
SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32):
SGND (Pin 8/Pin 12): Small Signal Ground common to Switch Node Connections to Inductors.
all three controllers, must be routed separately from high
current grounds to the common (–) terminals of the CIN TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High
capacitors. Current Gate Drives for Top N-Channel MOSFETs. These
are the outputs of floating drivers with a voltage swing
RUN1, RUN2, RUN3 (Pins 9, 10, 11/Pins 13, 14, 15): equal to INTVCC superimposed on the switch node volt-
Digital Run Control Inputs for Each Controller. Forcing age SW.
RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts
down that controller. Forcing all of these pins below 0.7V PGOOD1 (Pin 33/Pin 37): Open-Drain Logic Output.
shuts down the entire LTC3859A, reducing quiescent cur- PGOOD1 is pulled to ground when the voltage on the VFB1
rent to approximately 14µA. pin is not within ±10% of its set point.

OV3 (Pin 17/Pin 21): Overvoltage Open-Drain Logic

Output for the Boost Regulator. OV3 is pulled to ground
when the voltage on the VFB3 pin is under 110% of its set
point, and becomes high impedance when VFB3 goes over
110% of its set point.

3859af

11
LTC3859A
pin functions (QFN/TSSOP)

TRACK/SS1, TRACK/SS2, SS3 (Pins 34, 16, 3/Pins 38, VFB1, VFB2, VFB3 (Pins 36, 14, 6/Pins 2, 18, 10): Receives
20, 7): External Tracking and Soft-Start Input. For the buck the remotely sensed feedback voltage for each controller
channels, the LTC3859A regulates the VFB1,2 voltage to the from an external resistive divider across the output.
smaller of 0.8V, or the voltage on the TRACK/SS1,2 pin.
SENSE1+, SENSE2+, SENSE3+ (Pins 37, 13, 4/Pins 3, 17, 8):
For the boost channel, the LTC3859A regulates the VFB3 The (+) Input to the Differential Current Comparators.
voltage to the smaller of 1.2V, or the voltage on the SS3
The ITH pin voltage and controlled offsets between the
pin. An internal 1µA pull-up current source is connected SENSE– and SENSE+ pins in conjunction with RSENSE set the
to this pin. A capacitor to ground at this pin sets the ramp current trip threshold. For the boost channel, the SENSE3+
time to final regulated output voltage. Alternatively, a re- pin supplies current to the current comparator.
sistor divider on another voltage supply connected to the
TRACK/SS pins of the buck channels allow the LTC3859A SENSE1–, SENSE2–, SENSE3– (Pins 38, 12, 5/Pins 4,
buck outputs to track the other supply during start-up. 16, 9): The (–) Input to the Differential Current Compara-
tors. When SENSE1,2– for the buck channels is greater
ITH1, ITH2, ITH3 (Pins 35, 15, 7/Pins 1, 19, 11): Error than INTVCC, then SENSE1,2– pin supplies current to the
Amplifier Outputs and Switching Regulator Compensation current comparator.
Points. Each associated channel’s current comparator trip
point increases with this control voltage. PGND (Exposed Pad Pin 39): Driver Power Ground. Con-
nects to the sources of bottom N-channel MOSFETs and the
(–) terminal(s) of CIN. The exposed pad must be soldered
to the PCB for rated electrical and thermal performance.

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 BUCK CHANNELS 1 AND 2 INTVCC VIN1,2
PGOOD1
DB
BOOST
+ 0.88V
DROPOUT
– DET BOT
TG CB
VFB1 TOP
+ CIN
TOPON
S Q SWITCHING D
– 0.72V LOGIC
R Q SW
SHDN
20µA COUT
FREQ INTVCC
CLK2 VOUT1,2
VCO
Functional Diagram

BG
CLK1 BOT

+ SLEEP
PGND
–
PFD
CLP ICMP IR
+ +
L RSENSE
– –+ –
–+
SENSE+
3mV
SYNC 2.8V
DET 0.65V SENSE–

100k VFB
SLOPE COMP RB
+
VBIAS 0.80V
EA – TRACK/SS
– RA
EXTVCC
OV +
– 0.88V ITH CC
5.4V 5.4V 6µA CH1
LDO LDO 0.5µA CH2
EN EN SHDN 1µA TRACK/SS CC2 RC
RST FOLDBACK
+ 2(VFB)
11V CSS
4.7V – 6.8V SHDN

SGND INTVCC RUN

3859A BD

13
3859af
LTC3859A
14
BOOST CHANNEL 3 INTVCC VOUT3

DB
BOOST3
BOTON
CLK1
LTC3859A

S Q
R Q TG3 CB
TOP
SHDN COUT

SWITCHING
SW3
LOGIC
PLLIN/MODE
INTVCC CIN
BG3
BOT VIN3
functional diagram

0.425V + SLEEP
OV3 PGND
–
+ 1.32V ICMP IR
+ +
– VFB3 L RSENSE
– –+ +– –
2mV SENSE3–

2.8V
0.7V
SENSE3+

+
SLOPE COMP SNSLO
– 2V VFB3
RB
+
EA – 1.2V
– SS3 RA

OV +
– 1.32V
ITH3 CC
0.5µA
1µA SS3
CC2 RC
11V
CSS
SHDN SNSLO

RUN3

3859A BD

3859af
 LTC3859A
Operation (Refer to Functional Diagram)

Main Control Loop Each top MOSFET driver is biased from the floating
The LTC3859A uses a constant frequency, current mode bootstrap capacitor CB, which normally recharges during
each cycle through an external diode when the switch
step-down architecture. The two buck controllers, chan-
voltage goes low.
nels 1 and 2, operate 180 degrees out of phase with each
other. The boost controller, channel 3, operates in phase For buck channels 1 and 2, if the buck’s input voltage
with channel 1. During normal operation, the external decreases to a voltage close to its output, the loop may
top MOSFET for the buck channels (the external bottom enter dropout and attempt to turn on the top MOSFET
MOSFET for the boost channel) is turned on when the continuously. The dropout detector detects this and forces
clock for that channel sets the RS latch, and is turned off the top MOSFET off for about one twelfth of the clock
when the main current comparator, ICMP, resets the RS period every tenth cycle to allow CB to recharge.
latch. The peak inductor current at which ICMP trips and
resets the latch is controlled by the voltage on the ITH pin, Shutdown and Start-Up (RUN1, RUN2, RUN3 and
which is the output of the error amplifier EA. The error TRACK/SS1, TRACK/SS2, SS3 Pins)
amplifier compares the output voltage feedback signal at The three channels of the LTC3859A can be independently
the VFB pin, (which is generated with an external resistor shut down using the RUN1, RUN2 and RUN3 pins. Pulling
divider connected across the output voltage, VOUT, to RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts
ground) to the internal 0.800V reference voltage for the down the main control loop for that channel. Pulling all
bucks (1.2V reference voltage for the boost). When the three pins below 0.7V disables all controllers and most
load current increases, it causes a slight decrease in VFB internal circuits, including the INTVCC LDOs. In this state,
relative to the reference, which causes the EA to increase the LTC3859A draws only 14µA of quiescent current.
the ITH voltage until the average inductor current matches
the new load current. Releasing a RUN pin allows a small internal current to pull
up the pin to enable that controller. The RUN1 pin has a
After the top MOSFET for the bucks (the bottom MOSFET 6µA pull-up current while the RUN2 and RUN3 pins have
for the boost) is turned off each cycle, the bottom MOSFET a smaller 0.5µA. The 6µA current on RUN1 is designed
is turned on (the top MOSFET for the boost) until either to be large enough so that the RUN1 pin can be safely
the inductor current starts to reverse, as indicated by the floated (to always enable the controller) without worry
current comparator IR, or the beginning of the next clock of condensation or other small board leakage pulling the
cycle. pin down. This is ideal for always-on applications where
one or more controllers are enabled continuously and
INTVCC/EXTVCC Power
never shut down.
Power for the top and bottom MOSFET drivers and most
Each RUN pin may also be externally pulled up or driven
other internal circuitry is derived from the INTVCC pin.
directly by logic. When driving a RUN pin with a low
When the EXTVCC pin is left open or tied to a voltage less
impedance source, do not exceed the absolute maximum
than 4.7V, the VBIAS LDO (low dropout linear regulator)
rating of 8V. Each RUN pin has an internal 11V voltage
supplies 5.4V from VBIAS to INTVCC. If EXTVCC is taken
clamp that allows the RUN pin to be connected through
above 4.7V, the VBIAS LDO is turned off and an EXTVCC
a resistor to a higher voltage (for example, VBIAS), so
LDO is turned on. Once enabled, the EXTVCC LDO supplies
long as the maximum current in the RUN pin does not
5.4V from EXTVCC to INTVCC. Using the EXTVCC pin allows
exceed 100µA.
the INTVCC power to be derived from a high efficiency
external source such as one of the LTC3859A switching The start-up of each channel’s output voltage VOUT is
regulator outputs. controlled by the voltage on the TRACK/SS pin (TRACK/SS1
for channel 1, TRACK/SS2 for channel 2, SS3 for channel 3).
When the voltage on the TRACK/SS pin is less than the
3859af

15
LTC3859A
operation
0.8V internal reference for the bucks and the 1.2V internal current. If two channels are in sleep mode and the other
reference for the boost, the LTC3859A regulates the VFB shut down, it draws only 65µA of quiescent current. If all
voltage to the TRACK/SS pin voltage instead of the cor- three controllers are enabled in sleep mode, the LTC3859A
responding reference voltage. This allows the TRACK/SS draws only 80µA of quiescent. In sleep mode, the load
pin to be used to program a soft-start by connecting an current is supplied by the output capacitor. As the output
external capacitor from the TRACK/SS pin to SGND. An voltage decreases, the EA’s output begins to rise. When the
internal 1µA pull-up current charges this capacitor creating output voltage drops enough, the ITH pin is reconnected
a voltage ramp on the TRACK/SS pin. As the TRACK/SS to the output of the EA, the sleep signal goes low, and the
voltage rises linearly from 0V to 0.8V/1.2V (and beyond controller resumes normal operation by turning on the top
up to INTVCC), the output voltage VOUT rises smoothly external MOSFET on the next cycle of the internal oscillator.
from zero to its final value. When a controller is enabled for Burst Mode operation,
Alternatively the TRACK/SS pins for buck channels 1 and 2 the inductor current is not allowed to reverse. The reverse
can be used to cause the start-up of VOUT to track that of current comparator (IR) turns off the bottom external
another supply. Typically, this requires connecting to the MOSFET (the top external MOSFET for the boost) just
TRACK/SS pin an external resistor divider from the other sup- before the inductor current reaches zero, preventing it
ply to ground (see the Applications Information section). from reversing and going negative. Thus, the controller
operates in discontinuous operation.
Light Load Current Operation (Burst Mode Operation, In forced continuous operation or clocked by an external
Pulse-Skipping, or Continuous Conduction) clock source to use the phase-locked loop (see the Fre-
(PLLIN/MODE Pin) quency Selection and Phase-Locked Loop section), the
The LTC3859A can be enabled to enter high efficiency inductor current is allowed to reverse at light loads or
Burst Mode operation, constant frequency pulse-skipping under large transient conditions. The peak inductor cur-
mode or forced continuous conduction mode at low load rent is determined by the voltage on the ITH pin, just as
currents. To select Burst Mode operation, tie the PLLIN/ in normal operation. In this mode, the efficiency at light
MODE pin to ground. To select forced continuous opera- loads is lower than in Burst Mode operation. However,
tion, tie the PLLIN/MODE pin to INTVCC. To select pulse- continuous operation has the advantage of lower output
skipping mode, tie the PLLIN/MODE pin to a DC voltage voltage ripple and less interference to audio circuitry. In
greater than 1.2V and less than INTVCC – 1.3V. forced continuous mode, the output ripple is independent
of load current.
When a controller is enabled for Burst Mode operation, the
minimum peak current in the inductor is set to approxi- When the PLLIN/MODE pin is connected for pulse-skipping
mately 25% of the maximum sense voltage (30% for the mode, the LTC3859A operates in PWM pulse-skipping
boost) even though the voltage on the ITH pin indicates a mode at light loads. In this mode, constant frequency
lower value. If the average inductor current is higher than operation is maintained down to approximately 1% of
the load current, the error amplifier EA will decrease the designed maximum output current. At very light loads, the
voltage on the ITH pin. When the ITH voltage drops below current comparator ICMP may remain tripped for several
0.425V, the internal sleep signal goes high (enabling sleep cycles and force the external top MOSFET to stay off for
mode) and both external MOSFETs are turned off. The ITH the same number of cycles (i.e., skipping pulses). The
pin is then disconnected from the output of the EA and inductor current is not allowed to reverse (discontinuous
parked at 0.450V. operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
In sleep mode, much of the internal circuitry is turned off, reduced RF interference as compared to Burst Mode
reducing the quiescent current that the LTC3859A draws. operation. It provides higher low current efficiency than
If one channel is in sleep mode and the other two are forced continuous mode, but not nearly as high as Burst
shut down, the LTC3859A draws only 55µA of quiescent Mode operation.
3859af

16
 LTC3859A
Operation
Frequency Selection and Phase-Locked Loop Boost Controller Operation When VIN > VOUT
(FREQ and PLLIN/MODE Pins) When the input voltage to the boost channel rises above
The selection of switching frequency is a tradeoff between its regulated VOUT voltage, the controller can behave
efficiency and component size. Low frequency opera- differently depending on the mode, inductor current and
tion increases efficiency by reducing MOSFET switching VIN voltage. In forced continuous mode, the loop works
losses, but requires larger inductance and/or capacitance to keep the top MOSFET on continuously once VIN rises
to maintain low output ripple voltage. above VOUT. An internal charge pump delivers current to
the boost capacitor from the BOOST3 pin to maintain a
The switching frequency of the LTC3859A’s controllers sufficiently high TG voltage. (The amount of current the
can be selected using the FREQ pin. charge pump can deliver is characterized by two curves
If the PLLIN/MODE pin is not being driven by an external in the Typical Performance Characteristics section.)
clock source, the FREQ pin can be tied to SGND, tied to In pulse-skipping mode, if VIN is between 100% and
INTVCC, or programmed through an external resistor. Tying 110% of the regulated VOUT voltage, TG3 turns on if the
FREQ to SGND selects 350kHz while tying FREQ to INTVCC inductor current rises above approximately 3% of the
selects 535kHz. Placing a resistor between FREQ and programmed ILIM current. If the part is programmed in
SGND allows the frequency to be programmed between Burst Mode operation under this same VIN window, then
50kHz and 900kHz. TG3 turns on at the same threshold current as long as
A phase-locked loop (PLL) is available on the LTC3859A the chip is awake (one of the buck channels is awake and
to synchronize the internal oscillator to an external clock switching). If both buck channels are asleep or shut down
source that is connected to the PLLIN/MODE pin. The in this VIN window, then TG3 will remain off regardless of
LTC3859A’s phase detector adjusts the voltage (through the inductor current.
an internal lowpass filter) of the VCO input to align the If VIN rises above 110% of the regulated VOUT voltage in
turn-on of controller 1’s external top MOSFET to the ris- any mode, the controller turns on TG3 regardless of the
ing edge of the synchronizing signal. Thus, the turn-on inductor current. In Burst Mode operation, however, the
of controller 2’s external top MOSFET is 180 degrees out internal charge pump turns off if the entire chip is asleep
of phase to the rising edge of the external clock source. (the two buck channels are asleep or shut down). With
The VCO input voltage is pre-biased to the operating the charge pump off, there would be nothing to prevent
frequency set by the FREQ pin before the external clock the boost capacitor from discharging, resulting in an
is applied. If prebiased near the external clock frequency, insufficient TG voltage needed to keep the top MOSFET
the PLL loop only needs to make slight changes to the completely on. The charge pump turns back on when the
VCO input in order to synchronize the rising edge of the chip wakes up, and it remains on as long as one of the
external clock’s to the rising edge of TG1. The ability to buck channels is actively switching.
pre-bias the loop filter allows the PLL to lock in rapidly Boost Controller at Low SENSE Pin Common Voltage
without deviating far from the desired frequency.
The current comparator of the boost controller is powered
The typical capture range of the LTC3859A’s phase-locked directly from the SENSE3+ pin and can operate to voltages
loop is from approximately 55kHz to 1MHz, with a guar- as low as 2.5V. Since this is lower than the VBIAS UVLO of
antee over all manufacturing variations to be between the chip, VBIAS can be connected to the output of the boost
75kHz and 850kHz. In other words, the LTC3859A’s PLL controller, as illustrated in the typical application circuit
is guaranteed to lock to an external clock source whose in Figure 12. This allows the boost controller to handle
frequency is between 75kHz and 850kHz. input voltage transients down to 2.5V while maintaining
The typical input clock thresholds on the PLLIN/MODE output voltage regulation. If the SENSE3+ rises back
pin are 1.6V (rising) and 1.2V (falling). above 2.5V, the SS3 pin will be released initiating a new
soft-start sequence.
3859af

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LTC3859A
operation
Buck Controller Output Overvoltage Protection Buck Foldback Current
The two buck channels have an overvoltage comparator When the buck output voltage falls to less than 70% of
that guards against transient overshoots as well as other its nominal level, foldback current limiting is activated,
more serious conditions that may overvoltage their outputs. progressively lowering the peak current limit in proportion
When the VFB1,2 pin rises by more than 10% above its to the severity of the overcurrent or short-circuit condition.
regulation point of 0.800V, the top MOSFET is turned off Foldback current limiting is disabled during the soft-start
and the bottom MOSFET is turned on until the overvoltage interval (as long as the VFB voltage is keeping up with
condition is cleared. the TRACK/SS1,2 voltage). There is no foldback current
limiting for the boost channel.
Channel 1 Power Good (PGOOD1)
Channel 1 has a PGOOD1 pin that is connected to an open THEORY AND BENEFITS OF 2-PHASE OPERATION
drain of an internal N-channel MOSFET. The MOSFET Why the need for 2-phase operation? Up until the 2-phase
turns on and pulls the PGOOD1 pin low when the VFB1 pin family, constant-frequency dual switching regulators
voltage is not within ±10% of the 0.8V reference voltage
operated both channels in phase (i.e., single-phase
for the buck channel. The PGOOD1 pin is also pulled low
operation). This means that both switches turned on at
when the RUN1 pin is low (shut down). When the VFB1
the same time, causing current pulses of up to twice the
pin voltage is within the ±10% requirement, the MOSFET
amplitude of those for one regulator to be drawn from the
is turned off and the pin is allowed to be pulled up by an
input capacitor and battery. These large amplitude current
external resistor to a source no greater than 6V.
pulses increased the total RMS current flowing from the
Boost Overvoltage Indicator (OV3) input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
The OV3 pin is an overvoltage indicator that signals capacitor and battery.
whether the output voltage of the channel 3 boost control-
ler goes over its programmed regulated voltage. The pin With 2-phase operation, the two buck controllers of the
is connected to an open drain of an internal N-channel LTC3859A are operated 180 degrees out of phase. This
MOSFET. The MOSFET turns on and pulls the OV3 pin low effectively interleaves the current pulses drawn by the
when the VFB3 pin voltage is less than 110% of the 1.2V switches, greatly reducing the overlap time where they add
reference voltage for the boost channel. The OV3 pin is together. The result is a significant reduction in total RMS
also pulled low when the RUN3 pin is low (shut down). input current, which in turn allows less expensive input
When the VFB3 pin voltage goes higher than 110% of the capacitors to be used, reduces shielding requirements for
1.2V reference, the MOSFET is turned off and the pin is EMI and improves real world operating efficiency.
allowed to be pulled up by an external resistor to a source
no greater than 6V.

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18
 LTC3859A
Operation

5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV

INPUT CURRENT
5A/DIV

INPUT VOLTAGE
500mV/DIV

IIN(MEAS) = 2.53ARMS 3859A F01a

IIN(MEAS) = 1.55ARMS 3859A F01b

(a) (b)
Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching
Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator
Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

Figure 1 compares the input waveforms for a representative It can readily be seen that the advantages of 2-phase op-
single-phase dual switching regulator to the 2-phase dual eration are not just limited to a narrow operating range,
buck controllers of the LTC3859A. An actual measure- for most applications is that 2-phase operation will reduce
ment of the RMS input current under these conditions the input capacitor requirement to that for just one channel
shows that 2-phase operation dropped the input current operating at maximum current and 50% duty cycle.
from 2.53ARMS to 1.55ARMS. While this is an impressive The schematic on the first page is a basic LTC3859A ap-
reduction in itself, remember that the power losses are
plication circuit. External component selection is driven
proportional to IRMS2, meaning that the actual power wasted
by the load requirement, and begins with the selection of
is reduced by a factor of 2.66. The reduced input ripple
RSENSE and the inductor value. Next, the power MOSFETs
voltage also means less power is lost in the input power are selected. Finally, CIN and COUT are selected.
path, which could include batteries, switches, trace/con-
nector resistances and protection circuitry. Improvements 3.0

in both conducted and radiated EMI also directly accrue SINGLE PHASE
DUAL CONTROLLER
2.5
as a result of the reduced RMS input current and voltage.
INPUT RMS CURRENT (A)

2.0
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative 1.5
duty cycles which, in turn, are dependent upon the input 2-PHASE
DUAL CONTROLLER
voltage VIN (Duty Cycle = VOUT/VIN). Figure 2 shows how 1.0

the RMS input current varies for single-phase and 2-phase 0.5
VO1 = 5V/3A
operation for 3.3V and 5V regulators over a wide input VO2 = 3.3V/3A
voltage range. 0
0 10 20 30 40
INPUT VOLTAGE (V) 3859A F02

Figure 2. RMS Input Current Comparison

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LTC3859A
Applications Information
The Typical Application on the first page is a basic LTC3859A on the SENSE3– pin allows the current comparator to be
application circuit. LTC3859A can be configured to use used in inductor DCR sensing.
either DCR (inductor resistance) sensing or low value Filter components mutual to the sense lines should be
resistor sensing. The choice between the two current placed close to the LTC3859A, and the sense lines should
sensing schemes is largely a design trade-off between run close together to a Kelvin connection underneath the
cost, power consumption, and accuracy. DCR sensing current sense element (shown in Figure 3). Sensing cur-
is becoming popular because it saves expensive current rent elsewhere can effectively add parasitic inductance
sensing resistors and is more power efficient, especially and capacitance to the current sense element, degrading
in high current applications. However, current sensing the information at the sense terminals and making the
resistors provide the most accurate current limits for the programmed current limit unpredictable. If DCR sensing
controller. Other external component selection is driven is used (Figure 4b), sense resistor R1 should be placed
by the load requirement, and begins with the selection of close to the switching node, to prevent noise from coupling
RSENSE (if RSENSE is used) and inductor value. Next, the into sensitive small-signal nodes.
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected. TO SENSE FILTER
NEXT TO THE CONTROLLER

SENSE+ and SENSE– Pins

The SENSE+ and SENSE– pins are the inputs to the current CURRENT FLOW
comparators. 3859A F03
INDUCTOR OR RSENSE
Buck Controllers (SENSE1+/SENSE1–,SENSE2+/SENSE2–):
The common mode voltage range on these pins is 0V Figure 3. Sense Lines Placement with Inductor or Sense Resistor
to 28V (absolute maximum), enabling the LTC3859A to
Low Value Resistor Current Sensing
regulate buck output voltages up to a nominal 24V (al-
lowing margin for tolerances and transients). The SENSE+ A typical sensing circuit using a discrete resistor is shown
pin is high impedance over the full common mode range, in Figure 4a. RSENSE is chosen based on the required
drawing at most ±1µA. This high impedance allows the output current.
current comparators to be used in inductor DCR sensing. The current comparators have a maximum threshold
The impedance of the SENSE– pin changes depending on VSENSE(MAX) of 50mV. The current comparator threshold
the common mode voltage. When SENSE– is less than sets the peak of the inductor current, yielding a maximum
INTVCC –0.5V, a small current of less than 1µA flows out average output current, IMAX, equal to the peak value less
of the pin. When SENSE– is above INTVCC +0.5V, a higher half the peak-to-peak ripple current, DIL. To calculate the
current (≈700µA) flows into the pin. Between INTVCC –0.5V sense resistor value, use the equation:
and INTVCC +0.5V, the current transitions from the smaller VSENSE(MAX)
current to the higher current. RSENSE =
DI
Boost Controller (SENSE3+/SENSE3–): The common IMAX + L
2
mode input range for these pins is 2.5V to 38V, allowing When using the buck controllers in very low dropout
the boost converter to operate from inputs over this full conditions, the maximum output current level will be
range. The SENSE3+ pin also provides power to the cur- reduced due to the internal compensation required to
rent comparator and draws about 170µA during normal meet stability criterion for buck regulators operating at
operation (when not shut down or asleep in Burst Mode greater than 50% duty factor. A curve is provided in the
operation). There is a small bias current of less than 1µA Typical Performance Characteristics section to estimate
that flows out of the SENSE3– pin. This high impedance this reduction in peak output current level depending upon
the operating duty factor.
3859af

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 LTC3859A
Applications Information
VIN1,2 If the external R1||R2 • C1 time constant is chosen to be
(VOUT3)
INTVCC exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
BOOST
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
LTC3859A
TG
RSENSE
voltage across the sense terminals for applications where
SW
VOUT1,2
(VIN3)
the DCR is greater than the target sense resistor value.
BG To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
SENSE1,2+ using a good RLC meter, but the DCR tolerance is not
(SENSE3–)
CAP always the same and varies with temperature; consult the
PLACED NEAR SENSE PINS
SENSE1, 2–
(SENSE3+)
manufacturers’ data sheets for detailed information.
SGND Using the inductor ripple current value from the Inductor
3859A F04a Value Calculation section, the target sense resistor value
4a. Using a Resistor to Sense Current
is:
VSENSE(MAX)
R(EQUIV) =
DI
VIN1,2 IMAX + L
INTVCC
(VOUT3) 2
To ensure that the application will deliver full load cur-
BOOST rent over the full operating temperature range, determine
TG
INDUCTOR
RSENSE(EQUIV), keeping in mind that the maximum current
LTC3859A
SW
L DCR VOUT1,2 sense threshold (VSENSE(MAX)) for the LTC3859A is fixed
(VIN3)
BG
at 50mV.
Next, determine the DCR of the inductor. Where provided,
R1
SENSE1, 2+ use the manufacturer’s maximum value, usually given at
(SENSE3–)
C1* R2 20°C. Increase this value to account for the temperature
SENSE1, 2–
(SENSE3+) coefficient of resistance, which is approximately 0.4%/°C.
SGND
A conservative value for TL(MAX) is 100°C.
3859A F04b

(R1||R2) • C1 = L/DCR
To scale the maximum inductor DCR to the desired sense
*PLACE C1 NEAR SENSE PINS RSENSE(EQ) = DCR(R2/(R1+R2)) resistor value, use the divider ratio:
RSENSE(EQUIV)
4b. Using the Inductor DCR to Sense Current RD =
DCRMAX at TL(MAX)
Figure 4. Current Sensing Methods
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
This forces R1||R2 to around 2k, reducing error that might
Inductor DCR Sensing
have been caused by the SENSE+ pin’s ±1µA current.
For applications requiring the highest possible efficiency at The equivalent resistance R1||R2 is scaled to the room
high load currents, the LTC3859A is capable of sensing the temperature inductance and maximum DCR:
voltage drop across the inductor DCR, as shown in Figure 4b.
L
The DCR of the inductor represents the small amount of R1 R2 =
DC winding resistance of the copper, which can be less (DCR at 20°C) • C1

than 1mΩ for today’s low value, high current inductors.
The sense resistor values are:
In a high current application requiring such an inductor,
conduction loss through a sense resistor would cost several R1 R2 R1• RD
R1= ; R2 =
points of efficiency compared to DCR sensing.  RD 1− RD
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LTC3859A
applications information
The maximum power loss in R1 is related to duty cycle. For Accepting larger values of DIL allows the use of low
the buck controllers, the maximum power loss will occur inductances, but results in higher output voltage ripple
in continuous mode at the maximum input voltage: and greater core losses. A reasonable starting point for
(VIN(MAX) − VOUT ) • VOUT setting ripple current is DIL = 0.3(IMAX). The maximum
PLOSS R1= DIL occurs at the maximum input voltage for the bucks
R1 and VIN = 1/2•VOUT for the boost.
For the boost controller, the maximum power loss in R1 The inductor value also has secondary effects. The tran-
will occur in continuous mode at VIN = 1/2•VOUT : sition to Burst Mode operation begins when the average
(VOUT(MAX) − VIN ) • VIN inductor current required results in a peak current below
PLOSS R1= 25% of the current limit (30% for the boost) determined
R1 by RSENSE. Lower inductor values (higher DIL) will cause
Ensure that R1 has a power rating higher than this value. this to occur at lower load currents, which can cause a dip
If high efficiency is necessary at light loads, consider this in efficiency in the upper range of low current operation. In
power loss when deciding whether to use DCR sensing or Burst Mode operation, lower inductance values will cause
sense resistors. Light load power loss can be modestly the burst frequency to decrease.
higher with a DCR network than with a sense resistor, due
Inductor Core Selection
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc- Once the value for L is known, the type of inductor must
tion losses and provides higher efficiency at heavy loads. be selected. High efficiency converters generally cannot
Peak efficiency is about the same with either method. afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
Inductor Value Calculation cores. Actual core loss is independent of core size for a
The operating frequency and inductor selection are inter- fixed inductor value, but it is very dependent on inductance
related in that higher operating frequencies allow the use selected. As inductance increases, core losses go down.
of smaller inductor and capacitor values. So why would Unfortunately, increased inductance requires more turns
anyone ever choose to operate at lower frequencies with of wire and therefore copper losses will increase.
larger components? The answer is efficiency. A higher Ferrite designs have very low core loss and are preferred
frequency generally results in lower efficiency because at high switching frequencies, so design goals can con-
of MOSFET gate charge losses. In addition to this basic centrate on copper loss and preventing saturation. Ferrite
trade-off, the effect of inductor value on ripple current and core material saturates “hard,” which means that induc-
low current operation must also be considered. tance collapses abruptly when the peak design current is
The inductor value has a direct effect on ripple current. exceeded. This results in an abrupt increase in inductor
The inductor ripple current DIL decreases with higher ripple current and consequent output voltage ripple. Do
inductance or frequency. For the buck controllers, DIL not allow the core to saturate!
increases with higher VIN:
1  V 
DIL = VOUT 1− OUT 
(f)(L)  VIN 
For the boost controller, the inductor ripple current DIL
increases with higher VOUT:
1  V 
DIL = VIN 1− IN 
(f)(L)  VOUT 
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 LTC3859A
Applications Information
Power MOSFET and Schottky Diode The MOSFET power dissipations at maximum output
(Optional) Selection current are given by:
Two external power MOSFETs must be selected for each VOUT
( )
2
controller in the LTC3859A: one N-channel MOSFET for the PMAIN _ BUCK = IOUT(MAX) (1+ δ) RDS(ON) +
VIN
top switch (main switch for the buck, synchronous for the
boost), and one N-channel MOSFET for the bottom switch  IOUT(MAX) 
(VIN )2  (RDR )(CMILLER ) •
(main switch for the boost, synchronous for the buck).  2 
The peak-to-peak drive levels are set by the INTVCC voltage.  1 1 
This voltage is typically 5.4V during start-up (see EXTVCC  + (f)
Pin Connection). Consequently, logic-level threshold  VINTVCC − VTHMIN VTHMIN 
MOSFETs must be used in most applications. Pay close V −V
( )
2
PSYNC _ BUCK = IN OUT IOUT(MAX) (1+ δ) RDS(ON)
attention to the BVDSS specification for the MOSFETs as VIN
well; many of the logic level MOSFETs are limited to 30V
( VOUT − VIN ) VOUT
or less.
(IOUT(MAX) )
2
PMAIN _ BOOST = 2
•
Selection criteria for the power MOSFETs include the VIN
on-resistance RDS(ON), Miller capacitance CMILLER, input  V2   IOUT(MAX) 
voltage and maximum output current. Miller capacitance, (1+ δ) RDS(ON) +  OUT   •
CMILLER, can be approximated from the gate charge curve  VIN  2 
usually provided on the MOSFET manufacturers’ data  1 1 
sheet. CMILLER is equal to the increase in gate charge (RDR ) (CMILLER ) •  + (f)
along the horizontal axis while the curve is approximately  VINTVCC − VTHMIN VTHMIN 
flat divided by the specified change in VDS. This result is VIN
( ) (1+ δ)RDS(ON)
2
PSYNC _ BOOST = IOUT(MAX)
then multiplied by the ratio of the application applied VDS VOUT
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top where z is the temperature dependency of RDS(ON) and
and bottom MOSFETs are given by: RDR (approximately 2Ω) is the effective driver resistance
V at the MOSFET’s Miller threshold voltage. VTHMIN is the
Buck Main Switch Duty Cycle = OUT
VIN typical MOSFET minimum threshold voltage.
V − VOUT Both MOSFETs have I2R losses while the main N-channel
Buck Sync Switch Duty Cycle = IN equations for the buck and boost controllers include an
VIN
additional term for transition losses, which are highest at
V − VIN high input voltages for the bucks and low input voltages for
Boost Main Switch Duty Cycle = OUT
VOUT the boost. For VIN < 20V (high VIN for the boost) the high
VIN current efficiency generally improves with larger MOSFETs,
Boost Sync Switch Duty Cycle = while for VIN > 20V (low VIN for the boost) the transition
VOUT
losses rapidly increase to the point that the use of a higher
RDS(ON) device with lower CMILLER actually provides higher

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LTC3859A
applications information
efficiency. The synchronous MOSFET losses for the buck In a boost converter, the output has a discontinuous current,
controllers are greatest at high input voltage when the top so COUT must be capable of reducing the output voltage
switch duty factor is low or during a short-circuit when the ripple. The effects of ESR (equivalent series resistance) and
synchronous switch is on close to 100% of the period. The the bulk capacitance must be considered when choosing
synchronous MOSFET losses for the boost controller are the right capacitor for a given output ripple voltage. The
greatest when the input voltage approaches the output volt- steady ripple due to charging and discharging the bulk
age or during an overvoltage event when the synchronous capacitance is given by:
switch is on 100% of the period.
Ripple =
(
I OUT(MAX) • VOUT − VIN(MIN) )V
The term (1+ z) is generally given for a MOSFET in the COUT • VOUT • f
form of a normalized RDS(ON) vs Temperature curve, but
z = 0.005/°C can be used as an approximation for low where COUT is the output filter capacitor.
voltage MOSFETs. The steady ripple due to the voltage drop across the ESR
The optional Schottky diodes D4, D5, and D6 shown in is given by:
Figure 13 conduct during the dead-time between the DVESR = IL(MAX) • ESR
conduction of the two power MOSFETs. This prevents
Multiple capacitors placed in parallel may be needed to
the body diode of the synchronous MOSFET from turning
meet the ESR and RMS current handling requirements.
on, storing charge during the dead-time and requiring a
Dry tantalum, special polymer, aluminum electrolytic and
reverse recovery period that could cost as much as 3% ceramic capacitors are all available in surface mount
in efficiency at high VIN. A 1A to 3A Schottky is generally packages. Ceramic capacitors have excellent low ESR
a good compromise for both regions of operation due to characteristics but can have a high voltage coefficient.
the relatively small average current. Larger diodes result Capacitors are now available with low ESR and high ripple
in additional transition losses due to their larger junction current ratings such as OS-CON and POSCAP.
capacitance.
Buck CIN, COUT Selection
Boost CIN, COUT Selection
The selection of CIN for the two buck controllers is simplified
The input ripple current in a boost converter is relatively by the 2-phase architecture and its impact on the worst-
low (compared with the output ripple current), because case RMS current drawn through the input network (bat-
this current is continuous. The boost input capacitor CIN tery/fuse/capacitor). It can be shown that the worst-case
voltage rating should comfortably exceed the maximum capacitor RMS current occurs when only one controller
input voltage. Although ceramic capacitors can be relatively is operating. The controller with the highest (VOUT)(IOUT)
tolerant of overvoltage conditions, aluminum electrolytic product needs to be used in the formula shown in Equa-
capacitors are not. Be sure to characterize the input voltage tion (1) to determine the maximum RMS capacitor current
for any possible overvoltage transients that could apply requirement. Increasing the output current drawn from
excess stress to the input capacitors. the other controller will actually decrease the input RMS
The value of CIN is a function of the source impedance, and ripple current from its maximum value. The out-of-phase
in general, the higher the source impedance, the higher the technique typically reduces the input capacitor’s RMS
required input capacitance. The required amount of input ripple current by a factor of 30% to 70% when compared
capacitance is also greatly affected by the duty cycle. High to a single phase power supply solution.
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.

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 LTC3859A
Applications Information
In continuous mode, the source current of the top MOSFET A small (0.1µF to 1µF) bypass capacitor between the chip
is a square wave of duty cycle (VOUT)/(VIN). To prevent VIN pin and ground, placed close to the LTC3859A, is also
large voltage transients, a low ESR capacitor sized for the suggested. A small (1Ω to 10Ω) resistor placed between
maximum RMS current of one channel must be used. The CIN (C1) and the VIN pin provides further isolation between
maximum RMS capacitor current is given by: the two channels.
IMAX The selection of COUT is driven by the effective series
CIN Required IRMS ≈ ( VOUT ) ( VIN − VOUT )1/ 2 resistance (ESR). Typically, once the ESR requirement
VIN (1)
is satisfied, the capacitance is adequate for filtering. The
This formula has a maximum at VIN = 2VOUT, where IRMS output ripple (DVOUT) is approximated by:
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not  1 
DVOUT ≈ DIL ESR + 
offer much relief. Note that capacitor manufacturers’ ripple  8fCOUT 
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or where f is the operating frequency, COUT is the output
to choose a capacitor rated at a higher temperature than capacitance and DIL is the ripple current in the inductor.
required. Several capacitors may be paralleled to meet The output ripple is highest at maximum input voltage
size or height requirements in the design. Due to the high since DIL increases with input voltage.
operating frequency of the LTC3859A, ceramic capacitors
Setting Output Voltage
can also be used for CIN. Always consult the manufacturer
if there is any question. The LTC3859A output voltages are each set by an external
The benefit of the LTC3859A 2-phase operation can be cal- feedback resistor divider carefully placed across the output,
culated by using Equation (1) for the higher power controller as shown in Figure 5. The regulated output voltages are
and then calculating the loss that would have resulted if determined by:
both controller channels switched on at the same time.  R 
VOUT, BUCK = 0.8V 1+ B 
The total RMS power lost is lower when both controllers  RA 
are operating due to the reduced overlap of current pulses
 R 
required through the input capacitor’s ESR. This is why VOUT, BOOST = 1.2V 1+ B 
the input capacitor’s requirement calculated above for the  RA 
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery To improve the frequency response, a feedforward ca-
resistance, and PC board trace resistance losses are also pacitor, CFF, may be used. Great care should be taken to
reduced due to the reduced peak currents in a 2-phase route the VFB line away from noise sources, such as the
system. The overall benefit of a multiphase design will inductor or the SW line.
only be fully realized when the source impedance of the VOUT
power supply/battery is included in the efficiency testing.
The drains of the top MOSFETs should be placed within
RB CFF
1cm of each other and share a common CIN (s). Separat- 1/3 LTC3859A

ing the drains and CIN may produce undesirable voltage VFB

and current resonances at VIN. 3859A F05

RA

Figure 5. Setting Output Voltage

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LTC3859A
applications information
Tracking and Soft-Start 1/3 LTC3859A
(TRACK/SS1, TRACK/SS2, SS3 Pins) TRACK/SS
CSS
The start-up of each VOUT is controlled by the voltage on SGND
the respective TRACK/SS pin (TRACK/SS1 for channel 1, 3859A F06

TRACK/SS2 for channel 2, SS3 for channel 3). When the

voltage on the TRACK/SS pin is less than the internal Figure 6. Using the TRACK/SS Pin to Program Soft-Start
0.8V reference (1.2V reference for the boost channel), the
LTC3859A regulates the VFB pin voltage to the voltage on the
TRACK/SS pin instead of the internal reference. Likewise,
VX(MASTER)
the TRACK/SS pin for the buck channels can be used to
program an external soft-start function or to allow VOUT

OUTPUT (VOUT)
to track another supply during start-up.
VOUT(SLAVE)
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 6.
An internal 1µA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin. TIME 3859A F07a

The LTC3859A will regulate the VFB pin (and hence VOUT) 7a. Coincident Tracking
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value. VX(MASTER)
The total soft-start time will be approximately:
OUTPUT (VOUT)

0.8V
tSS _ BUCK = CSS • VOUT(SLAVE)
1µA
1.2V
tSS _ BOOST = CSS •
1µA
TIME 3859A F07b

Alternatively, the TRACK/SS1 and TRACK/SS2 pins for the 7b. Radiometric Tracking
two buck controllers can be used to track two (or more) sup-
plies during start-up, as shown qualitatively in Figures 7a Figure 7. Two Different Modes of Output Voltage Tracking
and 7b. To do this, a resistor divider should be connected
from the master supply (VX) to the TRACK/SS pin of the
slave supply (VOUT), as shown in Figure 8. During start-up VOUT

VOUT will track VX according to the ratio set by the resis- LTC3859A
tor divider: RB

VFB1,2
VX RA R + RTRACKB
= • TRACKA RA
VOUT RTRACKA RA + RB VX

For coincident tracking (VOUT = VX during start-up), RTRACKB

TRACK/SS1,2
RA = RTRACKA
RTRACKA
RB = RTRACKB
3859A F08

Figure 8. Using the TRACK/SS Pin for Tracking

3859af

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 LTC3859A
applications information
INTVCC Regulators To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
The LTC3859A features two separate internal P-channel
operating in continuous conduction mode (PLLIN/MODE
low dropout linear regulators (LDO) that supply power
= INTVCC) at maximum VIN.
at the INTVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connection of the EXTVCC When the voltage applied to EXTVCC rises above 4.7V, the
pin. INTVCC powers the gate drivers and much of the VBIAS LDO is turned off and the EXTVCC LDO is enabled.
LTC3859A’s internal circuitry. The VBIAS LDO and the The EXTVCC LDO remains on as long as the voltage applied
EXTVCC LDO regulate INTVCC to 5.4V. Each of these must to EXTVCC remains above 4.5V. The EXTVCC LDO attempts
be bypassed to ground with a minimum of 4.7µF ceramic to regulate the INTVCC voltage to 5.4V, so while EXTVCC
capacitor. No matter what type of bulk capacitor is used, an is less than 5.4V, the LDO is in dropout and the INTVCC
additional 1µF ceramic capacitor placed directly adjacent voltage is approximately equal to EXTVCC. When EXTVCC
to the INTVCC and PGND IC pins is highly recommended. is greater than 5.4V, up to an absolute maximum of 14V,
Good bypassing is needed to supply the high transient INTVCC is regulated to 5.4V.
currents required by the MOSFET gate drivers and to Using the EXTVCC LDO allows the MOSFET driver and
prevent interaction between the channels. control power to be derived from one of the LTC3859A’s
High input voltage applications in which large MOSFETs switching regulator outputs (4.7V ≤ VOUT ≤ 14V) dur-
are being driven at high frequencies may cause the maxi- ing normal operation and from the VBIAS LDO when the
mum junction temperature rating for the LTC3859A to be output is out of regulation (e.g., startup, short-circuit). If
exceeded. The INTVCC current, which is dominated by the more current is required through the EXTVCC LDO than
gate charge current, may be supplied by either the VBIAS is specified, an external Schottky diode can be added
LDO or the EXTVCC LDO. When the voltage on the EXTVCC between the EXTVCC and INTVCC pins. In this case, do
pin is less than 4.7V, the VBIAS LDO is enabled. Power dis- not apply more than 6V to the EXTVCC pin and make sure
sipation for the IC in this case is highest and is equal to than EXTVCC ≤ VBIAS.
VBIAS • IINTVCC. The gate charge current is dependent Significant efficiency and thermal gains can be realized
on operating frequency as discussed in the Efficiency
by powering INTVCC from the buck output, since the VIN
Considerations section. The junction temperature can be current resulting from the driver and control currents will
estimated by using the equations given in Note 2 of the be scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
Electrical Characteristics. For example, the LTC3859A For 5V to 14V regulator outputs, this means connecting
INTVCC current is limited to less than 40mA from a 40V the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
supply when not using the EXTVCC supply at a 70°C ambi- a 8.5V supply reduces the junction temperature in the
ent temperature in the QFN package:
previous example from 125°C to:
TJ = 70°C + (40mA)(40V)(34°C/W) = 125°C
TJ = 70°C + (40mA)(8.5V)(34°C/W) = 82°C
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTVCC power from
the output.

3859af

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LTC3859A
Applications Information
The following list summarizes the four possible connec- 3. EXTVCC connected to an external supply. If an external
tions for EXTVCC: supply is available in the 5V to 14V range, it may be
1. EXTVCC grounded. This will cause INTVCC to be powered used to power EXTVCC providing it is compatible with the
MOSFET gate drive requirements. Ensure that EXTVCC
from the internal 5.4V regulator resulting in an efficiency
< VIN.
penalty of up to 10% at high input voltages.
4. EXTVCC connected to an output-derived boost network
2. EXTVCC connected directly to the output voltage of one
off one of the buck regulators. For 3.3V and other low
of the buck regulators. This is the normal connection
voltage buck regulators, efficiency gains can still be
for a 5V to 14V regulator and provides the highest ef-
realized by connecting EXTVCC to an output-derived
ficiency.
voltage that has been boosted to greater than 4.7V. This
can be done with the capacitive charge pump shown in
Figure 9. Ensure that EXTVCC < VIN.

VIN1,2
BAT85 BAT85
C1
LTC3859A

MTOP BAT85
TG
EXTVCC RSENSE
L
SW VOUT1,2
MBOT

BG

PGND
3859A F09

Figure 9. Capacitive Charge Pump for EXTVCC

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 LTC3859A
applications information
Topside MOSFET Driver Supply (CB, DB) top MOSFET on continuously during dropout/overvolt-
External bootstrap capacitors CB connected to the BOOST age conditions. The Schottky/silicon diode selected for
pins supply the gate drive voltages for the topside MOSFETs. the boost topside driver should have a reverse leakage
Capacitor CB in the Functional Diagram is charged though less than the available output current the charge pump
external diode DB from INTVCC when the SW pin is low. can supply. Curves displaying the available charge pump
When one of the topside MOSFETs is to be turned on, the current under different operating conditions can be found
driver places the CB voltage across the gate-source of the in the Typical Performance Characteristics section.
desired MOSFET. This enhances the MOSFET and turns A leaky diode DB in the boost converter can not only
on the topside switch. The switch node voltage, SW, rises prevent the top MOSFET from fully turning on but it can
to VIN for the buck channels (VOUT for the boost channel) also completely discharge the bootstrap capacitor CB and
and the BOOST pin follows. With the topside MOSFET create a current path from the input voltage to the BOOST3
on, the boost voltage is above the input supply: VBOOST pin to INTVCC. This can cause INTVCC to rise if the diode
= VIN + VINTVCC (VBOOST = VOUT + VINTVCC for the boost leakage exceeds the current consumption on INTVCC . This
controller). The value of the boost capacitor CB needs to is particularly a concern in Burst Mode operation where
be 100 times that of the total input capacitance of the the load on INTVCC can be very small. There is an internal
topside MOSFET(s). The reverse breakdown of the external voltage clamp on INTVCC that prevents the INTVCC voltage
Schottky diode must be greater than VIN(MAX) for the buck from running away, but this clamp should be regarded as a
channels and VOUT(MAX) for the boost channel. failsafe only. The external Schottky or silicon diode should
The external diode DB can be a Schottky diode or silicon be carefully chosen such that INTVCC never gets charged
up much higher than its normal regulation voltage.
diode, but in either case it should have low leakage and fast
recovery. Pay close attention to the reverse leakage at high Care should also be taken when choosing the external
temperatures where it generally increases substantially. diode DB for the buck converters. A leaky diode not only
increases the quiescent current of the buck converter, but
The topside MOSFET driver for the boost channel includes
it can also cause a similar leakage path to INTVCC from
an internal charge pump that delivers current to the
VOUT for applications with output voltages greater than
bootstrap capacitor from the BOOST3 pin. This charge
the INTVCC voltage (~5.4V).
current maintains the bias voltage required to keep the

1000
900
800
700
FREQUENCY (kHz)

600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3859A F10

Figure 10. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

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LTC3859A
Applications Information
Fault Conditions: Buck Current Limit and Current A shorted top MOSFET for the buck channel will result in
Foldback a high current condition which will open the system fuse.
The LTC3859A includes current foldback for the buck The switching regulator will regulate properly with a leaky
channels to help limit load current when the output is top MOSFET by altering the duty cycle to accommodate
shorted to ground. If the buck output falls below 70% of the leakage.
its nominal output level, then the maximum sense volt-
Fault Conditions: Over Temperature Protection
age is progressively lowered from 100% to 40% of its
maximum selected value. Under short-circuit conditions At higher temperatures, or in cases where the internal
with very low duty cycles, the buck channel will begin power dissipation causes excessive self heating on chip
cycle skipping in order to limit the short-circuit current. (such as INTVCC short to ground), the over temperature
In this situation the bottom MOSFET will be dissipating shutdown circuitry will shut down the LTC3859A. When
most of the power but less than in normal operation. The the junction temperature exceeds approximately 170°C,
short-circuit ripple current is determined by the minimum the over temperature circuitry disables the INTVCC LDO,
on-time tON(MIN) of the LTC3859A (≈95ns), the input volt- causing the INTVCC supply to collapse and effectively
age and inductor value: shutting down the entire LTC3859A chip. Once the junc-
DIL(SC) = tON(MIN) (VIN/L) tion temperature drops back to approximately 155°C, the
INTVCC LDO turns back on. Long term overstress (TJ >
The resulting average short-circuit current is: 125°C) should be avoided as it can degrade the perfor-
1 mance or shorten the life of the part.
ISC = 40% • ILIM(MAX) − DIL(SC)
2
Fault Conditions: Buck Overvoltage Protection Phase-Locked Loop and Frequency Synchronization
(Crowbar) The LTC3859A has an internal phase-locked loop (PLL)
The overvoltage crowbar is designed to blow a system comprised of a phase frequency detector, a lowpass filter,
input fuse when the output voltage of the one of the buck and a voltage-controlled oscillator (VCO). This allows the
regulators rises much higher than nominal levels. The turn-on of the top MOSFET of controller 1 to be locked to
crowbar causes huge currents to flow, that blow the fuse the rising edge of an external clock signal applied to the
to protect against a shorted top MOSFET if the short oc- PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
curs while the controller is operating. is thus 180 degrees out of phase with the external clock.
A comparator monitors the buck output for overvoltage The phase detector is an edge sensitive digital type that
conditions. The comparator detects faults greater than provides zero degrees phase shift between the external
10% above the nominal output voltage. When this condi- and internal oscillators. This type of phase detector does
tion is sensed, the top MOSFET of the buck controller is not exhibit false lock to harmonics of the external clock.
turned off and the bottom MOSFET is turned on until the If the external clock frequency is greater than the internal
overvoltage condition is cleared. The bottom MOSFET oscillator’s frequency, fOSC, then current is sourced continu-
remains on continuously for as long as the overvoltage ously from the phase detector output, pulling up the VCO
condition persists; if VOUT returns to a safe level, normal input. When the external clock frequency is less than fOSC,
operation automatically resumes. current is sunk continuously, pulling down the VCO input.

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 LTC3859A
applications information
If the external and internal frequencies are the same but Minimum On-Time Considerations
exhibit a phase difference, the current sources turn on for
Minimum on-time tON(MIN) is the smallest time duration
an amount of time corresponding to the phase difference.
that the LTC3859A is capable of turning on the top MOSFET
The voltage at the VCO input is adjusted until the phase
(bottom MOSFET for the boost controller). It is determined
and frequency of the internal and external oscillators are
by internal timing delays and the gate charge required to
identical. At the stable operating point, the phase detector
turn on the top MOSFET. Low duty cycle applications may
output is high impedance and the internal filter capacitor,
approach this minimum on-time limit and care should be
CLP, holds the voltage at the VCO input.
taken to ensure that
Note that the LTC3859A can only be synchronized to an V
tON(MIN)_ BUCK < OUT
external clock whose frequency is within range of the VIN (f)
LTC3859A’s internal VCO, which is nominally 55kHz to V −V
1MHz. This is guaranteed to be between 75kHz and 850kHz. tON(MIN)_ BOOST < OUT IN
VOUT (f)
Typically, the external clock (on PLLIN/MODE pin) input high If the duty cycle falls below what can be accommodated
threshold is 1.6V, while the input low threshold is 1.2V. by the minimum on-time, the controller will begin to skip
Rapid phase-locking can be achieved by using the FREQ pin cycles. The output voltage will continue to be regulated,
to set a free-running frequency near the desired synchro- but the ripple voltage and current will increase.
nization frequency. The VCO’s input voltage is prebiased The minimum on-time for the LTC3859A is approximately
at a frequency correspond to the frequency set by the 95ns for the bucks and 120ns for the boost. However, as
FREQ pin. Once prebiased, the PLL only needs to adjust the peak sense voltage decreases the minimum on-time
the frequency slightly to achieve phase-lock and synchro- gradually increases up to about 130ns. This is of particu-
nization. Although it is not required that the free-running lar concern in forced continuous applications with low
frequency be near external clock frequency, doing so will ripple current at light loads. If the duty cycle drops below
prevent the operating frequency from passing through a the minimum on-time limit in this situation, a significant
large range of frequencies as the PLL locks. amount of cycle skipping can occur with correspondingly
Table 1 summarizes the different states in which the FREQ larger current and voltage ripple.
pin can be used.
Table 1
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor to SGND DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase-Locked to
External Clock

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LTC3859A
Applications Information
Efficiency Considerations 3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
The percent efficiency of a switching regulator is equal to
tor, and input and output capacitor ESR. In continuous
the output power divided by the input power times 100%.
mode the average output current flows through L and
It is often useful to analyze individual losses to determine
RSENSE, but is “chopped” between the topside MOSFET
what is limiting the efficiency and which change would
and the synchronous MOSFET. If the two MOSFETs have
produce the most improvement. Percent efficiency can
approximately the same RDS(ON), then the resistance
be expressed as:
of one MOSFET can simply be summed with the resis-
%Efficiency = 100% – (L1 + L2 + L3 + ...) tances of L, RSENSE and ESR to obtain I2R losses. For
where L1, L2, etc. are the individual losses as a percent- example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE
age of input power. = 10mΩ and RESR = 40mΩ (sum of both input and
output capacitance losses), then the total resistance
Although all dissipative elements in the circuit produce is 130mΩ. This results in losses ranging from 3% to
losses, four main sources usually account for most of the 13% as the output current increases from 1A to 5A for
losses in LTC3859A circuits: 1) IC VIN current, 2) INTVCC a 5V output, or a 4% to 20% loss for a 3.3V output.
regulator current, 3) I2R losses, 4) Topside MOSFET Efficiency varies as the inverse square of VOUT for the
transition losses. same external components and output power level. The
1. The VIN current is the DC supply current given in the combined effects of increasingly lower output voltages
Electrical Characteristics table, which excludes MOSFET and higher currents required by high performance digital
driver and control currents. VIN current typically results systems is not doubling but quadrupling the importance
in a small (<0.1%) loss. of loss terms in the switching regulator system!
2. INTVCC current is the sum of the MOSFET driver and 4. Transition losses apply only to the top MOSFET(s) (bot-
control currents. The MOSFET driver current results tom MOSFET for the boost), and become significant only
from switching the gate capacitance of the power when operating at high input voltages (typically 15V or
MOSFETs. Each time a MOSFET gate is switched from greater). Transition losses can be estimated from:
low to high to low again, a packet of charge, dQ, moves Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the Other hidden losses such as copper trace and internal
control circuit current. In continuous mode, IGATECHG battery resistances can account for an additional 5%
= f(QT + QB), where QT and QB are the gate charges of to 10% efficiency degradation in portable systems. It is
the topside and bottom side MOSFETs. very important to include these “system” level losses
during the design phase. The internal battery and fuse
Supplying INTVCC from an output-derived source power resistance losses can be minimized by making sure that
through EXTVCC will scale the VIN current required CIN has adequate charge storage and very low ESR at
for the driver and control circuits by a factor of (Duty the switching frequency. A 25W supply will typically
Cycle)/(Efficiency). For example, in a 20V to 5V applica- require a minimum of 20µF to 40µF of capacitance
tion, 10mA of INTVCC current results in approximately having a maximum of 20mΩ to 50mΩ of ESR. The
2.5mA of VIN current. This reduces the mid-current loss LTC3859A 2-phase architecture typically halves this
from 10% or more (if the driver was powered directly input capacitance requirement over competing solu-
from VIN) to only a few percent. tions. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.

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 LTC3859A
applications information
Checking Transient Response produce output voltage and ITH pin waveforms that will
The regulator loop response can be checked by looking at give a sense of the overall loop stability without breaking
the load current transient response. Switching regulators the feedback loop.
take several cycles to respond to a step in DC (resistive) Placing a power MOSFET directly across the output
load current. When a load step occurs, VOUT shifts by an capacitor and driving the gate with an appropriate signal
amount equal to DILOAD(ESR), where ESR is the effective generator is a practical way to produce a realistic load step
series resistance of COUT. DILOAD also begins to charge or condition. The initial output voltage step resulting from
discharge COUT generating the feedback error signal that the step change in output current may not be within the
forces the regulator to adapt to the current change and bandwidth of the feedback loop, so this signal cannot be
return VOUT to its steady-state value. During this recovery used to determine phase margin. This is why it is better to
time VOUT can be monitored for excessive overshoot or look at the ITH pin signal which is in the feedback loop and
ringing, which would indicate a stability problem. OPTI- is the filtered and compensated control loop response.
LOOP compensation allows the transient response to be
The gain of the loop will be increased by increasing
optimized over a wide range of output capacitance and
RC and the bandwidth of the loop will be increased by
ESR values. The availability of the ITH pin not only allows
decreasing CC. If RC is increased by the same factor
optimization of control loop behavior, but it also provides
that CC is decreased, the zero frequency will be kept the
a DC coupled and AC filtered closed loop response test
same, thereby keeping the phase shift the same in the
point. The DC step, rise time and settling at this test
most critical frequency range of the feedback loop. The
point truly reflects the closed loop response. Assuming a
output voltage settling behavior is related to the stability
predominantly second order system, phase margin and/
of the closed-loop system and will demonstrate the actual
or damping factor can be estimated using the percentage
overall supply performance.
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH A second, more severe transient is caused by switching
external components shown in Figure 16 will provide an in loads with large (>1µF) supply bypass capacitors. The
adequate starting point for most applications. discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
The ITH series RC-CC filter sets the dominant pole-zero
alter its delivery of current quickly enough to prevent this
loop compensation. The values can be modified slightly
sudden step change in output voltage if the load switch
(from 0.5 to 2 times their suggested values) to optimize
resistance is low and it is driven quickly. If the ratio of
transient response once the final PC layout is done and
CLOAD to COUT is greater than 1:50, the switch rise time
the particular output capacitor type and value have been
should be controlled so that the load rise time is limited
determined. The output capacitors need to be selected
to approximately 25 • CLOAD. Thus a 10µF capacitor would
because the various types and values determine the loop
require a 250µs rise time, limiting the charging current
gain and phase. An output current pulse of 20% to 80%
to about 200mA.
of full-load current having a rise time of 1µs to 10µs will

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LTC3859A
Applications Information
Buck Design Example The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
As a design example for one of the buck channels channel,
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
assume VIN = 12V(NOMINAL), VIN = 22V(MAX), VOUT = 3.3V,
maximum input voltage with T(estimated) = 50°C:
IMAX = 6A, VSENSE(MAX) = 50mV, and f = 350kHz.
3.3V
The inductance value is chosen first based on a 30% ripple PMAIN = (6A)2 {1+ (0.005)(50°C − 25°C)}
current assumption. The highest value of ripple current 22V
occurs at the maximum input voltage. Tie the FREQ pin 5A
(0.035Ω) + (22V)2 6 (2.5Ω)(215pF) •
to GND, generating 350kHz operation. The minimum 2
inductance for 30% ripple current is:  1 1 
 + (350kHz) = 433mW
V  VOUT   5V − 2.3V 2.3V 
DIL = OUT 1− 
(f)(L)  VIN(NOMINAL)  A short-circuit to ground will result in a folded back
current of:
A 3.9µH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus 20 mV 1  95ns(22V) 
ISC = −   = 3.07A
one half the ripple current, or 6.88A. Increasing the ripple 0.006Ω 2  3.9µH 
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at with a typical value of RDS(ON) and z = (0.005/°C)(25°C)
maximum VIN: = 0.125. The resulting power dissipated in the bottom
MOSFET is:
VOUT 3.3V
tON(MIN) = = = 429ns PSYNC = (2.23A)2 (1.125)(0.022Ω) = 233mW
VIN(MAX)(f) 22V(350kHz)
which is less than under full-load conditions.
The RSENSE resistor value can be calculated by using the
minimum value for the maximum current sense threshold The input capacitor to the buck regulator CIN is chosen
(43mV): for an RMS current rating of at least 3A at temperature
assuming only this channel is on. COUT is chosen with an
43mV ESR of 0.02Ω for low output ripple. The output ripple in
RSENSE ≤ = 0.006Ω
6.88A continuous mode will be highest at the maximum input volt-
age. The output voltage ripple due to ESR is approximately:
Choosing 1% resistors: RA = 25k and RB = 80.6k yields
an output voltage of 3.33V. VORIPPLE = RESR (DIL) = 0.02Ω(1.75A) = 35mVP-P

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 LTC3859A
Applications Information
PC Board Layout Checklist
When laying out the printed circuit board, the following 4. Are the SENSE– and SENSE+ leads routed together with
checklist should be used to ensure proper operation of minimum PC trace spacing? The filter capacitor between
the IC. These items are also illustrated graphically in the SENSE+ and SENSE– should be as close as possible
layout diagram of Figure 11. Figure 12 illustrates the current to the IC. Ensure accurate current sensing with Kelvin
waveforms present in the various branches of the 2-phase connections at the sense resistor.
synchronous buck regulators operating in the continuous 5. Is the INTVCC decoupling capacitor connected close
mode. Check the following in your layout: to the IC, between the INTVCC and the power ground
1. Are the top N-channel MOSFETs MTOP1 and MTOP2 pins? This capacitor carries the MOSFET drivers’ cur-
located within 1cm of each other with a common drain rent peaks. An additional 1µF ceramic capacitor placed
connection at CIN? Do not attempt to split the input immediately next to the INTVCC and PGND pins can help
decoupling for the two channels as it can cause a large improve noise performance substantially.
resonant loop. 6. Keep the switching nodes (SW1, SW2, SW3), top gate
2. Are the signal and power grounds kept separate? The nodes (TG1, TG2, TG3), and boost nodes (BOOST1,
combined IC signal ground pin and the ground return BOOST2, BOOST3) away from sensitive small-signal
of CINTVCC must return to the combined COUT (–) ter- nodes, especially from the opposites channel’s voltage
minals. The path formed by the top N-channel MOSFET, and current sensing feedback pins. All of these nodes
Schottky diode and the CIN capacitor should have short have very large and fast moving signals and therefore
leads and PC trace lengths. The output capacitor (–) should be kept on the output side of the LTC3859A and
terminals should be connected as close as possible occupy minimum PC trace area.
to the (–) terminals of the input capacitor by placing 7. Use a modified star ground technique: a low impedance,
the capacitors next to each other and away from the large copper area central grounding point on the same
Schottky loop described above. side of the PC board as the input and output capacitors
3. Do the LTC3859A VFB pins’ resistive dividers connect to with tie-ins for the bottom of the INTVCC decoupling
the (+) terminals of COUT? The resistive divider must be capacitor, the bottom of the voltage feedback resistive
connected between the (+) terminal of COUT and signal divider and the SGND pin of the IC.
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).

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LTC3859A
Applications Information
PC Board Layout Debugging Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
Start with one controller on at a time. It is helpful to use
dervoltage lockout circuit by further lowering VIN while
a DC-50MHz current probe to monitor the current in the
monitoring the outputs to verify operation.
inductor while testing the circuit. Monitor the output switch-
ing node (SW pin) to synchronize the oscilloscope to the Investigate whether any problems exist only at higher out-
internal oscillator and probe the actual output voltage as put currents or only at higher input voltages. If problems
well. Check for proper performance over the operating coincide with high input voltages and low output currents,
voltage and current range expected in the application. look for capacitive coupling between the BOOST, SW, TG,
The frequency of operation should be maintained over the and possibly BG connections and the sensitive voltage
input voltage range down to dropout and until the output and current pins. The capacitor placed across the current
load drops below the low current operation threshold— sensing pins needs to be placed immediately adjacent to
typically 25% of the maximum designed current level in the pins of the IC. This capacitor helps to minimize the
Burst Mode operation. effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
The duty cycle percentage should be maintained from cycle
high current output loading at lower input voltages, look
to cycle in a well-designed, low noise PCB implementation.
for inductive coupling between CIN, Schottky and the top
Variation in the duty cycle at a subharmonic rate can sug-
MOSFET components to the sensitive current and voltage
gest noise pickup at the current or voltage sensing inputs
sensing traces. In addition, investigate common ground
or inadequate loop compensation. Overcompensation of
path voltage pickup between these components and the
the loop can be used to tame a poor PC layout if regulator
SGND pin of the IC.
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should An embarrassing problem, which can be missed in an
both controllers be turned on at the same time. A particularly otherwise properly working switching regulator, results
difficult region of operation is when one controller channel when the current sensing leads are hooked up backwards.
is nearing its current comparator trip point when the other The output voltage under this improper hookup will still
channel is turning on its top MOSFET. This occurs around be maintained but the advantages of current mode control
50% duty cycle on either channel due to the phasing of will not be realized. Compensation of the voltage loop will
the internal clocks and may cause minor duty cycle jitter. be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.

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 LTC3859A
Applications Information

SW1 L1 RSENSE1 VOUT1

D1 COUT1 RL1

VIN

RIN
CIN

SW2 L2 RSENSE2 VOUT2

BOLD LINES INDICATE D2 COUT2 RL2

HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.

3859A F11

Figure 11. Branch Current Waveforms for Bucks

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LTC3859A
Typical Applications
VOUT1
RA1 OPT RB1
68.1k 357k LTC3859A
VFB1 SENSE1–
CITH1A C1
100pF 1nF

CITH1 RITH1 SENSE1+

1500pF 15k 100k
ITH1 PGOOD1 C1
CSS1 10µF
MTOP1 L1 RSENSE1
0.1µF TG1 VOUT1
4.9µH 6mΩ
5V
TRACK/SS1 SW1 CB1 5A
0.1µF
FREQ BOOST1
COUT1
PLLIN/MODE BG1 MBOT1 220µF

SGND D1
RUN1 VBIAS
CBIAS
VOUT2 RUN2 10µF
RA2 10pF RB2 RUN3 PGND
68.1k 649k
VFB2
CITH2 CINT1
RITH2
2.2nF 4.7µF C2
15k
10µF
ITH2 INTVCC
CITH2A
68pF D2

CSS2 TG2 MTOP2 L2 RSENSE2

CB2
0.1µF 6.5µH 8mΩ VOUT2
0.1µF
TRACK/SS2 BOOST2 8.5V
3A
VOUT3 SW2
COUT2
RA3 OPT RB3 BG2 MBOT2 68µF
68.1k 499k
VFB3
CITH3
0.01µF RITH3 SENSE2+
3.6k
C2
CITH3A ITH3 1nF
820pF
SENSE2– VOUT3
10V*
CSS3 D3
0.1µF COUT3
SS3 TG3 MTOP3 L3 RSENSE2
1.2µH 220µF
2mΩ
SW3 VIN
CB3 2.5V TO 38V
OV3 0.1µF
BOOST3 (START-UP ABOVE 5V)
MTOP1, MTOP2: BSZ097NO4LS
MBOT1, MBOT2: BSZ097NO4LS VOUT1 CIN
EXTVCC BG3 MBOT3
MTOP3: BSC027NO4LS 220µF
MBOT3: BSCO1BN04LS SENSE3–
L1: WÜRTH 744314490
L2: WÜRTH 744314650 C3
L3: WÜRTH 744325120 1nF
COUT1: SANYO 6TPB220ML SENSE3+ * VOUT3 IS 10V WHEN VIN < 10V,
COUT2: SANYO 10TPC68M
FOLLOWS VIN WHEN VIN > 10V
CIN, COUT3: SANYO 50CE220LX 3859A F12

D1, D2: CMDH-4E

D3: BAS140W

Figure 12. High Efficiency Wide Input Range Dual 5V/8.5V Converter

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 LTC3859A
typical Applications
VOUT1
RA1 33pF RB1
34k 475k LTC3859A
VFB1 SENSE1–
CITH1A C1
100pF 1nF

CITH1 RITH1 SENSE1+

680pF 10k 100k
ITH1 PGOOD1 C1
CSS1 10µF
MTOP1 L1 RSENSE1
0.1µF TG1 VOUT1
8.8µH 9mΩ
12V
TRACK/SS1 SW1 CB1 3A
0.1µF
FREQ BOOST1
COUT1
PLLIN/MODE BG1 MBOT1 47µF

SGND D1
RUN1 VBIAS
CBIAS
VOUT2 RUN2 10µF
RA2 15pF RB2 RUN3 PGND
68.1k 215k
VFB2
CITH2 CINT1
820pF RITH2
4.7µF C2
15k
10µF
ITH2 INTVCC
CITH2A
150pF
D2
CSS2 TG2 MTOP2 L2 RSENSE2
CB2
0.1µF 3.2µH 6mΩ VOUT2
0.1µF
TRACK/SS2 BOOST2 3.3V
5A
VOUT3 SW2
COUT2
RA3 OPT RB3 BG2 MBOT2 150µF
68.1k 787k
VFB3
CITH3
RITH3 SENSE2+
0.01µF
3.6k
C2
ITH3 1nF
CITH3A
820pF SENSE2– VOUT3
15V*
CSS3 D3
0.1µF COUT3
SS3 TG3 MTOP3 L3 RSENSE2
1.2µH 220µF
100k 2mΩ
INTVCC OV3 SW3 VIN
CB3 2.5V TO 38V
BOOST3 0.1µF (START-UP ABOVE 5V)
MTOP1, MTOP2: VISHAY Si7848DP
MBOT1, MBOT2: VISHAY Si7848DP CIN
EXTVCC BG3 MBOT3
MTOP3: BSC027NO4LS 220µF
MBOT3: BSCO1BN04LS SENSE3–
L1: SUMIDA CDEP105-8R8M
L2: SUMIDA CDEP105-3R2M C3
L3: WÜRTH 744325120 1nF
COUT1: KEMET T525D476MO16E035 SENSE3+ * VOUT3 IS 15V WHEN VIN < 15V,
COUT2: SANYO 4TPE150M
FOLLOWS VIN WHEN VIN > 15V
CIN, COUT3: SANYO 50CE220LX 3859A F13

D1, D2: CMDH-4E

D3: BAS140W

Figure 13. High Efficiency Wide Input Range Dual 12V/3.3V Converter

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39
LTC3859A
typical Applications
VOUT1
RA1 56pF RB1
115k 28.7k LTC3859A
VFB1 SENSE1–
CITH1A C1
200pF 1nF

CITH1 RITH1 SENSE1+

1000pF 3.93k 100k
ITH1 PGOOD1 C1
CSS1 10µF
MTOP1 L1 RSENSE1
0.01µF TG1
0.47µH 3.5mΩ VOUT1
TRACK/SS1 SW1 1V
CB1 8A
0.1µF
FREQ BOOST1
COUT1
PLLIN/MODE BG1 MBOT1 220µF
×2
SGND D1
RUN1 VBIAS
CBIAS
VOUT2 RUN2 10µF
RA2 56pF RB2 RUN3 PGND
115k 57.6k
VFB2
CITH2 CINT1
RITH2
1000pF 4.7µF C2
3.93k
10µF
ITH2 INTVCC
CITH2A
200pF D2

TG2 MTOP2 L2 RSENSE2

CSS2 CB2
0.47µH 3.5mΩ VOUT2
0.01µF 0.1µF
TRACK/SS2 BOOST2 1.2V
8A
VOUT3 SW2
COUT2
RA3 OPT RB3 BG2 MBOT2 220µF
12.1k 232k ×2
VFB3
CITH3
RITH3 SENSE2+
15nF
8.66k
C2
CITH3A ITH3 1nF
220pF
SENSE2– VOUT3
24V
CSS3 D3 COUT3 5A
0.01µF L3 220µF
SS3 TG3 MTOP3 RSENSE2
3.3µH 4mΩ VIN
OV3 SW3
CB3 12V
BOOST3 0.1µF
MTOP1, MTOP2: RENESAS RJK0305 CIN
MBOT1, MBOT2: RENESAS RJK0328 220µF
EXTVCC BG3 MBOT3
MTOP3, MBOT3: RENESAS HAT2169H
L1, L2: SUMIDA CDEP105-0R4 SENSE3–
L3: PULSE PA1494.362NL
COUT1, COUT2: SANYO 2R5TPE220M C3
CIN, COUT3: SANYO 50CE220AX 1nF
D1, D2: CMDH-4E SENSE3+
D3: BAS140W
3859A F14

Figure 14. High Efficiency Triple 24V/1V/1.2V Converter from 12V VIN

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40
 LTC3859A
typical Applications
VOUT1
RA1 RB1
115k 57.6k LTC3859A
VFB1 SENSE1–
CITH1A C1
100pF 1nF

CITH1 RITH1 SENSE1+

2.2nF 5.6k 100k
ITH1 PGOOD1 C1
CSS1 10µF
MTOP1 L1 RSENSE1
0.1µF TG1
2.2µH 9mΩ VOUT1
TRACK/SS1 SW1 1.2V
CB1 3A
0.1µF
FREQ BOOST1
COUT1
PLLIN/MODE BG1 MBOT1 220µF

SGND D1
RUN1 VBIAS
CBIAS
VOUT2 RUN2 10µF
RA2 RB2 RUN3 PGND
115k 357k
VFB2
CITH2 CINT1
RITH2
3.3nF 4.7µF C2
9.1k
10µF
ITH2 INTVCC
CITH2A
100pF D2

CSS2 TG2 MTOP2 L2 RSENSE2

CB2 6.5µH
0.1µF 9mΩ VOUT2
0.1µF
TRACK/SS2 BOOST2 3.3V
3A
VOUT3 SW2
COUT2
RA3 RB3 BG2 MBOT2 220µF
115k 887k
VFB3
CITH3
RITH3 SENSE2+
100nF
13k
C2
ITH3 1nF
CITH3A
10pF SENSE2–
D3 VOUT3
CSS3 10.5V
0.1µF COUT3 1.2A
SS3 TG3 270µF
•

C3
OV3 SW3 10µF RSENSE2
50V 9mΩ VIN
EXTVCC BOOST3
•

MTOP1, MTOP2: BSZ097NO4LS

L3 5.8V TO 34V
MBOT1, MBOT2: BSZ097NO4LS CIN
MBOT3: BSZ097NO4L BG3 MBOT3 10µH
220µF
L1: WURTH 744311220
L2: WURTH 744314650 SENSE3–
L3: COOPER BUSSMANN DRQ125-100 C3
COUT1: SANYO 2R5TPE220MAFB 1nF
COUT2: SANYO 4TPE220MAZB SENSE3+
COUT3: SANYO SVPC270M
CIN: SANYO 50CE220LX 3859A F15

D1, D2: CMDH-4E

D3: DIODES INC B360A-13-F

Figure 15. High Efficiency 1.2V/3.3V Step-Down Converter with 10.5V SEPIC Converter

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LTC3859A
Package Description
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)

Exposed Pad Variation AA

4.75 REF 9.60 – 9.80*

(.378 – .386)
4.75 REF
(.187)
38 20

6.60 ±0.10
2.74 REF
4.50 REF
SEE NOTE 4 6.40
2.74
0.315 ±0.05 REF (.252)
(.108)
BSC
1.05 ±0.10

0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 19
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.50
0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.17 – 0.27
FE38 (AA) TSSOP REV C 0910
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN MILLIMETERS FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

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 LTC3859A
Package Description
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ± 0.05

5.50 ± 0.05
5.15 ± 0.05

4.10 ± 0.05

3.00 REF 3.15 ± 0.05

PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.5 REF
6.10 ± 0.05
7.50 ± 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH
R = 0.30 TYP OR
0.75 ± 0.05 3.00 REF 0.35 × 45° CHAMFER
5.00 ± 0.10
0.00 – 0.05 37 38

0.40 ±0.10
PIN 1
TOP MARK 1
(SEE NOTE 6)
2

5.15 ± 0.10
7.00 ± 0.10 5.50 REF

3.15 ± 0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ± 0.05 R = 0.125 R = 0.10

0.50 BSC TYP TYP
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
OUTLINE M0-220 VARIATION WHKD MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3859af

43
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3859A
Typical Application
High Efficiency Wide Input Range Dual 3.3V/8.5V Converter
VOUT1
RA1 15pF RB1
68.1k 215k LTC3859A
VFB1 SENSE1–
CITH1A C1
150pF 1nF

CITH1 RITH1 SENSE1+

820pF 15k 100k
ITH1 PGOOD1 C1
CSS1 10µF
MTOP1 L1 RSENSE1
0.1µF TG1
3.2µH 6mΩ VOUT1
TRACK/SS1 SW1 3.3V
CB1 5A
FREQ BOOST1 0.1µF
COUT1
PLLIN/MODE BG1 MBOT1 150µF

SGND D1
RUN1 VBIAS
CBIAS
VOUT2 RUN2 10µF
RA2 10pF RB2 RUN3 PGND
68.1k 649k
VFB2
CITH2 CINT1
2.2nF RITH2
4.7µF C2
15k
10µF
ITH2 INTVCC
CITH2A
68pF D2

TG2 MTOP2 L2 RSENSE2

CSS2 CB2
6.5µH 8mΩ VOUT2
0.1µF 0.1µF
TRACK/SS2 BOOST2 8.5V
3A
VOUT3 SW2
COUT2
RA3 OPT RB3 BG2 MBOT2 68µF
68.1k 499k
VFB3
CITH3
0.01µF RITH3 SENSE2+
3.6k
C2
CITH3A ITH3 1nF
820pF –
SENSE2 VOUT3
10V*
CSS3 D3
0.1µF L3 COUT3
SS3 TG3 MTOP3 RSENSE2
1.2µH 220µF
2mΩ
SW3 VIN
CB3 2.5V TO 38V
MTOP1, MTOP2: VISHAY Si7848DP BOOST3 0.1µF (START-UP ABOVE 5V)
OV3
MBOT1, MBOT2: BSZ097NO4LS
MTOP3: BSC027NO4LS VOUT2 EXTVCC BG3 MBOT3 CIN
MBOT3: BSCO1BN04LS 220µF
–
L1: SUMIDA CDEP105-3R2M SENSE3
L2: WÜRTH 744314650 C3
L3: WÜRTH 744325120 1nF
COUT1: SANYO 6TPB220ML
COUT2: SANYO 4TPE150M SENSE3+ * VOUT3 IS 10V WHEN VIN < 10V,
CIN, COUT3: SANYO 50CE220LX 3859A TA02
FOLLOWS VIN WHEN VIN > 10V
D1, D2: CMDH-4E
D3: BAS140W

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PART NUMBER DESCRIPTION COMMENTS
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LTC3890/LTC3890-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz,
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LTC3834/LTC3834-1 Low IQ, Synchronous Step-Down DC/DC Controller with Phase-Lockable Fixed Frequency 140kHz to 650kHz,
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with 99% Duty Cycle 0.8V ≤ VOUT ≤ 24V, TSSOP-20E, 3mm × 4mm QFN-20
LTC3824 Low IQ, High Voltage DC/DC Controller, 100% Duty Cycle Selectable Fixed 200kHz to 600kHz Operating Frequency,
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3859af

44 Linear Technology Corporation

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