Triple Differential Driver With Sync-On-Common-Mode AD8134

FEATURES
Triple high speed differential driver 225 MHz, 3 dB large signal bandwidth 450 MHz, 3 dB small signal bandwidth Easily drives 1.4 V p-p video signal into doubly terminated 100 UTP cable 1600 V/s slew rate Fixed internal gain of 2 Internal common-mode feedback network Output balance error 60 dB @ 50 MHz On-chip sync-on-common-mode circuitry Output pull-down feature for line isolation Differential input and output Differential-to-differential or single-ended-to-differential operation High isolation between amplifiers: 80 dB @ 10 MHz Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply, RL, dm = 200 Low offset: 3 mV typical output-referred on 5 V supply Low power: 26.5 mA @ 5 V for three drivers and sync circuitry Wide supply voltage range: +5 V to 5 V Available in space-saving packaging: 4 mm 4 mm LFCSP

FUNCTIONAL BLOCK DIAGRAM

VS (SYNC) HSYNC
19 18 17 2 16 15

24

23

22

+IN G

IN G

VS+

21

20

OPD 1 VS 2 IN R 3 +IN R 4 VS 5 OUT R 6

AD8134

VSYNC

SYNC LEVEL VS+ (SYNC) IN B +IN B VS OUT B

14 13

10

11

12

VS+

+OUT G

OUT G

+OUT R

VS+

+OUT B

Figure 1.
0 10 VOUT, dm = 2V p-p VOUT, cm/VOUT, dm VS = 5V 30 40 50 60 70 80 90 100 1 10 FREQUENCY (MHz) 100
04770-018

OUTPUT BALANCE ERROR (dB)

20

APPLICATIONS
Keyboard-video-mouse (KVM) networking

VS = +5V

GENERAL DESCRIPTION
The AD8134 is a major advancement beyond using discrete op amps for driving differential RGB signals over twisted pair cable. The AD8134 is a triple, low cost differential or singleended input to differential output driver, and each amplifier has a fixed gain of 2 to compensate for the attenuation of the line termination resistors. The AD8134 is specifically designed for RGB signals but can be used for any type of analog signals or high speed data transmission. The AD8134 is capable of driving either Category 5 (Cat-5) unshielded twisted pair (UTP) cable or differential printed circuit board transmission lines with minimal signal degradation. A unique feature that allows the user to transmit balanced horizontal and vertical video sync signals over the three common-mode channels with minimal electromagnetic interference (EMI) radiation is included on-chip. The outputs of the AD8134 can be set to a low voltage state that allows easy differential multiplexing of multiple drivers on the same twisted pair cable, when used with external series diodes.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

04770-001

500

Figure 2. Output Balance vs. Frequency

The AD8134 driver is a natural complement to the AD8143, AD8129, and AD8130 differential receivers. Manufactured on the Analog Devices next generation XFCB bipolar process, the AD8134 has a large signal bandwidth of 225 MHz and a slew rate of 1600 V/s. The AD8134 has an internal common-mode feedback feature that provides output gain and phase matching that is balanced to 60 dB at 50 MHz, suppressing harmonics and reducing radiated EMI. The AD8134 is available in a 24-lead LFCSP and can operate over the 40C to +85C extended industrial temperature range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved.

AD8134 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 12 Definition of Terms.................................................................... 12 Analyzing an Application Circuit............................................. 12 Closed-Loop Gain ...................................................................... 12 Calculating an Application Circuits Input Impedance ......... 13 Input Common-Mode Voltage Range in Single-Supply Applications................................................................................. 13 Driving a Capacitive Load......................................................... 13 Output Pull-Down (OPD) ........................................................ 13 Sync-On-Common-Mode......................................................... 14 Applications..................................................................................... 15 Driving RGB Video Over Cat-5 Cable .................................... 15 How to Apply the Output Pull-Down Feature ....................... 16 KVM Networks........................................................................... 16 Video Sync-On-Common-Mode ............................................. 16 Level-Shifting Sync Pulses on 5 V Supplies.......................... 17 Layout and Power Supply Decoupling Considerations......... 18 Amplifier-to-Amplifier Isolation ............................................. 18 Exposed Paddle (EP).................................................................. 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19

REVISION HISTORY
10/05Rev. Sp0 to Rev. A Changes to Features and General Description ............................. 1 Changes to Figure 32...................................................................... 14 Changes to Figure 33...................................................................... 15 Changes to Figure 34...................................................................... 17 Added Level-Shifting Sync Pulses on 5 V Supplies Section ... 17 Changes to Ordering Guide .......................................................... 19 7/04Revision Sp0: Initial Version

Rev. A | Page 2 of 20

AD8134 SPECIFICATIONS
VS = 5 V, HSYNC and VSYNC = VS, RL, dm = 200 @ 25C, unless otherwise noted. TMIN to TMAX = 40C to +85C. Table 1.
Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth 3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Isolation Between Amplifiers DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance DC CMRR DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain Output Voltage Swing Output Offset Voltage Output Offset Drift Output Balance Error Output Voltage Noise (RTO) Output Short-Circuit Current COMMON-MODE SYNC PERFORMANCE SYNC DYNAMIC PERFORMANCE Slew Rate HSYNC AND VSYNC INPUTS Input Low Voltage Input High Voltage SYNC LEVEL INPUT Input Voltage Range Setting to Achieve 0.5 V Pulse Levels Gain to Red Common-Mode Output Gain to Green Common-Mode Output Gain to Blue Common-Mode Output POWER SUPPLY Operating Range Quiescent Current PSRR OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage OPD Input High Voltage OPD Input Bias Current OPD Assert Time OPD De-Assert Time Output Voltage When OPD Asserted Conditions Min Typ Max Unit

VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VO = 2 V p-p VO = 2 V p-p, 25% to 75% VO = 2 V step f = 10 MHz, between Amplifier R and Amplifier G

450 225 60 55 1600 15 80

MHz MHz MHz MHz V/s ns dB

Differential Single-ended input Differential VOUT, dm/VIN, cm, VIN, cm = 1 V VOUT, dm/VIN, dm, VIN, dm = 1 V Each single-ended output TMIN to TMAX f = 50 MHz DC f = 1 MHz 1.920 VS + 1.9 24

5 to +5 1.5 1.13 1 48 1.955 +4 30 60 70 25 90 2.000 VS+ 1.6 +24

V k k pF dB V/V V mV V/C dB dB nV/Hz mA

54

VOUT, cm = 1 V to +1 V; 25% to 75%

1000 VS to 2.75 2.25 to VS+

V/s V V V V V/V V/V V/V V mA dB V V A ns ns V

For linear operation VO, cm/VSYNC LEVEL VO, cm/VSYNC LEVEL VO, cm/VSYNC LEVEL 0.95 1.91 0.95 +4.5 VOUT, dm/VS; VS = 1V 31 54 VS to VS+ 4.15 VS+ 3.15 to VS+ 67 100 100 VS + 0.86 VS + 0.5 1.02 2.04 1.02 1.07 2.14 1.07 6 33 48

90

Each output, OPD input @ VS+

Rev. A | Page 3 of 20

VS + 0.90

AD8134
VS+ = 5 V, VS = 0 V, HSYNC and VSYNC = VS, RL, dm = 200 @ 25C, unless otherwise noted. TMIN to TMAX = 40C to +85C. Table 2.
Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth 3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Isolation Between Amplifiers DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance DC CMRR DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain Output Voltage Swing Output Offset Voltage Output Offset Drift Output Balance Error Output Voltage Noise Output Short-Circuit Current COMMON-MODE SYNC PERFORMANCE SYNC DYNAMIC PERFORMANCE Slew Rate HSYNC AND VSYNC INPUTS Input Low Voltage Input High Voltage SYNC LEVEL INPUT Input Voltage Range Setting to Achieve 0.5 V Pulse Levels Gain to Red Common-Mode Output Gain to Green Common-Mode Output Gain to Blue Common-Mode Output POWER SUPPLY Operating Range Quiescent Current PSRR OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage OPD Input High Voltage OPD Input Bias Current OPD Assert Time OPD De-Assert Time Output Voltage When OPD Asserted Conditions Min Typ Max Unit

VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VO = 2 V p-p, 25% to 75% VO = 2 V step f = 10 MHz, between Amplifier R and Amplifier G

400 200 50 1400 14 75

MHz MHz MHz V/s ns dB

Differential Single-ended input Differential VOUT, dm/VIN, cm, VIN, cm = 1 V VOUT, dm/VIN, dm, VIN, dm = 1 V Each single-ended output TMIN to TMAX f = 50 MHz DC f = 1 MHz 1.920 VS + 1.25 24

0 to 5 1.5 1.13 1 48 1.955 3 30 60 70 25 90 2.000 VS+ 1.15 +24

V k k pF dB V/V V mV V/C dB dB nV/Hz mA

54

VOUT, cm = 1 V to +1 V; 25% to 75%

700 VS to 1.10 1.40 to VS+

V/s V V V V V/V V/V V/V V mA dB V V A ns ns V

For linear operation VO, cm/VSYNC LEVEL VO, cm/VSYNC LEVEL VO, cm/VSYNC LEVEL 0.97 1.94 0.96 +4.5 26.5 54 VS to VS+ 3.85 VS+ 2.85 to VS+ 63 100 100 VS + 0.79 VS + 0.5 1.02 2.03 1.02 1.06 2.10 1.05 6 27.5 48

80

Each output, OPD input @ VS+

VS + 0.82

Rev. A | Page 4 of 20

AD8134 ABSOLUTE MAXIMUM RATINGS

Table 3.
Parameter Supply Voltage HSYNC, VSYNC, Sync Level Power Dissipation Input Common-Mode Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 12 V VS See Figure 3 VS 65C to +125C 40C to +85C 300C 150C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and commonmode feedback loops. The internal resistor tap used in the common-mode feedback loop places a 4 k differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the JA. The exposed pad on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a PCB plane to achieve the specified JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 24-lead LFCSP (70C/W) on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a PCB plane. JA values are approximations.
4.0 3.5 3.0 2.5 2.0 LFCSP 1.5 1.0 0.5 0 40
04770-017

THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for the device soldered in a circuit board in still air. Table 4. Thermal Resistance with the Underside Pad Thermally Connected to a Copper Plane
Package Type/PCB Type 24-Lead LFCSP/4-Layer JA 70 Unit C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8134 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8134. Exceeding a junction temperature of 175C for an extended period can result in changes in the silicon devices potentially causing failure.

MAXIMUM POWER DISSIPATION (W)

20

0 20 40 AMBIENT TEMPERATURE (C)

60

80

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 5 of 20

AD8134 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VS (SYNC)
24 23 22 21 20 19 18 17 2 16 15

OPD 1 VS 2 IN R 3 +IN R 4 VS 5 OUT R 6

AD8134

HSYNC

+IN G

IN G

VS+

VSYNC

SYNC LEVEL VS+ (SYNC) IN B +IN B VS OUT B

14 13

10

11

12

VS+

+OUT G

OUT G

+OUT R

VS+

+OUT B

Figure 4. 24-Lead LFCSP

Table 5. Pin Function Descriptions

Pin No. 1 2, 5, 14, 21 3 4 6 7 8, 11, 17, 24 9 10 12 13 15 16 18 19 20 22 23 Mnemonic OPD VS IN R +IN R OUT R +OUT R VS+ +OUT G OUT G +OUT B OUT B +IN B IN B SYNC LEVEL HSYNC VSYNC +IN G IN G Description Output Pull Down. Negative Power Supply Voltage. Inverting Input, Red Amplifier. Noninverting Input, Red Amplifier. Negative Output, Red Amplifier. Positive Output, Red Amplifier. Positive Power Supply Voltage. Positive Output, Green Amplifier. Negative Output, Green Amplifier. Positive Output, Blue Amplifier. Negative Output, Blue Amplifier. Noninverting Input, Blue Amplifier. Inverting Input, Blue Amplifier. The voltage applied to this pin controls the amplitude of the sync pulses that are applied to the common-mode voltages. Horizontal Sync Pulse Input. Vertical Sync Pulse Input. Noninverting Input, Green Amplifier. Inverting Input, Green Amplifier.
+5V VS+ 0.1F ON ALL VS+ PINS

AD8134
50 750 1.5k

53.6 VTEST 53.6 TEST SIGNAL SOURCE 50 750 MIDSUPPLY

04770-001

RL, dm 200 VOUT, dm

1.5k VS 5V
04770-034

0.1F ON ALL VS PINS

Figure 5. Basic Test Circuit

Rev. A | Page 6 of 20

AD8134 TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, RL, dm = 200, TA = 25C, HSYNC and VSYNC = VS, unless otherwise noted.
9 40C +85C +25C 6 +85C 6 40C +25C 9

GAIN (dB)

GAIN (dB)

0
04770-019

0
04770-021

VOUT, dm = 200mV p-p 3 1 10 100 FREQUENCY (MHz)

VOUT, dm = 2V p-p 3 1 10 100 FREQUENCY (MHz)

1000

1000

Figure 6. Small Signal Frequency Response at Various Temperatures

9 VS = 5V 6 VS = +5V

Figure 9. Large Signal Frequency Response at Various Temperatures

6.9 6.8 6.7 6.6 VOUT, dm = 2V p-p

GAIN (dB)

GAIN (dB)

6.5 6.4 6.3 6.2 VOUT, dm = 200mV p-p

3
04770-020

6.1 VOUT, dm = 2V p-p 6.0 5.9 1 10 FREQUENCY (MHz) 100

04770-022

6 1 10 100 FREQUENCY (MHz)

1000

1000

Figure 7. Large Signal Frequency Response for Various Power Supplies

30 40 50 VS = +5V VOUT, dm = 2V p-p 30

Figure 10. 0.1 dB Flatness

VS = +5V VOUT, dm = 2V p-p 40

DISTORTION (dBc)

70 80 90 100 110
04770-023

DISTORTION (dBc)

60

50

RL, dm = 200

60 70

RL, dm = 200

RL, dm = 1000

80

RL, dm = 1000

120 130 0.1 1 10 FREQUENCY (MHz)

100

100 0.1

10 FREQUENCY (MHz)

100

Figure 8. Second Harmonic Distortion at VS = 5 V at Various Loads

Figure 11. Third Harmonic Distortion at VS = 5 V at Various Loads

Rev. A | Page 7 of 20

04770-024

90

AD8134
30 VOUT, dm = 2V p-p 40 50 40 50 30 VOUT, dm = 2V p-p

DISTORTION (dBc)

60 RL, dm = 200 70 80 90 100

04770-025

DISTORTION (dBc)

60 70 80 90 100

RL, dm = 200

RL, dm = 1000

RL, dm = 1000 110 120 130 0.1 1 10 FREQUENCY (MHz)

04770-026

110 120 0.1 1 10 FREQUENCY (MHz)

100

100

Figure 12. Second Harmonic Distortion at VS = 5 V at Various Loads

200 VS = +5V 100 VS = 5V 50 VOUT, dm = 200mV p-p

Figure 15. Third Harmonic Distortion at VS = 5 V at Various Loads

VS = +5V 1.0 VS = 5V 0.5 VOUT, dm = 2V p-p

VOUT, dm (mV)

VOUT, dm (V)

50

0.5

04770-009

5ns/DIV 200

5ns/DIV

Figure 13. Small Signal Transient Response for Various Power Supply Voltages
10 8 6 4 VOUT, dm 2 VIN, dm

Figure 16. Large Signal Transient Response for Various Power Supply Voltages

VIN, dm 250mV/DIV

VOLTAGE (V)

2 0 2 4 6

+0.1%

SETTLING TIME ERROR 2mV/DIV

0.1%

100ns/DIV 10

10ns/DIV

t=0
Figure 14. Overdrive Recovery Figure 17. Settling Time (0.1%)

Rev. A | Page 8 of 20

04770-012

04770-014

04770-008

100

1.0

AD8134
2 RL, dm = SINGLE-ENDED OUTPUT 30
VOUT, dm/VIN, cm VIN, cm = 200mV p-p

COMMON-MODE REJECTION (dB)

35

VS = +5V 40 VS = 5V

VOLTAGE (V)

1 OUTPUT PULL-DOWN

45 50 55

3 4 100ns/DIV 5

VOUTN
04770-013

VON

65 1 10 100 FREQUENCY (MHz)

1000

Figure 18. Output Pull-Down Response

1000

Figure 21. Common-Mode Rejection Ratio vs. Frequency

10 VOUT, dm/VS 0 10

NOISE (nVHz)

100

PSRR (dB)

20 30 40 50 PSRR+

04770-027

PSRR
04770-029

60 70 0.1

10 10

100

1k

10k 100k FREQUENCY (Hz)

1M

10M

100M

10 FREQUENCY (MHz)

100

1000

Figure 19. Output-Referred Voltage Noise vs. Frequency

0 10
VOUT, dm = 2V p-p VOUT, cm/VOUT, dm

Figure 22. Power Supply Rejection Ratio vs. Frequency

40 RED TO GREEN VOUT, dm G/VIN, dm R VIN, dm = 200mV p-p

50 VS = 5V

OUTPUT BALANCE ERROR (dB)

20 30 40 50 60 70 80 90 100 1 10 FREQUENCY (MHz) 100

04770-028 04770-011

60

ISOLATION (dB)

70

VIN, dm = 2V p-p

VS = +5V

80 90 100 110 1 10 100 FREQUENCY (MHz)

500

1000

Figure 20. Output Balance vs. Frequency

Figure 23. Amplifier-to-Amplifier Isolation vs. Frequency

Rev. A | Page 9 of 20

04770-015

60

AD8134
VOUT, dm/VIN, dm WITH

OUTPUT PULL-DOWN ISOLATION (dB)

32 34 36 38 40 42 44 46 48 50 0.1

OUTPUT PULL-DOWN

3.5 2.5 1.5 0.5 VS = +5V 0.5 1.5 2.5 3.5 4.5 100 1000 LOAD () 10000 VS = 5V 2 1 0 5 4 3

VIN = 2V p-p

+5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

+5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

30

4.5

10 FREQUENCY (MHz)

100

1000

04770-016

Figure 24. Output Pull-Down Isolation vs. Frequency

+5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)
4.0 1.0

Figure 27. Output Saturation Voltage vs. Output Load

1.5 RL, dm = 200 1.5 1.0

5V SINGLE-ENDED OUTPUT VOLTAGE (V)

3.5 VS = 5V 3.0

5V SINGLE-ENDED OUTPUT VOLTAGE (V)

VS = +5V

2.0

0.5

2.5

5.0

2.5

2.0 VS = +5V 1.5

4.5

4.0

3.0

VS = 5V

04770-031

1.0 40

25

15 35 TEMPERATURE (C)

55

75

3.5 85

3.5 40

25

15 35 TEMPERATURE (C)

55

75

85

Figure 25. Positive Output Saturation Voltage vs. Temperature

40 VS = 5V 35 30 25 20 15 10
04770-030

Figure 28. Negative Output Saturation Voltage vs. Temperature

SUPPLY CURRENT (mA)

VS = +5V

5 0 40 30

10

10 30 TEMPERATURE (C)

50

70

85

Figure 26. Power Supply Current vs. Temperature

Rev. A | Page 10 of 20

04770-032

04770-033

AD8134
3.5 VS = +5V 30

RED 3.0 25

BLUE 2.5 20

OUTPUT AMPLITUDE (V)

GREEN 2.0 15

1.5

10

VSYNC 1.0 5

0.5 HSYNC 5ns 0

Figure 29. Output Common-Mode Signals for Various Sync Pulse Inputs

Rev. A | Page 11 of 20

04770-010

SYNC AMPLITUDE (V)

AD8134 THEORY OF OPERATION

Each differential driver in the AD8134 differs from a conventional op amp in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The AD8134 drivers make it easy to perform single-ended-to-differential conversion, commonmode level-shifting, and amplification of differential signals. Previous differential drivers, both discrete and integrated designs, are based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. DC common-mode level-shifting has also been difficult with previous differential drivers. Level-shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes, the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. Excellent performance over a wide frequency range has proven difficult with this approach. Each of the AD8134 drivers uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set by the internal resistors, controls the differential output voltage only. The internal common-mode feedback loop controls the common-mode output voltage only. This architecture makes it easy to arbitrarily set the output common-mode level by simply applying a voltage to the VOCM input. The output commonmode voltage is forced, by internal common-mode feedback, to equal the voltage applied to the VOCM input, without affecting the differential output voltage. The VOCM inputs are not available to the user but are internally connected to the sync-on-commonmode circuitry. The AD8134 architecture results in outputs that are highly balanced over a wide frequency range without requiring external components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude that are exactly 180 apart in phase. Common-mode voltage refers to the average of two node voltages with respect to a common reference. The output common-mode voltage is defined as
VOUT , cm = (VOP + VON ) 2

Output Balance Output balance is a measure of how well the differential output signals are matched in amplitude and how close they are to exactly 180 apart in phase. Balance is easily determined by placing a well-matched resistor divider between the differential output voltage nodes and comparing the magnitude of the signal at the dividers midpoint with the magnitude of the differential signal. By this definition, output balance error is the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differentialmode voltage in response to a differential input signal
Output Balance Error = VOUT , cm VOUT , dm

ANALYZING AN APPLICATION CIRCUIT

The AD8134 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages to minimize the differential and common-mode input error voltages. The differential input error voltage is defined as the voltage between the differential inputs labeled VAP and VAN in Figure 30. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed.

CLOSED-LOOP GAIN
The differential mode gain of the circuit in Figure 30 can be described by
VOUT,dm R = F =2 VIN,dm RG

where RF = 1.5 k and RG = 750 nominally.

RF + VIP RG VAP RL, dm RG VAN RF VON VOUT, dm VOP

DEFINITION OF TERMS
Differential Voltage Differential voltage refers to the difference between two node voltages that are balanced with respect to each other. For example, in Figure 30, the output differential voltage (or equivalently output differential mode voltage) is defined as VOUT, dm = (VOP VON)

Figure 30. Circuit Definitions

Rev. A | Page 12 of 20

04770-005

VIN, dm VOCM VIN

AD8134
CALCULATING AN APPLICATION CIRCUITS INPUT IMPEDANCE
The effective input impedance of a circuit such as that in Figure 30 at VIP and VIN depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the differential input impedance, RIN, dm, between the inputs VIP and VIN is simply RIN,dm = 2 RG = 1.5 k In the case of a single-ended input signal (for example, if VIN is grounded and the input signal is applied to VIP), the input impedance becomes
RG = 1.125 k = RF 1 2 (RG + RF )

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output impedance of the AD8134 to reduce phase margin, resulting in high frequency ringing in the pulse response. The best way to minimize this effect is to place a small resistor in series with each of the amplifiers outputs to buffer the load capacitance.

OUTPUT PULL-DOWN (OPD)

The AD8134 has an OPD pin that when pulled high significantly reduces the power consumed while simultaneously pulling the outputs to within less than 1 V of VS when used with series diodes (see the Applications section). The equivalent schematic of the output in the output pull-down state is shown in Figure 31. (The ESD diodes shown in Figure 31 are for ESD protection and are distinct from the series diodes used with the output pull-down feature.) See Figure 18 and Figure 24 for the output pull-down transient and isolation performance. The threshold levels for the OPD input pin are referenced to the positive power supply and are listed in the Specifications tables. When the OPD pin is pulled high, the AD8134 enters the output pull-down state.
VCC ESD DIODE VOUT VS+

RIN

The circuits input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG.

INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONS

The inputs of the AD8134 are designed to facilitate levelshifting of ground referenced input signals on a single power supply. For a single-ended input, this would imply, for example, that the voltage at VIN in Figure 30 would be 0 V when the amplifiers negative power supply voltage was also set to 0 V. It is important to ensure that the common-mode voltage at the amplifier inputs, VAP and VAN, stays within its specified range. Since voltages VAP and VAN are driven to be essentially equal by negative feedback, the amplifiers input common-mode voltage can be expressed as a single term, VACM. VACM can be calculated as
VACM = VOCM + 2VICM 3
PULL-DOWN (OUTPUT IS PULLED DOWN WHEN SWITCH IS CLOSED)

ESD DIODE
04770-006

VS

Figure 31. Output Pull-Down Equivalent Circuit

where VICM is the common-mode voltage of the input signal, VIP + VIN . that is, VICM = 2

Rev. A | Page 13 of 20

AD8134
SYNC-ON-COMMON-MODE
The AD8134 drives RGB video signals over UTP cable. The balance of the differential outputs is trimmed to ensure low radiated energy from each of the twisted pairs. The commonmode outputs of each of the R, G, and B differential outputs are set using the circuit in Figure 32. This circuit embeds the horizontal and vertical sync pulses on the three common-mode outputs in a way that also results in low radiated energy. For a more detailed description of the sync scheme, see the Applications section. The sync-on-common-mode circuit generates a current based on the SYNC LEVEL input pin (Pin 18). With SYNC LEVEL input tied to VS, the common-mode output of all drivers is set at (VS+ + VS)/2. Using a resistor divider, a voltage can be applied between VS and SYNC LEVEL that determines the maximum deviation of the common-mode outputs from their midsupply level. If, for instance, SYNC LEVEL VS = 0.5 V and the supply voltage is 5 V, then the common-mode outputs fall within an envelope of 2.5 V 0.5 V. The state of each VOUT, cm output based on the HSYNC and VSYNC inputs is determined by the equations defined in the Applications section. On a single 5 V supply, the sync-on-common-mode circuit can be used by directly applying the HSYNC and VSYNC signals to the respective AD8134 inputs. The logic thresholds of the HSYNC and VSYNC inputs are nominally set at (VS+ VS)/4, using a resistor divider with an impedance of approximately 200 k. This allows the inputs to be driven beyond the rails without logic inversion and maintains fast switching speeds. The robustness of the HSYNC and VSYNC inputs therefore allows them to be driven directly off the output of a computer video card without concern of overdriving the inputs. The input path from HSYNC and VSYNC inputs to the switches in the current mode level-shifting circuit are well matched to eliminate false switching transients. This maximizes common-mode balance and minimizes radiated energy. The sync-on-common-mode circuit can be used with 5 V supplies, but in this case, the HSYNC and VSYNC logic signals require level-shifting. Level-shifting details are provided in the Applications section.

VS+ MIRROR

V VSYNC H HSYNC H V

RED VOCM GREEN VOCM BLUE VOCM

SYNC LEVEL

R VS

Figure 32. Sync-On-Common-Mode Simplified Circuit

Rev. A | Page 14 of 20

04770-007

MIRROR

AD8134 APPLICATIONS
DRIVING RGB VIDEO OVER CAT-5 CABLE
The AD8134 is a device whose foremost application is driving RGB video signals over UTP cable in KVM networks. Singleended video signals are easily converted to differential signals for transmission over the cable, and the internally fixed gain of 2 automatically compensates for the losses incurred by the source and load terminations. The AD8134 can be used in all of the typical KVM network topologies, including daisy-chained, star, and point-to-point. Figure 33 shows the AD8134 in a triple, single-ended-to-differential application in a daisychained network when driven from a 75 video source.

+5V VS+ 0.1F ON ALL VS+ PINS

AD8134
1.5k 75 RED VIDEO SOURCE 80.6 750 38.3 1.5k 1.5k 75 GREEN VIDEO SOURCE 80.6 750 38.3 1.5k 1.5k 75 BLUE VIDEO SOURCE 80.6 750 38.3 OUTPUT PULL-DOWN OPD VS 1.5k 750 B 750 G 750 R

49.9 UTP R 49.9

49.9 UTP G 49.9

49.9 UTP B 49.9

Figure 33. AD8134 in Single-Ended-to-Differential Application on Single 5 V Supply (Sync Pulse Encoding Not Shown)

Rev. A | Page 15 of 20

04770-002

AD8134
HOW TO APPLY THE OUTPUT PULL-DOWN FEATURE
The output pull-down feature, when used in conjunction with series Schottky diodes, offers a convenient means to connect a number of transmitters together to form a video network. The OPD pin is a binary input that controls the state of the AD8134 outputs. Its binary input level is referenced to the most positive power supply (see the Specifications section for the logic levels). When the OPD input is driven to its low state, the AD8134 output is enabled and operates in its normal fashion. In this state, the sync-on-common-mode circuitry provides a midsupply voltage and encoded sync pulses on the output common-mode voltage. The midsupply voltage is used to forward bias the series diodes, allowing the AD8134 to transmit signals over the network. When the OPD input is driven to its high state the outputs of the AD8134 are forced to a low voltage irrespective of the levels on the sync inputs. This reverse-biases the series diodes and presents a high impedance to the network. This feature allows a three-state output to be realized that maintains its high impedance state even when the AD8134 is not powered. This condition can occur in KVM networks where the AD8134s do not all reside in the same module, and where some modules in the network are not powered. It is recommended that the output pull-down feature only be used in conjunction with series diodes in such a way as to ensure that the diodes are reverse-biased when the output pulldown feature is asserted because some loading conditions can prevent the output voltage from being pulled all the way down. termination resistor into two 50 resistors in series. The diode currents are routed from the tap between the 50 resistors back to the respective transmitters over one of the wires of the fourth twisted pair in the UTP cable. Series resistors in the common-mode path are generally required to set the desired diode current. In point-to-point networks, there is one transmitter and one receiver per cable, and the switching is generally implemented with a crosspoint switch. In this case, there is no need to use diodes or the output pull-down feature. Diode and crosspoint switching are by no means the only type of switching that can be used with the AD8134. Many other types of mechanical, electromechanical, and electronic switches can be used.

VIDEO SYNC-ON-COMMON-MODE
In computer video applications, the horizontal and vertical sync signals are often separate from the video information signals. For example, in typical computer monitor applications, the red, green, and blue (RGB) color signals are transmitted over separate cables, as are the vertical and horizontal sync signals. When transmitting these types of video signals over long distances on UTP cable, it is desirable to reduce the required number of physical channels. One way to do this is to encode the vertical and horizontal sync signals as weighted sums and differences of the output common-mode signals. The RGB color signals are each transmitted differentially over separate physical channels. The fact that the differential and common-mode signals are orthogonal allows the RGB color and sync signals to be separated at the channels receiver. Cat-5 cable contains four balanced twisted-pair physical channels that can support both differential and common-mode signals. Transmitting typical computer monitor video over this cable can be accomplished by using three of the twisted pairs for the RGB and sync signals and one wire of the fourth pair as a return path for the Schottky diode bias currents. Each color is transmitted differentially, one on each of the three pairs, and the encoded sync signals are transmitted among the commonmode signals of each of the three pairs. To minimize EMI from the sync signals, the common-mode signals on each of the three pairs produced by the sync encoding scheme induce electric and magnetic fields that for the most part cancel each other. A conceptual block diagram of the sync encoding scheme is presented in Figure 34. Since the AD8134 has the sync encoding scheme implemented internally, the user simply applies the horizontal and vertical sync signals to the appropriate inputs. (See the Specifications tables for the definitions of the high and low levels of the horizontal and vertical sync pulse voltages).

KVM NETWORKS
In daisy-chained KVM networks, the drivers are distributed along one cable and a triple receiver is located at one end. Schottky diodes in series with the driver outputs are biased such that the one driver that is transmitting video signals has its diodes forwardbiased and the disabled drivers have their diodes reverse-biased. The output common-mode voltage, set by the sync-on-commonmode circuitry, supplies the forward-biased voltage. When the output pull-down feature is asserted, the differential outputs are pulled to a low voltage, reverse-biasing the diodes. In star networks, all cables radiate out from a central hub, which contains a triple receiver. The series diodes are all located at the receiver in the star network. Only one ray of the star is transmitting at a given time, and all others are isolated by reverse-biased diodes. Diode biasing is controlled in the same way as in the daisy-chained network. In the daisy-chained and star networks that use diodes for isolation, return paths are required for the common-mode currents that flow through the series diodes. A common-mode tap can be implemented at each receiver by splitting the 100

Rev. A | Page 16 of 20

AD8134
3.1

AD8134
750 +IN R 750 IN R VSYNC

1.5k

3.0 G
OUT R VOCM R +OUT R 1.5k

2.9 2.8 2.7 2.6 2.5 R 2.4

HSYNC SYNC LEVEL 750 +IN G

2

2.3
1.5k

2.2 2.1
OUT G

2.0 5.0 4.5 4.0

IN G

750

VOCM G +OUT G 1.5k 1.5k

3.5
750 +IN B 750 IN B 1.5k VOCM B +OUT B OUT B

3.0 2.5 2.0 1.5 HSYNC VSYNC

OPD

1.0
VOCM WEIGHTING EQUATIONS: RED VOCM = K(VSYNC HSYNC) + VMIDSUPPLY 2 GREEN VOCM = K(2VSYNC) + VMIDSUPPLY 2 BLUE VOCM = K(VSYNC + HSYNC) + VMIDSUPPLY 2

0.5
04770-003

0 0.98

0.99

1.00

1.01

1.02 1.03 TIME (s)

1.04

1.05

1.06

1.07

Figure 34. AD8134 Sync-On-Common-Mode Encoding Scheme

Figure 35. AD8134 Sync-On-Common-Mode Signals in Single 5 V Application

6.04k

VS

Figure 35 shows how the sync signals appear on each commonmode voltage in a single 5 V supply application when the voltage applied to the SYNC LEVEL input is 500 mV. A typical setting for the SYNC LEVEL voltage is 500 mV above the negative supply.

Figure 36. Level-Shifting Sync Pulses on 5 V Supplies

Rev. A | Page 17 of 20

04770-035

The transmitted common-mode sync signal magnitudes are scaled by applying a dc voltage to the SYNC LEVEL input, referenced to the negative supply. The difference between the voltage applied to the SYNC LEVEL input and the negative supply sets the peak deviation of the encoded sync signals about the midsupply common-mode voltage. For example, with the SYNC LEVEL input set at VS + 500 mV, the deviation of the encoded sync pulses about the nominal midsupply commonmode voltage is typically 500 mV. The equations in Figure 34 describe how the VSYNC and HSYNC signals are encoded on each colors midsupply common-mode signal. In these equations, the weights of the VSYNC and HSYNC signals are 1 (+1 for high, 1 for low), and the constant K is equal to the peak deviation of the encoded sync signals.

LEVEL-SHIFTING SYNC PULSES ON 5 V SUPPLIES

The vertical and horizontal sync pulses received from a computer video port are generally referenced to ground. When using 5 V supplies, these pulses must be level-shifted before being applied to the negative-supply referenced VSYNC and HSYNC inputs because these inputs are referenced to the negative supply. The circuit shown in Figure 36 provides the proper sync pulse level-shifting for a negative supply voltage of 5 V. The vertical and horizontal sync pulses each require a level-shift circuit.
GROUND-REFERENCED SYNC PULSE 1k 2N3906 LEVEL-SHIFTED SYNC PULSE 2.21k TO AD8134

04770-004

AD8134
LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to when designing with the AD8134. A solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling.

EXPOSED PADDLE (EP)

The 24-lead LFCSP package has an exposed paddle on the underside of its body. To achieve the specified thermal resistance, it must have a good thermal connection to one of the PCB planes. The exposed paddle must be soldered to a pad on top of the board that is connected to an inner plane with several thermal vias.

AMPLIFIER-TO-AMPLIFIER ISOLATION
The least amount of isolation between the three amplifiers exists between Amplifier R and Amplifier G. This is therefore viewed as the worst-case isolation and is what is reflected in the Specifications tables and Typical Performance Characteristics. Refer to the basic test circuit in Figure 5 for test conditions.

Rev. A | Page 18 of 20

AD8134 OUTLINE DIMENSIONS

4.00 BSC SQ 0.60 MAX 0.60 MAX
19 18 EXPOSED PA D
(BO TTOMVIEW)

PIN 1 INDICATOR
24 1

PIN 1 INDICATOR

TOP VIEW

3.75 BSC SQ

0.50 BSC 0.50 0.40 0.30

*2.45 2.30 SQ 2.15

6

13 12

0.23 MIN 2.50 REF

1.00 0.85 0.80

12 MAX

0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08

SEATING PLANE

*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION

Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters

ORDERING GUIDE
Model AD8134ACP-R2 AD8134ACP-REEL AD8134ACP-REEL7 AD8134ACPZ-R2 1 AD8134ACPZ-REEL1 AD8134ACPZ-REEL71
1

Temperature Package 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C

Package Description 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ

Package Outline CP-24-2 CP-24-2 CP-24-2 CP-24-2 CP-24-2 CP-24-2

Z = Pb-free part.

Rev. A | Page 19 of 20

AD8134 NOTES

2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04770-0-10/05(A)
T T

Rev. A | Page 20 of 20