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Interface Codes

The document contains Verilog code for a simple 4-bit adder module and its corresponding testbench. It includes an interface for signal communication and a driver class that triggers the addition operation on the rising edge of a clock signal. The testbench initializes the clock and runs the driver to simulate the adder's functionality, outputting results to a dump file.

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Vinay A J
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7 views3 pages

Interface Codes

The document contains Verilog code for a simple 4-bit adder module and its corresponding testbench. It includes an interface for signal communication and a driver class that triggers the addition operation on the rising edge of a clock signal. The testbench initializes the clock and runs the driver to simulate the adder's functionality, outputting results to a dump file.

Uploaded by

Vinay A J
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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module add

(
input [3:0] a,b,
output reg [4:0] sum,
input clk
);

always@(posedge clk)
begin
sum <= a + b;
end

endmodule

/////////////////////////Testbench Code

interface add_if;
logic [3:0] a;
logic [3:0] b;
logic [4:0] sum;
logic clk;
endinterface

class driver;

virtual add_if aif;

task run();
forever begin
@(posedge aif.clk);
aif.a <= 2;
aif.b <= 3;
$display("[DRV] : Interface Trigger");
end
endtask

endclass

module tb;

add_if aif();
driver drv;

add dut (aif.a, aif.b, aif.sum, aif.clk );

initial begin
aif.clk <= 0;
end
always #10 aif.clk <= ~aif.clk;

initial begin
drv = new();
drv.aif = aif;
drv.run();

end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
#100;
$finish();
end

endmodule

with modport
///////////////////////////Design

module add
(
input [3:0] a,b,
output reg [4:0] sum,
input clk
);

always@(posedge clk)
begin
sum <= a + b;
end

endmodule

//////////////////////////////////Testbench

interface add_if;
logic [3:0] a;
logic [3:0] b;
logic [4:0] sum;
logic clk;

modport DRV (outpu a,b,clk input sum);


endinterface

class driver;

virtual add_if.DRV aif;

task run();
forever begin
@(posedge aif.clk);
aif.a <= 2;
aif.b <= 3;
$display("[DRV] : Interface Trigger");
end
endtask

endclass

module tb;

add_if aif();
driver drv;

add dut (aif.a, aif.b, aif.sum, aif.clk );

initial begin
aif.clk <= 0;
end

always #10 aif.clk <= ~aif.clk;

initial begin
drv = new();
drv.aif = aif;
drv.run();

end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
#100;
$finish();
end

endmodule

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