Module 5

MOORE’S LAW
➢ No. of transistors on a chip doubled every 18 to 24 months.
➢ Semiconductor technology will double its effectiveness every 18 months.
 Scaling of MOSFET
➢ Scaling of MOSFET means shrink the size of the MOSFET device.

➢ Lateral dimensions such as the channel length and width of the channel reduced by
a factor of k

➢ Scaling down of MOSFET has a multitude of benefits.

1. Improvement in packing density
2. Speed of device
3. Reduce Power consumption

➢ Disadvantage :
Electric fields within the Gate Oxide grow larger.
 Scaling of MOSFET
➢ Proper scaling of MOSFET however requires not only a size reduction of the gate length
and width but also requires a reduction of all other dimensions including the gate/source
and gate/drain alignment, the oxide thickness and the depletion layer widths.

➢ Scaling of the depletion layer widths also implies scaling of the substrate doping density.
 Types of Scaling

➢ Two types of scaling are common:

1) Constant field scaling

2) Constant voltage scaling.

CONSTANT VOLTAGE SCALING

➢ In this method the device dimensions (both horizontal and vertical) are scaled by k, however,
the operating voltages remain constant.

➢ Electric field within the device will increase (field =Voltage/distance)

➢ Threshold voltages remain constant and the power per transistor will increase by k.
 FULL-SCALING (CONSTANT-FIELD SCALING)

➢ In this method the device dimensions (both horizontal and vertical) are scaled down by
1/k, where k is the scaling factor.

➢ In order to keep the electric field constant within the device, the voltages have to be
scaled also by 1/k such that the ratio between voltage and distance (which represents
the electric field) remain constant.

➢ The threshold voltage is also scaled down by the same factor as the voltage to preserve
the functionality of the circuits and the noise margins relative to one another.
 CONSTANT VOLTAGE SCALING
➢ The power density per unit area will increase by k3! This means that for the
same chip area, the chip power will increase by k3.
➢ The device doping has to be increased more aggressively (by k2) to prevent
channel punch through.
➢ By increasing the doping by k2, the depletion region thickness is reduced by k (the
same ratio as the channel length).
➢ However, there is a limit for how much the doping can be increased (the solid
solubility limit of the dopant in Silicon).
 FULL-SCALING (CONSTANT-FIELD SCALING)

➢ As a result of the scaling the currents will be reduced and hence the total power per
transistor (P=IxV) will also be reduced;

➢ However the power density will remain constant since the number of transistors per
unit area will increase.

➢ This means that the total power will remain constant if the chip size remains the
same.
 Short channel effects

1. Channel length modulation

➢ The channel is pinched off at the drain end for drain voltage equal to

➢ The inversion layer charge at the drain end becomes zero.

➢ If the drain-to-source voltage VDS is increased even further beyond the saturation edge so
that VDS > VDSAT, an even larger portion of the channel becomes pinched-off.

➢ The effective channel length (the length of the inversion layer) is reduced to

➢ Where L is the length of the channel segment with Qi = 0.

➢ Hence, the pinch off point moves from the drain end of the channel toward the source with
increasing drain-to-source voltages.

➢ The remaining portion of the channel between the pinch-off point and the drain will be in
depletion mode.

➢ Since Qi(y) = 0 for L'< y < L, the channel voltage at the pinch-off point remains equal to
VDSAT
➢ The channel current

➢ The above equation accounts for the actual shortening of the channel, also called channel
length modulation.

➢ Since L'< L, the saturation current calculated by using above equation will be larger than that
found by using normal equation with out channel length modulation under the same bias
conditions.
➢ We will use the following empirical relation between L and the drain-to-source
voltage instead.

➢ Here, is an empirical model parameter, and is called the channel length modulation
coefficient.

➢ Assuming that VDS << 1, the saturation current can now be written as:
 2. Drain- Induced Barrier Lowering

➢ For small channel length MOSFETs, there can be unintended electrostatic interactions between
the source and the drain known as Drain- Induced Barrier Lowering (DIBL).

Drain-​induced barrier lowering in MOSFETs . Cross sections and potential distribution along the channel
for a long channel and short channel MOSFET.
➢ As the drain bias is increased(reverse bias increases), the conduction band edge in the drain is
pulled down, and the drain-channel depletion width expands.

➢ For a long channel MOSFET as the distance between the drain and source is large, the drain
bias does not affect the source- to- channel potential barrier, which corresponds to the built-in
potential of the source- channel p-n junction.

➢ For a short channel MOSFET, as the drain bias is raised and the conduction band edge in the
drain is pulled down (with a increase of the drain depletion width), the source-channel
potential barrier is lowered due to DIBL.

➢ The onset of DIBL is sometimes considered to correspond to the drain depletion region
expanding and merging with the source depletion region, and causing punch- through
breakdown between source and drain.

➢ Once the source-channel barrier is lowered by DIBL, there can be significant drain leakage
current, with the gate being unable to shut it off.
Methods to overcome DIBL

1. The source/drain junctions must be made sufficiently shallow (i.e., scaled properly) as the
channel lengths are reduced, to prevent DIBL.

2. Secondly, the channel doping must be made sufficiently high to prevent the drain from
being able to control the source junction.
 3. Hot Carrier Effects.
➢ When an electron travels from the source to the drain along the channel, it gains kinetic energy at
the expense of electrostatic potential energy in the pinch-off region, and becomes a “hot”
electron.

➢ At the conduction band edge, the electron has potential energy only; as it gains more kinetic
energy, it moves higher up in the conduction band.

➢ A few of the electrons can become energetic enough to surmount the 3.1-eV potential barrier
between the Si channel and the gate oxide and go through the gate oxide and be collected as gate
current, thereby reducing the input impedance.

➢ More importantly, some of these electrons can be trapped in the gate oxide as fixed oxide
charges. this increases the flat band voltage, and therefore the VT.
Hot carrier generation (electron–hole pair creation) in the pinch-​off region
 ➢ In addition, these energetic hot carriers can rupture Si–H bonds that exist at the Si-SiO2
interface, creating fast interface states that degrade MOSFET parameters such as
transconductance and subthreshold slope, with stress.

➢ The solution to this problem is to use what is known as a lightly doped drain (LDD).

➢ By reducing the doping concentration in the source/drain, the depletion width at the reverse-
biased drain-channel junction is increased and the electric field is reduced.

Hot carrier effects are less problematic in P-channel MOSFET. Because

1. In P-channel MOSFET, hole act as the carrier, mobility of hole is approximately half that of the
electron, so for the same EF there are fewer hot holes than electrons

2. Barrier of hole injection form semiconductor channel to oxide (Si to SiO2) is high compared to
electron injection barrier between semiconductor to oxide.
 4. VELOCITY SATURATION

➢ In Short channel MOSFET Drain current may saturate at lower value of VDsat , due to High
electric field in channel

➢ Electric field in channel for given VDS become very large for short channel device. Mobility
of carrier saturated for high Electric Field
➢ For short channel MOSFET this EF is very high and velocity of carriers saturate for low
value of VDS and Drain current become saturate before VDSat

➢ Any further increment increase of VDS , mobility of carrier decreases and velocity of carrier
remain same and Drain current remain same.

➢ This effect in Short channel effect is called Velocity Saturation

Here the device gets
saturated much before
normal saturation values
thereby reducing the
saturation current
 VELOCITY SATURATION
Effects of velocity saturation

1. IDsat for the given VGS reduces significantly

2. The current in saturation region mainly depends on VDS in contrast to the square law
model.
 SUB-THRESHOLD CONDUCTION

➢ If we look at the drain current expression it appears that the current abruptly goes to zero as
soon as VG is reduced to VT.

➢ In reality, there is still some drain conduction below threshold, and this is known as
subthreshold conduction.

➢ This current is due to weak inversion in the channel between flat band and threshold which
leads to a diffusion current from source to drain.

➢ The drain current in the subthreshold region is equal to

➢ It can be seen that ID depends exponentially on gate bias, VG. However, VD has little influence
once VD exceeds a few kT>q.

➢ .
➢ ln ID as a function of gate bias VG plot, we should get a linear behavior in the subthreshold
regime.

➢ The slope of this line (or more precisely the reciprocal of the slope) is known as the
subthreshold slope, S, which has typical values of 70 mV/decade at room temperature for
MOSFETs.

➢ This means that a change in the input VG of 70 mV will change the output ID by an order of
magnitude.

➢ Clearly, the smaller the value of S, the better the transistor is as a switch. A small value of S
means a small change in the input bias can modulate the output current considerably
➢ For a very small gate voltage, the subthreshold current is reduced to the leakage current of the
source/drain junctions.

➢ This determines the off- state leakage current, and therefore the standby power dissipation in many
complementary MOS (CMOS) circuits

➢ From the subthreshold characteristics, it can be seen that if the VT of a MOSFET is too low, it
cannot be turned off fully at VG = 0.

➢ Also, unavoidable statistical variations of VT cause drastic variations of the subthreshold leakage
current.
 Substrate Bias Effects—the “Body” Effect
➢ With a reverse bias between the substrate and the source, the source- channel junction
potential barrier is increased.

➢ Clearly, the gate must be biased more positively than for the grounded substrate, to lower the
source-channel potential barrier sufficiently to create an inversion layer.

➢ This causes the threshold voltage to increase with (reverse) substrate bias—this is known as
the body effect.

➢ The depletion region in the channel is widened and the threshold gate voltage required to
achieve inversion must be increased to accommodate the larger Q’d.
➢ The change in threshold voltage due to the substrate bias is