Application Guide Volume III AG2016-02

Testing the Directional Negative-Sequence and

Phase Overcurrent Elements in the SEL-751
Using Directional Element Control
Deepak John

INTRODUCTION
This application guide describes the directional elements in the SEL-751 Feeder Protection Relay,
focusing on how they control the negative-sequence and the phase instantaneous overcurrent
elements. It also discusses how to test these elements.

BACKGROUND
Before testing the directional control, it is highly recommended that you test the logic of the
instantaneous overcurrent elements (without directional control) shown in Figure 1. Doing so will
help you take note of the differences in the logic and the output Relay Word bits when the same
elements incorporate directional control using the setting EDIR (setting EDIR to Y or AUTO
enables directional control).
50PnP
50PnD
50PnP –
50PnT
|IP| + 0
50PnTC 50QnP
50QnD
50QnP –
50QnT
|3I2| + 0
50QnTC

Figure 1 Negative-Sequence and Phase Instantaneous/Definite-Time Overcurrent Logic When EDIR = N or

the Directional Control Option Is Not Included
Note that n = 1–4 in 50PnP and 50QnP. These numbers are the various levels of overcurrent
elements.

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Figure 2 shows the combination of directional control input and the SELOGIC® control equation
for torque control using an AND gate and the supervision of the overcurrent elements. It is
important to note that the output Relay Word bits in this case are now 67PnP, 67PnT, 67QnP, and
67QnT. The 50PnP, 50PnT, 50QnP, 50QnT, 50GnP, and 50GnT are nonfunctional when
EDIR = Y or AUTO.
67PnP
50PnD
50PnP –
67PnT
|IP| + 0
50PnTC
PnDIR 67QnP
50QnD
50QnP –
67QnT
|3I2| + 0
50QnTC
QnDIR

Figure 2 Phase- and Negative-Sequence Instantaneous/Definite-Time Overcurrent Logic

When EDIR = Y or AUTO
For testing directional control, set all of the torque control Relay Word bits (50PnTC and
50QnTC) to 1 (the default setting that enables the element).
This guide first discusses the negative-sequence directional overcurrent element and,
subsequently, the phase directional overcurrent element.

NEGATIVE-SEQUENCE DIRECTIONAL OVERCURRENT ELEMENT

The principle of the negative-sequence directional overcurrent element is considerably different
from the traditional principle of torque calculation using the magnitudes and angles of a
polarizing quantity (typically voltage) and an operating quantity (typically current). The SEL-751
calculates the negative-sequence impedance based on negative-sequence voltage and current and
uses the calculated impedance to determine directionality. Because the aim of this guide is to
assist you in testing, it does not focus on the principle in detail but rather recommends that you
review [1] and [2], which are two documents that discuss this principle in detail.

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Testing the Logic Stages

The logic flow of the negative-sequence directional overcurrent element control is best
understood by recognizing the various stages involved, shown in Figure 3, and testing the stages
one by one.
Relay Relay Relay Direction
Word Word Directional Word Forward/
Internal Bit Directional Bit Element Bit Reverse Directional
Enables Outputs Elements Outputs Routing Outputs Logic Control

Level 1
50QF/
50QR Negative- FDIRQ/ DIRQF/
Sequence RDIRQ DIRQR To Negative-Sequence
1 Voltage- 3 4 Instantaneous/Definite-
DIRQE Level 2 Time Overcurrent
Polarized
2 Level 3 Elements
Level 4

Figure 3 Logic Stages of the Negative-Sequence Directional Overcurrent Element

The logic is divided into four stages, which are discussed in the following subsections. The
settings, input Relay Word bits, output Relay Word bits, and the procedure to test the logic are
discussed for each stage.

Internal Enables
In this stage, the relay looks for the presence of negative-sequence current, I2 (see Figure 4). It
also looks for the absence of a loss-of-potential (LOP) bit (voltage-polarized directional elements
are unreliable during an LOP event) and checks that I2/I1 > a2 (where I2/I1 is the ratio of
negative-sequence current to positive-sequence current and a2 is a restraining factor of typically
10 percent) to make sure that the condition is not a load unbalance.
Relay
Word Bit
|3I2| Outputs
Settings +
50QF
50QFP –

+
50QR
50QRP –

Relay
Word Bit
LOP DIRQE
(internal enable)
|I2| +

a2 • |I1| –

Setting VNOM = OFF

Figure 4 Internal Enable Logic for Negative-Sequence Directional Element

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Test Settings and Targets

To test the Internal Enables logic stage, enter the following settings:
EDIR = Y (enables directional control)
50QFP = 0.5 (the threshold of negative-sequence current that must be present during a
forward fault for the element to activate)
50QRP = 0.25 (the threshold of negative-sequence current that must be present during a
reverse fault for the element to activate)
a2 = 0.10
VNOM = 120 (nominal secondary voltage)
The targets for this test are as follows:
50QF (indicates that the negative-sequence current is above the 50QFP threshold)
50QR (indicates that the negative-sequence current is above the 50QRP threshold)
DIRQE (indicates that the negative-sequence directional element is enabled)

Test Procedure
Step 1. Apply balanced three-phase voltages and make sure that LOP is deasserted.
Step 2. Apply IA at 0.1 amperes and observe that 50QF and 50QR are de-asserted.
Leaving IB and IC at 0 amperes causes 3I2 to equal IA.
Step 3. Ramp up current and observe that DIRQE and 50QR assert when 50QRP is
0.25 amperes (±3 percent and ±0.02 • Inom) and 50QF asserts when 50QFP is
0.50 amperes (±3 percent and ±0.02 • Inom, with an Inom of 1 ampere or
5 amperes, depending on the relay part number).

Directional Elements
In this stage, the directional determination is based on the negative-sequence impedance
calculation (Z2) to determine if the fault is forward or reverse, as shown in Figure 5. Note that a
positive Z2 indicates a reverse fault and a negative Z2 indicates a forward fault. For a detailed
explanation, refer to [1] and [2].
Relay
Word Bit
50QF
Relay
Forward Word Bits
+
Threshold FDIRQ
–
Relay (forward)
Word Bits
DIRQE
Enable

Re  V 2 • (I2 • 1∠Z1ANG ) 
*
V2
Z2 =  
2
I2 I2 +
Reverse RDIRQ
–
Threshold (reverse)
Relay
Word Bit
50QR

Figure 5 Negative-Sequence Voltage-Polarized Directional Check

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Test Settings and Targets

Enter the following settings in addition to the previously described settings:
Z1MAG = 2.14 (positive-sequence line impedance in secondary ohms)
Z1ANG = 68.86 (positive-sequence line angle in secondary ohms)
Z2F = 1.07 (negative-sequence impedance threshold for forward fault)
Z2R = 1.27 (negative-sequence impedance threshold for reverse fault)
The targets are as follows:
FDIRQ (indicates a forward fault).
RDIRQ (indicates a reverse fault).

Test Procedure
Step 1. Start with the currents and voltages at the values from the end of the previous test
(Step 3 of the Internal Enable Logic Test Procedure). Set the A-phase current angle
to 111.14 degrees, and leave the magnitude unchanged from the previous test. This
will start the test in reverse direction. Double-check to make sure that 50QF, 50QR,
and DIRQE are all asserted.
Step 2. Drop the A-phase voltage to 58 volts and subsequently to 48 volts. This provides a
negative-sequence voltage (3V2) of 19∠180 volts. (This is done in two successive
steps to prevent LOP from picking up and de-asserting DIRQE.)
Step 3. Increase A-phase current (3I2) and verify that RDIRQ de-asserts at approximately
14.51∠111.14 amperes. RDIRQ de-asserts because the calculated Z2R has crossed
the reverse threshold shown in Figure 6.
X2
Reverse Threshold Z2 Plane

R2

Forward Threshold

Directional Element Characteristics

Forward Threshold
V2
If Z2F Setting ≤ 0, Forward Threshold = 0.75 • Z2F – 0.25 •
I2
V2
If Z2F Setting > 0, Forward Threshold = 1.25 • Z2F – 0.25 •
I2

Reverse Threshold
V2
If Z2R Setting ≥ 0, Reverse Threshold = 0.75 • Z2R + 0.25 •
I2
V2
If Z2R Setting < 0, Reverse Threshold
= 1.25 • Z2R + 0.25 •
I2

Figure 6 Negative-Sequence Voltage-Polarized Directional Check

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Step 4. Increase the A-phase current (3I2) until it is slightly above 17.45∠111.14 and
verify that FDIRQ asserts. It asserts because the calculated Z2F has crossed the
forward threshold shown in Figure 6.
Note that you could also use the EDIR = AUTO setting and repeat the same steps. The relay
automatically sets the following settings:
50QFP = 0.5
50QRP = 0.25
a2 = 0.10
Z2F = 1.07 (Z2F is set to 0.5 • Z1MAG at angle ∠Z1ANG)
Z2R = 1.27 (Z2R is set to Z2F + 0.2)

Directional Element Routing

In this stage, you route the output of the directional check logic to the directional Relay Word bits
that control the negative-sequence elements. One key feature incorporated in this stage is to
enable forward elements on an LOP condition. This makes the forward-looking elements
nondirectional (DIRQF is forced to 1) because directional checks are no longer reliable when
there is an LOP condition. The logic is shown in Figure 7.
Setting
EFWDLOP = Y

Relay
Word Bits
LOP
DIRQF
FDIRQ
(forward)

RDIRQ DIRQR
(reverse)

Figure 7 Negative-Sequence Directional Element Routing

Test Inputs, Settings, and Targets

The inputs are FDIRQ and RDIRQ (from the directionality check logic test).
Enter the following setting in addition to all previously mentioned settings:
EFWDLOP = Y
The targets are as follows:
DIRQF
DIRQR

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Test Procedure
Step 1. Apply the required conditions from the previous test such that FDIRQ, and
therefore DIRQF, is asserted and LOP is de-asserted. Drop the B-phase voltage to
zero and verify that LOP is asserted. Also, verify that DIRQF stays asserted even
though FDIRQ has now dropped out.
Step 2. Repeat Step 1, this time with EFWDLOP = N, and verify that DIRQF drops out
when LOP is asserted.
Step 3. Apply the required conditions from the directionality check test such that RDIRQ
and DIRQR are asserted. Also, verify that upon dropping B-phase voltage to
simulate an LOP condition, both DIRQR and RDIRQ de-assert irrespective of the
EFDWLOP setting.

Direction Forward/Reverse Logic

In this last stage, the relay exerts directional control on the negative-sequence overcurrent
elements based on the Level 1 through Level 4 forward/reverse direction settings (DIR1–DIR4).
Review the logic in Figure 8. The examples in this guide test only the Level 1 element because
the other three levels work the same.
Level
Direction
Relay Settings
Word Bit DIR1 = F Forward
DIRQF Forward Directional
Control
To Negative-Sequence
Setting DIR1 = N Level Q1DIR
Time-Overcurrent
VNOM = OFF Element
Relay DIR1 = R
Word Bit Reverse
DIRQR

Figure 8 Negative-Sequence Directional Control for Level 1 Negative-Sequence Overcurrent Elements

Test 1 Inputs, Settings, and Targets

The inputs are DIRQF and DIRQR.
Enter the following setting in addition to all of the previously mentioned settings:
VNOM = OFF
The target is as follows:
Q1DIR

Test 1 Procedure
Verify that Q1DIR is 1 irrespective of the currents and voltages applied. This is because
VNOM = OFF is a direct input to the OR gate that drives Q1DIR. This effectively makes the
element nondirectional.

Test 2 Settings
Enter the following settings:
VNOM = 120
DIR1 = N

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Test 2 Procedure
Verify that Q1DIR is asserted irrespective of currents and voltages because DIR = N effectively
sets the element to be nondirectional.

Test 3 Settings
Enter the following settings:
VNOM = 120
DIR1 = F

Test 3 Procedure
Apply the required current and voltages from the previous tests such that DIRQF and FDIRQ are
asserted to 1. Verify that Q1DIR is asserted. Bring the A-phase current down below 17∠111.14
and verify that Q1DIR drops out because DIRQF has dropped out. Bring the current further down
to about 14∠111.14 and verify that Q1DIR is still de-asserted even though DIRQR and RDIRQ
asserted.

Test 4 Settings
Enter the following settings:
VNOM = 120
DIR1 = R

Test 4 Procedure
With the currents applied from the previous step such that DIRQR and RDIRQ are asserted,
verify that Q1DIR now picks up to 1.

Negative-Sequence Instantaneous/Definite-Time Overcurrent Element

Now that you have tested negative-sequence directional control, you can test the negative-
sequence instantaneous/definite-time overcurrent elements that are set to trip for faults either in
the forward or reverse direction. The logic diagram is shown in Figure 9. Test only Level 1 of the
element because all other levels are the same.
67QnP
50QnD
50QnP –
67QnT
|3I2| + 0
50QnTC
QnDIR

Figure 9 Negative-Sequence Instantaneous/Definite TOC Element Logic

Reverse Directional Control

Test Settings and Targets

Enter the following settings in addition to the previously mentioned settings:
DIR1 = R
50Q1P = 13

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50Q1D = 1
50Q1TC = 1
The targets are as follows:
67Q1P
67Q1T
Note that when EDIR = Y or AUTO, the 67Q1P and 67Q1T Relay Word bits are functional and
used. When EDIR = N, 50Q1P and 50Q1T are functional and 67Q1P and 67Q1T are
nonfunctional.

Test Procedure
Step 1. Apply the following currents: Ia = 14∠111.14 amperes, Ib = 0 amperes, and
Ic = 0 amperes. This gives 3I2 = 14∠111.14 amperes.
Step 2. Apply the following voltages: Va = 48∠0 volts; Vb = 67∠–120 volts;
Vc = 67∠120 volts. This gives 3V2 = 19∠180 volts.
Note that to avoid LOP assertion, you must first apply balanced voltages of
67 volts and drop the A-phase voltage in two steps, one of 10 volts and one of
9 volts, to bring it down to 48 volts without assertion of LOP.
Step 3. Verify that 67Q1P is asserted and that 67Q1T is asserted 1 second later. Bring Ia
below 13∠111.14 amperes and verify that 67Q1P and 67Q1T de-assert below
13 amperes even though Q1DIR stays asserted. This is required because 3I2 has
dropped below the pickup setting 50Q1P of 13 amperes.
Step 4. Increase Ia to above 14.51∠111.14 amperes and verify that 67Q1P and 67Q1T
de-assert. This happens because Q1DIR de-asserts, indicating that the fault is no
longer a reverse fault.

Forward Directional Control

Test Settings and Targets

Enter the following settings in addition to the previously mentioned settings:
DIR1 = F
50Q1P = 16
50Q1D = 1
50Q1TC = 1
The targets are as follows:
67Q1P
67Q1T

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Test Procedure
Step 1. Apply the following currents: Ia = 14∠111.14 amperes, Ib = 0 amperes, and
Ic = 0 amperes. This gives 3I2 = 14∠111.14 amperes.
Step 2. Apply the following voltages: Va = 48∠0 volts, Vb = 67∠–120 volts, and
Vc = 67∠120 volts. This gives 3V2 = 19∠180 volts.
Note that to avoid LOP assertion, you must first apply balanced voltages of
67 volts and drop the A-phase voltage in two steps, one of 10 volts and one of
9 volts, to bring it down to 48 volts without the assertion of LOP.
Step 3. Increase current Ia above 16∠111.14 amperes but below 17.45∠111.14 amperes.
Verify that 67Q1P is de-asserted. This is required because even though you have
crossed the 50Q1P pickup, the relay has not declared a forward fault via Q1DIR,
which controls the 67Q1P and 67Q1T outputs.
Step 4. Increase Ia to above 17.45∠111.14 amperes such that DIRQF and Q1DIR assert.
Verify that 67Q1P asserts and that 67Q1T is asserted 1 second later. Now the relay
has successfully declared a forward fault and allowed the element to assert its
output Relay Word bits.
Now that you have completed the testing of the negative-sequence overcurrent elements, try to
test the negative-sequence TOC elements, which use the same directional control. Refer to the
SEL-751 Instruction Manual for logic diagrams (available at https://www.selinc.com).

PHASE DIRECTIONAL ELEMENT

Principle
The SEL-751 uses the positive-sequence impedance calculation based on the ratio of V1/I1,
where V1 is the positive-sequence voltage measured or memorized (in the case of memory
voltage) and I1 is the measured positive-sequence current. The SEL-751 plots the calculated
impedance on an impedance plane to determine directionality.
As shown in Figure 10, if the angle of the calculated positive-sequence impedance falls within
±90 degrees of the Z1ANG setting, which is the characteristic angle of the line, then the relay
declares the fault as forward, provided that other conditions (as shown in the logic in Figure 11)
are satisfied.
(90°)
X1

Forward

Z1ANG

(180°) (0°)
R1

Reverse

(270°)

Figure 10 Positive-Sequence Impedance Plane

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Relay
Word Bits
FDIRP
(forward)
[90° + Z1ANG] > ∠Z1 [ −90° + Z1ANG]
Relay
Word Bits Positive-Sequence
Polarizing Voltage Present RDIRP
VPOLV
Load Condition (reverse)
ZLOAD
Negative-Sequence
Directional Element
Has Priority
DIRQE

LOP
VNOM = OFF
|IA–IB| +

|IB–IC| +
50PDIR
–

|IC–IA| +

50PDIRP 3

Setting (fixed at [phase channel nominal rating] • [0.1]

when load encroachment is enabled)

Figure 11 Positive-Sequence Voltage-Polarized Directional Element Logic

If the calculated positive-sequence impedance angle falls within ±90 degrees of the –Z1ANG
setting, then the fault is declared reverse, again provided that the other logic conditions from
Figure 11 are satisfied.
VPOLV signals the presence of a polarizing voltage, which is V1. Without a reliable polarizing
voltage, the directional decision is compromised. When the fault is a close-in bolted fault, there is
the possibility of zero voltage or the loss of V1. At this time, the relay retains VPOLV for at least
30 cycles, which is enough time for the relay to make a directional decision and trip the breaker.
ZLOAD indicates a load condition. This input comes from the load encroachment logic and is
based on user-defined parameters of forward and reverse load impedances. (See the SEL-751
Instruction Manual for more details on load encroachment logic.)
DIRQE is the internal enable logic output from the negative-sequence directional logic (see
Figure 4). The negative-sequence directional logic has priority over the positive-sequence
directional logic and therefore the DIRQE Relay Word bit has to be de-asserted for the positive-
sequence phase directional logic to process. In other words, only when the negative-sequence
directional element (which is immune to load and mutual coupling) is not enabled is the positive-
sequence directional element enabled (three-phase fault conditions).
LOP indicates blown potential transformer (PT) fuses and the absence of reliable V1. LOP
prevents the logic from processing.
VNOM = OFF indicates the absence of PTs and prevents the logic from processing.
50PDIRP is the three-phase current pickup setting used to supervise the positive-sequence
directional element output, which the user can define except when ELOAD = Y. If ELOAD = Y,
this setting is automatically set to 0.1 • Inom (phase channel nominal rating), which equals
0.5 amperes for a 5-ampere relay.

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Testing the Logic Stages

The logic flow of the positive-sequence directional element control is best understood by
recognizing the various stages involved, as shown in Figure 12, and testing these one by one.
Relay Relay Relay Direction
Word Word Directional Word Forward/
Internal Bit Directional Bit Element Bit Reverse Directional
Enables Outputs Elements Outputs Routing Outputs Logic Control

Level 1

Positive- FDIRP/ DIRPF/ To Phase

Sequence RDIRP DIRPR Instantaneous/
DIRQF Voltage- 2 3
(disable) Level 2 Definite-Time
Polarized
Level 3 Overcurrent
1 Elements
Level 4

Figure 12 Logic Flow of the Positive-Sequence Voltage-Polarized Directional Element

Directional Check
In this stage, the directional determination is made based on the impedance calculation of Z1 to
determine if the fault is forward or reverse, as shown in the logic in Figure 11.

Test Settings and Targets

Enter the following settings:
EDIR = Y or AUTO
Z1MAG = 2.14
Z1ANG = 68.86
ELOAD = N
50DIRP = 1
VNOM = 120
The targets are as follows:
FDIRP (indicates a forward fault)
RDIRP (indicates a reverse fault)

Test Procedure
Step 1. Start with the following balanced currents and voltages:
• Ia = 0.2∠–68.86 amperes, Ib = 0.2∠–188.86 amperes, and
Ic = 0.2∠51.14 amperes.
• Va = 67∠0 volts, Vb = 67∠–120 volts, and Vc = 67∠120 volts.
Step 2. Verify that RDIRP and FDIRP are de-asserted.
Step 3. Increase the magnitude of the three currents simultaneously and verify that 50PDIR
and FDIRP assert above 1 ampere, indicating a forward directional decision.

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Step 4. Apply the following currents with the same voltages: Ia = 0.2∠111.14 amperes,
Ib = 0.2∠–8.86 amperes, and Ic = 0.2∠–128.86 amperes.
Step 5. Increase the magnitude of the three currents simultaneously and verify that 50PDIR
and RDIRP assert above 1 ampere, indicating a reverse directional decision.

Directional Element Routing

In this stage, the output of the directional check logic is routed to the directional Relay Word bits
that control the positive-sequence overcurrent elements, as shown in Figure 13. One key feature
incorporated in this stage is to enable forward elements upon an LOP condition. This is done to
effectively make the forward-looking elements nondirectional. Refer to Figure 7 to see how
DIRQF is always asserted when EFWDLOP = Y because directional checks are no longer
reliable when is an LOP condition.
DIRQF
(forward) DIRPF
FDIRP (forward)

DIRQR
(reverse) DIRPR
RDIRP (reverse)

Figure 13 Positive-Sequence Directional Element Routing

Test Inputs, Settings, and Targets

The inputs are FDIRP and RDIRP (from the directional check logic test).
Note that FDIRQ is also an input that can assert DIRPF, indicating that a forward unbalanced
fault also asserts DIRPF. However, this test does not apply unbalanced currents, so only FDIRP
and RDIRP are treated as inputs.
Enter the following setting in addition to all of the previously mentioned settings:
EFWDLOP = Y
The targets are as follows:
DIRPF
DIRPR

Test Procedure
Step 1. Apply the required conditions from Step 3 of the directional check test such that
FDIRP and therefore DIRPF is asserted and LOP is de-asserted. Drop the B-phase
voltage to zero and verify that LOP is asserted. Verify also that DIRPF stays
asserted even though FDIRP has now dropped out.
Step 2. Repeat Step 1, this time with EFWDLOP = N, and verify that when LOP is
asserted, DIRPF drops out.
Step 3. Apply the required conditions from the directional check logic check test such that
RDIRP and DIRPR are asserted. Verify also that upon dropping B-phase voltage to
simulate an LOP condition, both DIRPR and RDIRP de-assert irrespective of the
EFDWLOP setting.

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Directional Control for Phase-Overcurrent Elements

In this last stage, the relay exerts directional control on the phase-overcurrent elements based on
the Level 1 through Level 4 forward/reverse direction settings (DIR1–DIR4). This logic is shown
in Figure 14. This guide focuses only on the Level 1 element, because the other three levels are
the same.
Level
Direction
Relay Settings
Word Bit DIR1 = F Forward
Forward Directional
DIRPF
Control
Setting Level P1DIR To Phase
DIR1 = N Time-Overcurrent
VNOM = OFF
Elements
DIR1 = R
DIRPR Reverse

Figure 14 Positive-Sequence Directional Control for Level 1 Phase-Overcurrent Elements

Test 1 Inputs, Settings, and Targets

The inputs are DIRPF and DIRPR.
Enter the following setting in addition to all of the previously mentioned settings:
VNOM = OFF
The target is as follows:
P1DIR

Test 1 Procedure
Verify that P1DIR is 1 irrespective of the currents and voltages applied. This is because
VNOM = OFF is a direct input to the OR gate that drives P1DIR.

Test 2 Settings
The settings are as follows:
VNOM = 120
DIR1 = N

Test 2 Procedure
Verify that P1DIR is asserted irrespective of currents and voltages because DIR = N effectively
sets the element to be nondirectional.

Test 3 Settings
Enter the settings as follows:
VNOM = 120
DIR1 = F

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Test 3 Procedure
Apply the required conditions from Step 3 of the directional check test such that DIRPF and
FDIRP are asserted to 1. Verify that P1DIR is asserted. Rotate all three currents by more than
90 degrees such that DIRPF drops out, and verify that P1DIR drops out as expected because the
fault is no longer forward.

Test 4 Settings
Enter the settings as follows:
VNOM = 120
DIR1 = R

Test 4 Procedure
With the currents applied from the previous step such that DIRPR and RDIRP are asserted, verify
that P1DIR picks up to 1. Rotate all three currents by more than 90 degrees and verify that P1DIR
drops out because the fault is no longer reverse.

Phase Instantaneous/Definite-Time Overcurrent Element

Test the phase overcurrent elements, which are set to trip for faults either in the forward or in the
reverse direction.
Again, test only Level 1 of the element because all other levels are the same. Figure 15 shows the
logic diagram.
67PnP
50PnD
50PnP –
67PnT
|IP| + 0
50PnTC
PnDIR

Figure 15 Phase Instantaneous/Definite TOC Element Logic

Phase Instantaneous Overcurrent Set Reverse

Test Settings and Targets

Enter the following settings in addition to the settings mentioned in the directional check test:
DIR1 = R
50P1P = 5
50P1D = 1
50P1TC = 1
The targets are as follows:
67P1P
67P1T

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Note that when EDIR = Y or AUTO, the 67P1P and 67P1T Relay Word bits are functional and
used. When EDIR = N, 50Q1P and 50Q1T are functional and 67Q1P and 67Q1T are
nonfunctional.

Test Procedure
Step 1. Apply the following current: Ia = 5.1∠111.14 amperes, Ib = 5.1∠–8.86 amperes,
and Ic = 5.1∠–128.86 amperes.
Step 2. Apply the following voltages: Va = 67∠0 volts, Vb = 67∠–120 volts, and
Vc = 67∠120 volts.
Step 3. Verify that 67P1P is asserted and that 67P1T is asserted 1 second later. Rotate the
current angles by more than 90 degrees and verify that both 67P1P and 67P1T drop
out because P1DIR dropped out, indicating a forward fault. The rotated current
values should be Ia = 5.1∠201.14 amperes, Ib = 5.1∠81.14 amperes, and
Ic = 5.1∠–38.86 amperes.

Phase Instantaneous Overcurrent Set Forward

Test Settings and Targets

Enter the following settings in addition to the settings mentioned in the directional check test:
DIR1 = F
50P1P = 5
50P1D = 1
50P1TC = 1
The targets are as follows:
67P1P
67P1T

Test Procedure
The procedure is as follows:
Step 1. Apply the following currents and voltages:
• Ia = 5.1∠–68.86 amperes, Ib = 5.1∠–188.86 amperes, and
Ic = 5.1∠51.14 amperes.
• Va = 67∠0 volts, Vb = 67∠–120 volts, and Vc = 67∠120 volts.
Step 2. Verify that 67P1P is asserted and that 67P1T asserts 1 second later. Rotate the
current angles by more than 90 degrees and verify that both 67P1P and 67P1T drop
out because P1DIR dropped out, indicating a reverse fault. The rotated current
values are Ia = 5.1∠21.14 amperes, Ib = 5.1∠–98.86 amperes, and
Ic = 5.1∠141.14 amperes.
With the testing of the phase overcurrent elements completed, you can try testing the phase TOC
elements, which use the same directional control. Refer to the SEL-751 Instruction Manual
(available at https://www.selinc.com) for logic diagrams.

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REFERENCES
[1] B. Fleming, “Negative-Sequence Impedance Directional Element,” proceedings of the 10th
Annual Pro Test User Group Meeting, Pasadena, CA, February 1998. Available:
https://www.selinc.com.
[2] A. Hargrave, “Understanding and Testing the Negative-Sequence Directional Element.”
Available: https://www.selinc.com.

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SEL Application Guide 2016-02 Date Code 20160126