LAPTOP CHIPS VOLTAGES

CPU 2.5V (VDD)

VCORE (1V Aprox 30Amp current)
DDR 3.3V LAN 5V
1.05VCCP 1.25V (VTT ) HDD
3.3V (SPD)
1
3.3V
Vtt CPU

1.8V (VDD)
BIO FAN
1.05VCCP or 5V
0.9V (VTT DDR 3.3V S
1.5v DDR)
MCH 2
1.8V 3.3V (SPD) DVD
Nort
h 5V 5V
3.3V bridg 1.5V US
e (VDD) B 3.3 AUDIO
0.75V
DDR V
(VTT ) 3
3.3V CARD
RTC DDR 3L READ
3.3V ER 3.3
1.05VC
(SPD) V
CP THERMAL
3.3V 1.35V
LCD 3.3V
(VDD) /
5V ICH LE CLOCK 5V
0.65V (VTT
D
Sout )
h 3.3V
bridg (SPD)
e
V IN
3.3
V

CORE
GFXCORE1.1V 3.3V
GP i3,i5,i7 1.05V
U
SIO VCORE
(KB
3.3V C) 1.5 1.8V GFX CHI GFXCO
RE
V P
1.05VCCP Core i3 CPU PCH
1.8
1.5V V

TC 7
1.
5V
 Up to C2D CPU
3volt VCC 1
(cpu)
32.7KHZ
BIOS VR_ON (B

KBC_PWRBTN PWR_ON ( main_on, Run on)

SIO
3
6 SUSp_ON
2
4 5

PM_SLP_S3
PM_PWRBTN

PM_SLP_S4
3 VOLT
RSMRST

susb

susc
VCC

RSMRST

PWRBTN

ICH PM_PWRBTN

SLP_S3

SLP_S4
POWER ON BUTTON SEQ.
 3volt VCC
32.7KHZ
Pin No 8 1
EC BIOS

VR_ON (cpu)

PWR_ON (Bridge, Ram supply)

2 7
KBC_PWRBTN Main on(sys on)
SIO
SUSP_ON
4 3
RSMRST

PM_PWRBTN
5 6

PM_SLP_S4
PM_SLP_S3
susb

susc

PCH

POWER ON BUTTON SEQ.

 Presenter
2016-04-07 23:46:38
--------------------------------------------
Approved molly, ramey, morhardt,
bettencourt, tucker 3/25 Includes small and
large business

Core i3 power sequence

SW

1 SW

SIO
R304 Y1

C345 R491 R490 R503

ITE-8518 R105

EC

PCH
9
SUS_ON

RUN_ON
10
1
EC_PWROK313 HWPG
VR_ON
1211
Core i3 VRM 1 Vin voltage

section
5vo
lt
VCC CPU core

2
3
From SIO 1 v to 1.5v
VR_ON

6 VRM
5
To SIO Clock Core v
enable
4
6
VRM
power
Core i3
good CPU
VID signal from

GFX Core
CPU
GND
32
 230v AC
Power Block Diagram
CPU Core
volt
0.8 v or 1v VCORE

Battery Adopter
17
18
1

0.9 v
Volt In
Step down
2
1.8v
1.05v
14
SM BUS

CHG_ENABLE

2 15

MOSFET 3.3vSUS

On\off
VR_ON
12
switch 16 5vSUS
13 MOSFET
Enable

SYS_ON
8 11
SUSP

(SIO) 4 SLP_S5 Step 3.3VALWS

Enab VRMPWRGD down 5 5VALWS
1
PG OK

sig
KBC
32.7khz crystal

3v supply 3VL
6 3
ICH
PG 9 19 P3,SLP4,
P W RB T
si
N
l g n a EC_PWRGD(PWRGD)
S
1 0
3 vo lt L
 RSMRST 7
PWRBTN
 SUS_PWRGD
MAIN_PWRGD Power Block Diagram
GFX_PWRGD 230v AC
CPU Core 0.8v or 1v VCORE
volt
Adopter 18
Battery

1
GFX 15
Volt In
1.8v
SM BUS

Step down
13
CHG_ENABLE

2 1.05v
0.9v
ACIN

2 15

MOSFET 3.3vSUS
VR_ON 17

14
16
GFX_ON
11
5vSUS
Enable

SYS_on(Run1o
MOSFET
HWPG
2n) SUSP 10
SIO Step 3.3VALWS
Enab 19 VRMPWRGD down 5 5VALWS
32.7khz crystal

1
KBCsig
SLP_S5
4 3
3v supply
RSMRST 6
ICH
On\off
PG 8 9
P W RB T 3 vo lt
switch si l g n a
N
20
SLP3,SLP4,
7
ECP PM_PWRBTN
WRO
K(PW
R_GD
)
 POWER ON AND RESET SEQUENCE

18v adopter 10.8 Battary

Input Input 8
ON/OFF SLP4
SW 10
SLP3
Clock start

V In
PM_PWRBTN Clock 20
ACIN 9
CPU 23
SIO RSMRST
19
CORE_V
17 CPU_PWRGD

16 7

CK_PWRGD
HWPG 15 22 M_PWRGD

CPU Reset
1 SYS_ON (MAIN ON) 13
ECPWORK 25
21

CPU_PWRGD
RST
CKT KBC_RST
PLTRST
3

VRMPW MCH
KBC_3D3_ALWS

RGD North Bridge

6
BIOS
SUSON

2 RSTIN CL_RST
(VGATE)
4
PWRGD
SLP_S5

11
Step 6 24
down 12 PLTRST
3.3v_ALWS 3.3V_SUSP
1 5 CL_RST
5V_ALWS 5v_SUSP CLK_PWRGD

SLP4/ 5
1.8v SLP3
Step To DDR
Down 0.9v 14
PWROK
15
2 1.05V 7 RSMRST
PWROK
ICH 23
South Bridge
3.3V

VR_ON 1.05V
w.shriraminfo CPU
tech.net Core
ww
17 CPU_CORE

VRMPWRGD 18
VRMP
WRG
D
 CPU RESET
R322

CPU
SIO

R313

R605

PCH
ECPWROK
ADOPTER Battery
ALWS PWRGD
CLOCK
MAIN PWRGD
SUS PWRGD HWPG

PWRBTN 18
ACIN
13
3

DRAM PWRGD
CPU PWRGD
Slp _S5

PLTRST
Step
down
2 ECPWORK 19 21 20
1 1
3.3VAL 22
EC BIOS
SUSB, SLP_S3
5V SUSC, SLP_S4 8 PCH
4 7
SUS ON

PM_PWRBTN
MOSFET

MOSFET
RSMRST
6
3.3V
5V
5
9 MAINON
Step
10 1.05V(PCH, CPU)
Down
1.5V(DDR3)
2
1.8V
14
11 GFX ON
VR_PWRGD

GFX 15 16
CORE 12 GFXCORE V
VR_ON
CK_PWRGD
CPUCORE V
CPU
 BIOS
CS
23
CLOCK CHIP
ADOPTER Battery
ALWS
CLOCK
PWRGD MAIN PWRGD HWP
SUS PWRGD G
PWRBT
N
ACIN 13
21 20
3

PWRGD
PWRGD
Step SLP _S5

PLTR

DRAM
dow
2 ECPWORK 19

ST
1 n1 3.3VAL 2

CPU
SUSB, SLP_S3
2

5V SUSC, SLP_S4 8 PCH

4
MOSFET
7
SUS
ON

PM_PWRBTN

MOSFET
RSMRST
6
Step
Dow
5 3.3V

n2
9 MAINON
1.05V(PCH,
CPU)
10

1.5V(DDR3)

GFX ON 14
 11 16
GFX

VR_PWR
COR GFXCORE V
E 12
VR_ON

GD
CPUCORE
CP V
U 15 1
Cor
7
e 47
CK_PWRGD
 5 4 3 2 1

ATX P/S WITH 1A STBY CURRENT ATX4P

5VSB 5V 3.3V 12V -12V 12V
+/-5% +/-5% +/-5% +/-5% +/-5% Intel Sandy Bridge CPU Fans
+/-5% Vcore:0.65~1.3V 112Amax
Switching VID
UP6230 VCCP 0.25~1.52V 85A(95W) 12V_200mA
Vaxg:0.65~1.3V 35Amax
4 hases VID
VAXG 0.25~1.52V 25A
V_CPU_VTT:1.05V 17Amax SPI D
D
Switching VTT 1.05V(1V) 8.5A
UP6123 VCC_SA:0.925V(0.85V) 8.8Amax
Linear VCC3_30mA
1 phase OP358 VCC_SA 0.925V(0.85V) 8.8A

VCCPLL 1.8V 1A
VCC V_DIMM:1.5V 28.5Amax CRT
Switching
5VSB 5VDUAL APW 7120 VDDQ 1.5V 4.5A
P/N MOS VCC_1A fuse

DDR3 DIMM (4) 1333MHz

LDO HDMI/DP
LDO APL5336
VDDQ 15A_S0
3VSB Intel Cougar Point (TDP 5.5W) VCC3_0.5A fuse x 2
1.0A_S3
DDR_VTT:0.75V V_PROC_IO 1.05V 1mA
V_SM_VTT 1.0A_S0
HDMI L.S.
VccDMI 1.05V 0.057A
Linear PCH_CORE:1.05V 6.2Amax VCC3_180mA
OP358 VccCORE 1.05V 1.6A

VccIO 1.05V 4.07A

Flash/NVM
VccADPLLA 1.05V 0.1A
VCC3 _0.3A
VccADPLLB 1.05V 0.1A
C
1.8V_0.1A C

VccCLKDMI 1.05V 0.02A

Non AMT:
VccASW(ME) short to V1P05_PCH VccSSC 1.05V 0.105A

VccDIFFCLKN 1.05V 0.055A

V_ME:1.05V 1.8Amax
VccASW(ME) 1.05V 1.61A

VccDFTERM 1.8V 0.2A

Linear V_SFR:1.8V 1.6Amax
VccVRM 1.8V 0.159A
OP358

Vcc3_3 3.3V 0.409A

VccADAC 3.3V 0.068A
Not support DSW mode:
VccDSW short to 3VSB VccSPI 3.3V 0.02A

VccDSW3_3 3.3V 0.003A

VccSUS3_3 3.3V 0.097A

VccSUSHDA 3.3V 0.01A

Battery
B B
VccRTC 3.3V 6uA(G3) 3V

V5REF 5V 1mA

V5REF_SUS 5V 1mA

VCC3
NEC_D720200
3VDUAL
3VSB P/N MOS VDD3P3 3.3V TBD
Extrenal from V1P05_PCH
VDD1P05 1V TBD

VCC CTRL1P0 internal LVR Output

5VDUAL
5VSB
Switch IC
UP7536 SUPER I/O F71808A

3VSB 3VSB 3.3V TBD

USB_5V
VCC3 VCC3 3.3V TBD

BAT 3.3V 3.3V TBD

X16 PCIE Slot per X1 PCIE Slot per PCI Slot per USB X4 Header USB X4 IO USB3.0
A A

3.3V 3A(S0) 3.3V 3A(S0) 5V 5A(S0) VDD VDD

5VDual AUDIO VT1705CE
12V 5.5A(S0) 12V 0.5A(S0) 12V 0.5A(S0) 5VDual 5VDual VCC3
2A
3.3Vaux 0.375A 3.3Vaux 0.375A 3.3Vaux 0.375A 2.0A 2.0A 5VSB
DVDD 3.3V 3.3V 23mA

Total 1 Slot 3.3V 7.6A(S0)

Total 2 Slots AVDD 5V 38mA
Elitegroup Computer Systems
Total 1 Slot
Title
Power Delivery
Size Document Number Rev
C H61H2-M12 1.0
 Date: Wednesday, July 13, 2011 Sheet 27 of 29
5 4 3 2 1
 5 4 3 2 1

9 V_1P05_PCH
7 EN
12
CPUVTT

CPUVTT RT8121
D D

13 VTT_PWRGD 18 VCORE

38 EN_VTT

VCORE
Bi-direction
19 SVDATA 17 VIDSOUT

VCORE RT8859A
40 VR_RDY 19 VR_RDY

21 SIO_PCIRST1_L

C
Slot:PCIEx16/x1/LAN

SVDATA(B37) VCCCORE VCCIO

SIO_PCIRST2_L
21 C

21 SIO_PCIRST2_L CMOS 1.1V

RESET#(F36)

CPU
PCH Cougar Point Sandy Bridge
2 FP_PWRBTN_L 20 PLTRST_L
PLTRST#(BK48) SYS_PWROK(BJ53) Desktop Processor
POWER BUTTON Socket H2
4 RSMRST_L RSMRST#(BK38)
PROCPWRGD(D53) 16 CPU_PWROK
UNCOREPWRGOOD(J40)

3 3VSB
6 SLP4_L
SLP_S4#(BN52)

7 SLP3_L
SLP_S3#(BM53) CPUCLK(P31/R31) 15 CPU_BCLK
BCLK(W1/W2)

5 SIO_PWRBTN_L PWRBTN#(BT43)
B B

DRAMPWROK(BG46) 14 DRAM_PWROK SM_DRAMPWROK(AJ19)

11 PWROK PWROK(BJ38)

9 8 SYS_RESET#(BE52)
SYSRST_L
+VCC PSON_L
RESET BUTTON

4, 6, [21..23] 16
10
VCC5 PS_ON
ATX_PWRGD
8 PWROK

ATX_POWER
1 3VSB_IO 9 5VSB
A A
 Elitegroup Computer Systems
Title

Power Sequence, Reset Diagram

Size Document Number Rev
Custom
H61H2-M12 1.0
Date: Wednesday, July 13, 2011 Sheet 28 of 29
5 4 3 2 1

12 PCIRST2# 44 PCIRST3#

LRESET 15
35 PANSHW#

RSMRST# 45

31 SYS_3VSB SUSC# 37

Super I/O SUSB# 32

29 3VSB ITE 8758
PWRON# 33

54 ATXPG PWRGD[1..3] 32/18/78

55 VIN1 36 PSON#
 Timing Diagram for S5 to S0 mode +1.05V_RUN
VCC
PCH PWRBTN#
SIO_PWRBTN#

PCH_RSMRST#
VCCIO
VCCUSBPLL
V_PROC_IO
RSMRST#
SIO_SLP_S5#
4
SLP_S5#
+1.05V_M VCCCLK
VCCASW SIO_SLP_S4#
SLP_S4#
+1.5V_RUN SIO_SLP_S3#
VCCADAC1_5
VCCVRM
SLP_S3#
SIO_SLP_A#
5
+3.3V_ALW_PCH SLP_A#
VCCSUS3_3 SIO_SLP_LAN#
VCCSUSHDA SLP_LAN#

CPU +3.3V_RUN SLP_WLAN#/GPIO29

SIO_SLP_WLAN#
PM_DRAM_PWRGD_CPU +VCC_CORE VCCADACBG3_3
14 SM_DRAMPWROK VCC VCC3_3_R30
VCC3_3_R32
SYS_PWROK
SYS_PWROK
16
+VCCIO_OUT RESET_OUT#
VCC3_3
VCCIO_OUT PWROK
H_CPUPWRGD VCCCLK3_3

15 PWRGOOD +VCOMP_OUT 13
VCOMP_OUT 3 +3.3V_ALW
VDDDSW3_3
DRAMPWROK
PM_DRAM_PWRGD

17
CPU_PLTRST#_R
PLTRSTIN +1.35V_MEM 14
VDDQ
PLTRST# H_CPUPWRGD
17 PCH_PLTRST# PROCPWRGD
15
APWROK

7 PM_APWROK_R

DPWROK
PCH_DPWROK

4
Pop option
DGPU_PWR_EN# DMN65D8LW-7 DGPU_PWR_EN
GPIO54
11

+3.3V_ALW

TPS22965 LCD_ENVDD_SW
+LCDVDD
GPIO17
DGPU_PWROK MXM 12
+3.3V_ALW
Pop option
6 +3.3V_M +3.3V_LAN
TPS22965 SIO_SLP_LAN# DGPU_PEX_RST#

17

+5V_ALW Power Button

RUN_ON
+5V_RUN +5V_HDD
TPS22965
SIO_SLP_S3# SIO 5048 1BAT 2AC
+3.3V_ALW
SIO_SLP_S4#
+PWR_SRC 1BAT
5 SIO_SLP_M#
TPS22965 9
ADAPTER
ALWON 2AC
+3.3V_RUN TPS5125 +5V_ALW
SIO_SLP_LAN# EC 5075
+3.3V_ALW
+1.05V_M
ALW_PWRGD_3V_5V
SI4164DY +1.05V_RUN
1.35V_SUS_PWRGD
+3.3V_ALW BATTERY 5048

SYN470DBC +1.5V_RUN
DGPU_PWROK

DGPU_PWR_EN
MXM
4 PCH_RSMRST#

11 +PWR_SRC +3.3V_ALW
PCH_ALW_ON TPS22965 3
+PWR_SRC_MXM IMVP_VR_ON
+VCC_CORE 12 +3.3V_ALW_PCH
10 +MXM_PWR_SRC SI4835D 3.3V_RUN_GFX_ON
ISL95812
PM_APWROK
IMVP_PWRGD
7 +3.3V_ALW 6 Pop option
A_ON TPS22965 +3.3V_M
+3.3V_ALW +3.3V_LAN
10 3.3V_RUN_GFX_ON 8 RESET_OUT#
+3.3V_MXM +PWR_SRC
TPS22965 SUS_ON 14 +PWR_SRC
+1.35V_MEM VDDQ A_ON

+5V_ALW 0.75V_DDR_VTT_ON
RT8207MZ
+0.675V_DDR_VTT VTT
DDR
TPS51212
+1.05V_M 6
10 +5V_MXM 3.3V_RUN_GFX_ON 5
SIO_SLP_S5#
1.05V_A_PWRGD
TPS22965 1.35V_SUS_PWRGD
5075

+3.3V_ALW +PWR_SRC
+3.3V_ALW SUS_ON PCH_ALW_ON TP0610K 3
+3.3V_PCIE_FLASH TPS22965 +PWR_SRC_S
TPS22965
MCARD_MISC_PWREN +3.3V_SUS 8
+5V_ALW
+3.3V_ALW MODC_EN
+3.3V_WLAN
TPS22965
AUX_EN_WOWL TPS22965 +5V_MOD 12
+PWR_SRC
+3.3V_ALW EN_INVPWR
NVRAM_PWR_EN
FDC654P
+3.3V_PCIE_WWAN +BL_PWR_SRC
TPS22965 BC BUS
 5 4 3 2 1

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3a -3a -3a 3a
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D

3
PM_SLP_S4#
-3b -3c EN
DDR_VREF_S3 3b
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
Page40 LL1 PUMP
TPS51216RUKR
3D3V_S5
LL2
SWITCH 5a 0D75V_S0
Page40 5V_AUX_S5 VTT
VREG5
TPS51123RGER
DC/DC 3D3V_AUX_S5 -4 1.05VTT_PWRGD
VTT_EN
VREG3 RUNPWROK
-5 (3V/5V) 3 PGD

DCBATOUT 3V_5V_POK PM_SLP_S4# Page46

VIN PGOOD 5
Page41

4 5V_S5 3D3V_S5
DC BQ24707 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 Page37
3D3V_AUX_KBC -3a 4 VOUT
VDD VIN 1D8V_S0
Page40 ACOK 3D3V_S0
S5_ENABLE SWITCH TPS53311RGTR
-6a Page37 PM_SLP_S3# EN
PGD
Page47 RUNPWROK
AC_IN# GPIO34 1D5V_S0
GPIO70
C
SWITCH C

1
Page37 5
-1 KBC SLP_S4# SLP_S3#
KBC_PWRBTN#
GPIO6 NPCE795P -2
Power Button PM_RSMRST# 9 0D75V_EN
AND GATE
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 PROCPWRGD
H_CPUPWRGD H_CPUPWRGD_R
UNCOREPWRGOOD
Page27 Cougar Point 10
GPIO77 PCH Sandy Bridge
8
15 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK

14

SVID
11
5V_S5 DCBATOUT

B V5IN VIN 1D05_VTT 5a B

VOUT
5
RUNPWROK
TPS51218DSCR
EN 1.05VTT_PWRGD
Page45 PGOOD
14
5V_S5 DCBATOUT 5b IMVP_PWRGD SYS_PWROK

VDDP VIN 0D85_S0 5c -4

5b VOUT -7 3D3V_AUX_S5
1.05VTT_PWRGD TPS51461RGER RTC_AUX_S5
EN
PGOOD
D85V_PWRGD -8
Page48
+RTC_VCC
6
DCBATOUT
RTC battery

11
SVID
VIN VCC_CORE
OUTPUT
A
SVID
VR VCC_GFXCORE 12
OUTPUT
A

6 ISL95831HRTZ
D85V_PWRGD
7
IMVP_VR_ON 13 DV15 HR Vos GIIIGA HDMIII NoSurrrge
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
21F,,, 88,,, Sec...1,,, Hsiiin Taiii Wu Rd...,,, Hsiiichiiih,,,

Power Up Sequence: -8 ~ 15
Taiiipeiii Hsiiien 221,,, Taiiiwan,,, R...O...C...

Tiiitttllle

Power Sequence Diagram

Siiize Documenttt Numberrr
A2 Enric
 Rev
o/Caruso 15 HR X01
Dattte::: Thurrrsday,,, June 02,,, 2011 Sheettt 99 offf 104
5 4 3 2 1