p-n junction: A p-n junction is formed when a p-type and an n-type
semiconductor are brought into intimate contact. The p-n junction, in addition
to being a device that is used in many applications, is the basic building block
for other semiconductor devices.
Basic fabrication steps:
Transistor Action:
The emitter-base junction of a transistor is forward biased whereas collector-base
junction is reverse biased. If for a moment, we ignore the presence of emitter-base
junction, then practically no current would flow in the collector circuit because of
the reverse bias. However, if the emitter-base junction is also present, then
forward bias on it causes the emitter current to flow. It is seen that this emitter
current almost entirely flows in the collector circuit. Therefore, the current in the
collector circuit depends upon the emitter current. If the emitter current is zero,
then collector current is nearly zero.
Working of npn transistor:
Common Base Connection:
FET: The field effect transistor (FET) has, by virtue of its construction and biasing,
large input impedance which may be more than 100 megaohms. The FET is
generally much less noisy than the ordinary or bipolar transistor.
JFET: In a JFET, the current conduction is either by electrons or holes and is
controlled by means of an electric field between the gate electrode and the
conducting channel of the device. The JFET has high input impedance and low noise
level.
Metal Oxide Semiconductor FET (MOSFET):
The main drawback of JFET is that its gate must be reverse biased for roper operation of
the device i.e. it can only have negative gate operation for n-channel and positive gate
operation for p-channel. This means that we can only decrease the width of the
channel. This type of operation is referred to as depletion-mode operation. However,
there is a field effect transistor (FET) that can be operated to enhance (or increase) the
width of the channel (with consequent increase in conductivity of the channel) i.e. it
can have enhancement-mode operation. Such a FET is called MOSFET.
A MOSFET is an important semiconductor device and can be used in any of the circuits
covered for JFET. However, a MOSFET has several advantages over JFET including high
input impedance and low cost of production.
Types of MOSFETs:
There are two basic types of MOSFETs viz.
1. Depletion-type MOSFET or D-MOSFET. The D-MOSFET can be operated in both the
depletion-mode and the enhancement-mode. For this reason, a D-MOSFET is
sometimes called depletion/enhancement MOSFET.
2. Enhancement-type MOSFET or E-MOSFET. The E-MOSFET can be operated only in
enhancement-mode.
Crystal growth technology:
The two most important semiconductors for discrete devices and integrated circuits are silicon and
gallium arsenide. In this chapter we describe the common techniques for growing single crystals of
these two semiconductors. The basic process flow from starting materials to polished wafers is
shown in Fig. 1. The starting materials, silicon dioxide for a silicon wafer and gallium and arsenic for
a gallium arsenide wafer, are chemically processed to form a high-purity polycrystalline
semiconductor from which single crystals are grown. The single-crystal ingots are shaped to define
the diameter of the material and sawed into wafers. These wafers are etched and polished to
provide smooth, specular surfaces on which devices will be made.
A technology closely related to crystal growth involves the growth of single-crystal semiconductor
layers on a single-crystal semiconductor substrate. This is called epitaxy, from
the Greek words epi (meaning "on") and taxis (meaning "arrangement"). The epitaxial layer and the
substrate materials may be the same, giving rise to homoepitaxial.
SILICON CRYSTAL GROWTH FROM THE MELT
The basic technique for silicon crystal growth from the melt, which is material in liquid form,
is the Czochralski technique. A substantial percentage (> 90%) of the silicon crystals for the
semiconductor industry is prepared by the Czochralski technique, and virtually all the silicon
used for fabricating integrated circuits is prepared by this technique.
Starting Material
The starting material for silicon is a relatively pure form of sand (SiO,) called quartzite. This is
placed in a furnace with various forms of carbon (coal, coke, and wood chips). Although a
number of reactions take place in the furnace, the overall reaction is
SiC (solid) + Si02 (solid) Si (solid) +SiO (gas) + CO (gas), (1)
This process produces metallurgical-grade silicon with a purity of about 98%. Next, the
silicon is pulverized and treated with hydrogen chloride (HCI) to form trichlorosilane
(SiHC13):
300°C
Si (solid) + 3HCl (gas) SiHCl3 (gas) + H2 (gas). (2)
The trichlorosilane is a liquid at room temperature (boiling point 32OC); Fractional
distillation of the liquid removes the unwanted impurities. The purified SiHCI, is then used in
a hydrogen reduction reaction to prepare the electronic-grade silicon (EGS):
SiHCl3 (gas) + H2 (gas) Si (solid) + 3HCl (gas). (3)
This reaction takes place in a reactor containing a resistance-heated silicon rod, which serves
as the nucleation point for the deposition of silicon. The EGS, a polycrystalline material of
high purity, is the raw material used to prepare device-quality, single-crystal silicon. Pure
EGS generally has impurity concentrations in the parts-per-billion range.
The Czochralski Technique
The Czochralski technique uses an apparatus called a crystal puller shown in Fig. 2. The
puller has three main components: (a) a furnace, which includes a fused-silicon (SiOz)
crucible, a graphite susceptor, a rotation mechanism (clockwise as shown), a heating
element, and a power supply; (b) a crystal-pulling mechanism, which includes a seed
holder and a rotation mechanism (counter-clockwise); and (c) an ambient control, which
includes a gas source (such as argon), a flow control, and a exhaust system. In addition, the
puller has an overall microprocessor-based control system to control process parameters
such as temperature, crystal diameter, pull rate, and rotation speeds, as well as to permit
programmed process steps. Also, various sensors and feedback loops allow the control
system to respond automatically, reducing operator intervention.
In the crystal-growing process, polycrystalline electronic grade silicon (EGS) is placed in the
crucible and the furnace is heated above the melting temperature of silicon. A suitably
oriented seed crystal (e.g., [111]) is suspended over the crucible in a seed holder. The seed
is inserted into the melt. Part of it melts, but the tip of the remaining seed crystal still
touches the liquid surface. It is then slowly withdrawn. Progressive freezing at the solid-
liquid. interface yields a large, single crystal. A typical pull rate is a few millimeters per
minute. For large-diameter silicon ingots, an external magnetic field is applied to the
basic Czochralski puller. The purpose of the external magnetic field is to control the
concentration of defects, impurities, and oxygen content. Figure 3 shows a 300 mm (12
in.) and a 400 mm (16 in.) Czochralski grown silicon ingots.
Fig. 3 300 mm (12 in.) and 400 mm
(16 in.) Czochralski-grown silicon
ingots.
GaAs CRYSTAL-GROWTH TECHNIQUES:
Starting Materials
The starting materials for the synthesis of polycrystalline gallium arsenide are the elemental,
chemically pure gallium and arsenic . Note that long before the melting point is reached, the
surface layers of liquid gallium arsenide may decompose into gallium and arsenic. Since the
vapor pressure of gallium and arsenic is different, there is a preferential loss of the more
volatile arsenic species, and the liquid becomes gallium rich. To synthesize gallium arsenide, an
evacuated, sealed quartz tube system with a two temperature furnace is commonly used. The
high-purity arsenic is placed in a graphite boat and heated to 610-620°C, whereas the high-
purity gallium is placed in another graphite boat and heated to slightly above the gallium
arsenide melting temperature (1240-1260°C). Under these conditions, an overpressure of
arsenic is established (a) to cause the transport of arsenic vapor to the gallium melt, converting
it into gallium arsenide, and (b) to prevent decomposition of the gallium arsenide while it is
being formed in the furnace. When the melt cools, a high-purity polycrystalline gallium arsenide
results. This serves as the raw material to grow single-crystal gallium arsenide.
Crystal-Growth Techniques
There are two techniques for GaAs crystal growth: the Czochralski technique and the Bridgman
technique. Most gallium arsenide is grown by the Bridgman technique. Figure 12 shows a
Bridgman system in which a two-zone furnace is used for growing single-crystal gallium
arsenide. The left-hand zone is held at a temperature ( ̴610°C) to maintain the required
overpressure of arsenic, whereas the right-hand zone is held just above the melting point of
gallium arsenide (1240°C). The sealed tube is made of quartz and the boat is made of graphite.
In operation, the boat is loaded with a charge of polycrystalline gallium arsenide, with the
arsenic kept at the other end of the tube.
As the furnace is moved toward the right, the melt cools at one end. Usually, there
is a seed placed at the left end of the boat to establish a specific crystal orientation.
The gradual freezing (solidification) of the melt allows a single crystal to propagate
at the liquid-solid interface. Eventually, a single crystal of gallium arsenide is grown.
Crystal Characterization:
Crystal Defects
A real crystal (such as a silicon wafer) differs from the ideal crystal in important
ways. It is finite; thus, surface atoms are incompletely bonded. Furthermore, it has
defects, which strongly influence the electrical, mechanical, and optical properties
of the semiconductor. There are four categories of defects: point defects, line
defects, area defects, and volume defects.
Figure 15 shows several forms of point defects. Any foreign atom incorporated into
the lattice at either a substitutional site [i.e., at a regular lattice site (Fig. 15a)l or
interstitial site [i.e., between regular lattice sites (Fig.15b)l is a point defect. A
missing atom in the lattice creates a vacancy, also considered a point defect (Fig.
15c). A host atom that is situated between regular lattice sites and adjacent to a
vacancy is called a Frenkel defect (Fig. 15d). Point defects are particularly important
subjects in the kinetics of diffusion and oxidation processes.
Fig. 15 Point defects. (a) Substitutional impurity. (b) Interstitial impurity. (c) Lattice vacancy.
(d) Frenkel-type defect
Fig. 16 (a) Edge and (b) screw dislocation formation in cubic crystals.
Fig. 17 (a) Twinning and (b) grain boundary formation in crystals.
The next class of defects is the line defect, also called a dislocation. There are two types
of dislocations: the edge and screw types. Figure 16a is a schematic representation of an
edge dislocation in a cubic lattice. There is an extra plane of atoms AB inserted into the
lattice. The line of the dislocation would be perpendicular to the plane of the page. The
screw dislocation may be considered as being produced by cutting the crystal partway
through and pushing the upper part one lattice spacing over, as show in Fig. 16b. Line
defects in devices are undesirable because they act as precipitation sites for metallic
impurities, which may degrade device performance.
Area defects represent a large area discontinuity in the lattice. Typical defects are twins
and grain boundaries. Twinning represents a change in the crystal orientation across a
plane (Fig. 17a). A grain boundary is a transition between crystals having no particular
orientational relationship to one another (Fig. 17b). Such defects appear during crystal
growth. Another area defect is the stacking fault. In this defect, the stacking sequence of
atomic layer is interrupted. In Fig. 18 the sequence of atoms in a stack is ABCABC . . . .
When a part of layer C is missing, this is called the intrinsic stacking fault, Fig. 18a. If an
extra plane A is inserted between layers B and C, this is an extrinsic stacking fault (Fig.
18b). Such defects may appear during crystal growth. Crystals having these area defects
are not usable for integrated-circuit manufacture and are discarded.
Precipitates of impurities or dopant atoms make up the fourth class of defects, the
volume defects. These defects arise because of the inherent solubility of the impurity in
the host lattice.
Fig. 18 Stacking fault in semiconductor. (a) Intrinsic stacking fault. (b)
Extrinsic stacking fault.
EPITAXIAL-GROWTH TECHNIQUES:
In an epitaxial process, the substrate wafer acts as the seed crystal. Epitaxial
processes are differentiated from the melt-growth processes in that the epitaxial
layer can be grown at a temperature substantially below the melting point,
typically 30-40% lower. The common techniques for epitaxial growth are chemical-
vapor deposition (CVD) and molecular-beam epitaxy (MBE).
Chemical-Vapor Deposition
CVD is also known as vapor-phase epitaxy (VPE). CVD is a process whereby an
epitaxial layer is formed by a chemical reaction between gaseous compounds. CVD
can be performed at atmospheric pressure (APCVD) or at low pressure (LPCVD).
Fig. 20 Three common susceptors for chemical vapor deposition: (a) horizontal,
(b) pancake, and (c) barrel susceptor.
analogous to the crucible in the crystal growing furnaces. Not only do they
mechanically support the wafer, but in induction-heated reactors they also serve as
the source of thermal energy for the reaction. The mechanism sf CVD involves a
number of steps: (a) the reactants such as the gases and dopants are transported to
the substrate region, (b) they are transferred to the substrate surface where they
are adsorbed, (c) a chemical reaction occurs, catalyzed at the surface, followed by
growth of the epitaxial layer, (d) the gaseous products are desorbed into the main
gas stream, and (e) the reaction products are transported out of the reaction
chamber.
CVD for GaAs
For gallium arsenide, the basic setup is similar to that shown in Fig. 20a. Since
gallium arsenide decomposes into gallium and arsenic upon evaporation, its direct
transport in the vapor phase is not possible. One approach is the use of As, for the
arsenic component and gallium chloride (GaCI3) for the gallium component. The
overall reaction leading to epitaxial growth of gallium arsenide is
As4 + 4GaCl3 +6H2 + 4GaAs +12HCl (1)
The As, is generated by thermal decomposition of arsine (ASH3):
4AsH3 As4+6H2 (2)
and the gallium chloride is generated by the reaction
6HCl+ 2Ga 2GaCl3+3H2 (3)
The reactants are introduced into a reactor with a carrier gas (e.g., Hz). The gallium
arsenide wafers are typically held within the 650"-850°C temperature range. There
must be sufficient arsenic overpressure to prevent thermal decomposition of the
substrate and the growing layer.
Molecular-Beam Epitaxy
MBE is an epitaxial process involving the reaction of one or more thermal beams of
atoms or molecules with a crystalline surface under ultrahigh-vacuum conditions
̴ 0-8 Pa). MBE can achieve precise control in both chemical compositions and
(1
doping profiles. Single-crystal multilayer structures with dimensions on the order of
atomic layers can be made using MBE, Thus, the MBE method enables the precise
fabrication of semiconductor heterostructures having thin layers from a fraction of a
micron down to a monolayer. In general, MBE growth rates are quite low, and for
GaAs, a value of 1 prn/hr is typical.
A schematic of MBE system is shown in Fig. 24 for gallium arsenide and related III-V
compounds such as AlxGa1-xAs. The system represents the ultimate in film
deposition control, cleanliness, and in-situ chemical characterization capability.
Separate effusion ovens made of pyrolytic boron nitride are used for Ga, As, and the
dopants. All the effusion ovens are housed in an ultrahigh-vacuum chamber (-lo4
Pa). The temperature of each oven is adjusted to give the desired evaporation rate.
The substrate holder rotates continuously to achieve uniform epitaxial layers (e.g.,
+- 1% in doping variations and +-0.5% in thickness variations).
Fig. 24 Arrangement of the sources and substrate in a conventional
molecular-beam epitaxy (MBE) system.
To grow GaAs, an overpressure of As is maintained, since the sticking coefficient of Ga to
GaAs is unity, whereas that for As is zero, unless there is a previously deposited Ga layer. For
a silicon MBE system, an electron gun is used to evaporate silicon. One or more effusion
ovens are used for the dopants. Effusion ovens behave like small-area sources and exhibit a
cose emission, where 8 is the angle between the direction of the source and the normal to
the substrate surface.
MBE uses an evaporation method in a vacuum systems. An important parameter for vacuum
technology is the molecular impingement rate, that is, how many molecules impinge on a
unit area of the substrate per unit time. The impingement rate 4 is a function of the
molecular weight, temperature, and pressure. . The rate can be expressed as
where P is the pressure in Pa, m is the mass of a molecule in kg , k is Boltzmams constant in
J/K, T is the temperature in Kelvin, and M is the molecular weight. Therefore, at 300 K and 10-4
Pa pressure, the impingement rate is 2.7×114 molecules/cm2-s for oxygen (M = 32).
STRUCTURES OF EPITAXIAL LAYERS:
Lattice-Matched and Strained-Layer Epitaxy
For conventional homoepitaxial growth, a single-crystal semiconductor layer is grown on
a single-crystal semiconductor substrate. The semiconductor layer and the substrate are
the same material having the same lattice constant. Therefore, homoepitaxy is a lattice-
matched epitaxial process. The homoepitaxial process offers one important means of
controlling the doping profiles so that device and circuit performance can be optimized.
For example, an n-type silicon layer with a relatively low doping concentration can be
grown epitaxially on an n+-silicon substrate. This structure substantically reduces the
series resistance associated with the substrate.
For heteroepitaxy, the epitaxial layer and the substrate are two different
semiconductors, and the epitaxial layer must be grown in such a way that an idealized
interfacial structure is maintained. This implies that atomic bonding across the interface
must be continuous without interruption. Therefore, the two semiconductor must either
have the same lattice spacing or be able to deform to adopt a common spacing. These
two cases are referred to as lattice-matched epitaxy and strained-layer epitaxy. Figure
25a shows a lattice-matched epitaxy where the substrate and the film have the same
lattice constant. For the lattice-mismatched case, if the epitaxial layer has a larger lattice
constant and is flexible, it will be compressed in the plane of growth to conform to the
substrate spacing. Elastic forces then compel it to dilate in a direction perpendicular to
the interface. This type of structure is called strained-layer epitaxy and is illustrated in
Fig. 25b. On the other hand, if the epitaxial layer has a smaller lattice constant, it will be
dilated in the plane of growth and compressed in a direction perpendicular to the
Fig. 25 Schematic illustration of (a) lattice-matched, (b) strained, and (c)
relaxed heteroepitaxial structures.
In the above strained-layer epitaxy, as the strained-layer thickness increases, the
total number of atoms under strain or the distorted atomic bonds grows, and at
some point misfit dislocations are nucleated to relieve the homogeneous strain
energy. This thickness is referred to as the critical layer thickness for the system.
Figure 25c shows the case in which there are edge dislocations at the interface.
Defects in Epitaxial Layers:
Defects in epitaxial layers will degrade device properties. For example, defects can
result in reduced mobility or increased leakage current. The defects in epitaxial
layers can be categorized into five groups.
1. Defects from the substrates. These defects may propagate from the substrate
into the epitaxial layer. To avoid these defects, dislocation-free semiconductor
substrates are required.
2. Defects from the interface. The oxide precipitates or any contamination at the
interface of the epitaxial layer and substrate may cause the formation of
misoriented clusters or nuclei containing stacking faults. These clusters and
stacking faults may coalesce with normal nuclei and grow into the film in the
shape of an inverted pyramid. To avoid these defects, the surface of the substrate
must be thoroughly cleaned.
3. Precipitates or dislocation loops. Their formation is due to supersaturation of
impurities or dopants. Epitaxial layers containing very high intentional or
unintentional dopants or impurity concentrations are susceptible to such defects.
Fig. 27 Illustration of the elements and formation of an strained-layer
superlattice. Arrows show the direction of the strain.
4. Low-angle grain boundaries and twins. Any misoriented areas of an epitaxial film
during growth may meet and coalesce to form these defects.
5. Edge dislocations. These are formed in the heteroepitaxy of two lattice-
mismatched semiconductors. If both lattices are rigid, they will retain their
fundamental lattice spacings, and the interface will contain rows of misbonded
atoms described as misfit or edge dislocations. The edge dislocations can also
form in a strained layer when the layer thickness becomes larger than the critical
layer thickness.
MOSFET TECHNOLOGY
At present, the MOSFET is the dominant device used in ULSI circuits because it can
be scaled to smaller dimensions than other types of devices. The dominant
technology for MOSFET is the CMOS (complementary MOSFET) technology, in
which both n-channel and p-channel MOSFETs (called NMOS and PMOS,
respectively) are provided on the same chip. CMOS technology is particular
attractive for ULSI circuits because it has the lowest power consumption of all IC
technology. Figure 14 shows the reduction in the size of the MOSFET in recent
years. In the early 1970s, the gate length was 7.5 μm and the corresponding device
area was about 6000 μm2. As the device is scaled down, there is a drastic reduction
in the device area. For a MOSFET with a gate length of 0.5 μm , the device area
shrinks to less than 1% of the early MOSFET.
The Basic Fabrication Process
To process an n-channel MOSFET (NMOS), the
starting material is a p-type, lightly doped (~1015
cm-3), [100]-oriented, polished silicon wafer. The
100)-orientation is preferred over [111] because it
has an interface-trap density that is about one-
tenth that of [111]. The first step is to form the
oxide isolation region using LOCal Oxidation of
Silicon (LOCOS) technology. A thin-pad oxide ( 3 ̴ 5
nm) is thermally grown, followed by a silicon nitride
(1̴ 50 nm) deposition (Fig, 16a). The active device
area is defined by a photoresist mask and a boron
chanstop layer is then implanted through the
composite nitride-oxide layer (Fig. 16b), The nitride
layer not covered by the photoresist mask is
subsequently removed by etching. After stripping
the photoresist, the wafer is placed in an oxidation
Fig. 14 Reduction in the area of the furnace to grow an oxide (called the field oxide),
MOSFET as the gate length is reduced. where the nitride layer is removed, and to drive in
the boron implant. The thickness of the field oxide
is typically 0.5-1 μm.
Fig. 16 Cross-sectional view of NMOS fabrication sequence (a) Formation of SiO2, Si3N4, and photoresist
layer, (b) Boron implant, (c) Field oxide, (d) Gate.
The second step is to grow the gate oxide and to adjust the threshold voltage. The composite
nitride-oxide layer over the active device area is removed, and a thin-gate oxide layer (less
than 10 nm) is grown, For an enhancement-mode n-channel device, boron ions are implanted
in the channel region, as shown in Fig, 16c, to increase the threshold voltage to a
predetermined value (e,g,, + 0.5V). For a depletion-mode n-channel device, arsenic ions are
implanted in the channel region to decrease the threshold voltage (e.g,, -0,5V), The third step
is to form the gate, A polysilicon is deposited and is heavily doped by diffusion or implantation
of phosphorus to a typical sheet resistance of 20-30 Ohm/sq.. This resistance is adequate for
MOSFETs with gate lengths larger than 3 μm. For smaller devices,
polycide, a composite layer of metal silicide and polysilicon such as W-polycide, can
be used as the gate materials to reduce the sheet resistance to about 1 Ohm/sq..
The fourth step is to form the source and drain. After the gate is patterned (Fig.
̴ 0 keV, ̴5 x 1015 to form the
16d), it serves as a mask for the arsenic implantation ( 3
source and drain (Fig. 17a), which are self-aligned with respect to the gate7. At this
stage, the only overlapping of the gate is due to lateral straggling of the implanted
ions. If low-temperature processes are used for subsequent steps to minimize
lateral diffusion, the parasitic gate-drain and gate-source coupling capacitances can
be much smaller than the gate-channel capacitance.
The last step is the metallization. A phosphorus-doped oxide (P-glass) is deposited
over the entire wafer and is flowed by heating the wafer to give a smooth surface
topography (Fig. 17b). Contact windows are defined and etched in the P-glass. A
metal layer, such as aluminum, is then deposited and patterned. A cross-section
view of the completed MOSFET is shown in Fig. 17c, and the corresponding top view
is shown in Fig. 17d. The gate contact is usually made outside the active device area
to avoid possible damage to the thin-gate oxide.
Fig. 17 NMOS fabrication sequence. (a) Source and drain. (b) P-glass deposition. (c) Cross
section of the MOSFET. (d) Top view of the MOSFET.
