Department of Electrical Engineering

ELEC261 - Digital Systems Design

FPGA Briefing

ELEC261
&
VHDL: The Very Basics

Lecture 6 Prof. F Bensaali

FPGA Briefing

2
Content:
• What is an FPGA
• Traditional FPGA structure
• Basic logic blocks
• Look-up table functionality
• FPGA programming

3
 What is
What is an
an FPGA?
FPGA?

 Field Programmable Gate Array

 An FPGA is a silicon chip device

 The FPGA is made up of an array of logic blocks

 The blocks can be configured and connected together by a

user to create an electronic circuit

4
 What is
What is an
an FPGA?
FPGA? (Cont’d)
(Cont’d)

FPGA Chip FPGA Development Board

5
 Implementation approaches
Implementation approaches

 There are a wide range of computing applications

 Each application is best served by a different approach:
o Off-the-shelf microprocessors (MPUs) and microcontrollers
(MCUs)
o Off-the-shelf graphics processing units (GPUs)

o FPGAs
o Application Specific Integrated
Circuits (ASICs): a set of electronic
circuits on a single small chip designed
for a specific use or application
6
7
 Implementation approaches
Implementation approaches (Cont’d)
(Cont’d)

ASIC Designed all the way from No physical layout design; FPGA
Application Specific behavioral description to design ends with a bitstream Field Programmable
Integrated Circuit physical layout used to configure the FPGA Gate Array

Design must be sent for

Bought off-the-shelf and
expensive and time
reconfigured by designers
consuming fabrication in
themselves
semiconductor foundry

ASICs FPGAs
Off-the-shelf

Low development
High performance
cost
Short time to
Low power
market
Low cost in high
Reconfigurability
volumes

8
 FPGA vendors
FPGA vendors

 SRAM-based FPGAs
o Xilinx, Inc.
Share over 60% of the market
o Altera Corp.
o Atmel
o Lattice Semiconductor

 Flash & antifuse FPGAs

o Actel Corp.
o Quick Logic Corp.

9
 Traditional FPGA
Traditional FPGA Structure
structure

Logic Block Input/Output Cell

 An FPGA generally consists of:

o A matrix of programmable logic

blocks or Logic Elements(LE)

o I/O cells, which connect the logic

cells to external signals

o A programmable routing network

interconnecting the cells
Routing
Network

10
 Basic logic
Basic logic blocks
blocks

a y
b 4-input MUX
c LUT
d
Q
e Flip-flop/
latch
f
clock
enable
set/reset

 A typical FPGA has a logic block with:

o One or more 4-input Look-up Table (LUT)

o Flip-Flops (FFs)

 FFs can be used for pipelining, registers, or any other situation

where clocking is required (i.e., sequential circuits) 11
 Look-Up Tablefunctionality
Look-up table functionality

 LUTs are primary elements for logic implementation

 Each LUT can implement any function of 4 inputs

I1
I2
I1 I2 I3 I1 O
I3 0 0 0 0 0
I4 0 0 0 1 1
I1 0 0 1 0 0
I2 0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
O
1 0 0 1 1
1 0 1 0 0
I1
1 0 1 1 0
I2 1 1 0 0 1
4-LUT O
I3 1 1 0 1 1
I4 O 1 1 1 0 0
1 1 1 1 0

12
 Look-Up Tablefunctionality
Look-up table functionality(Cont’d)
(Cont’d)
RAM16x1S
 Each LUT can be configured I1
D
WE

as a 16 by 1-bit RAM, which I2

I3 4-LUT O
= A0 O

is called distributed RAM I4

A1
A2
A3

o Available anywhere
across the user circuit I4 I3 I2 I1 I4 I3 I2 I1

 Two LUTs can be combined 4-LUT 4-LUT

to create:
o 16 by 2-bit RAM O O

=
o 32 by 1-bit RAM RAM32x1S RAM16x2S RAM16x1D
D D0 D
WE D1 WE
WE
A0 O0
A1 O A0 O1 A0 SPO
A2 A1 A1
A3 A2 A2
A4 A3 A3

DPA0 DPO
DPA0
DPA0
DPA0

I3 I4 13
 Extra features
Extra features

 Dedicated memory blocks. These complement the distributed

RAMs implemented using logic cells
o Each Block RAM is a synchronous dual-ported RAM with
independent control signals for each port

 Dedicated hardware blocks (e.g., multipliers)

o More efficient than their synthesised counterparts

 Embedded microprocessor core (e.g., PowerPC)

14
 FPGADesign
FPGA design Flow
flow

Design Entry
e.g., VHDL, Schematic No

Design
Synthesis Correct
No

Yes
Functional Simulation Design
Correct

Place & Route /

Fitting Yes

Timing Analysis and

Simulation

Configuration

15
 FPGADesign
FPGA design Flow
flow (Cont’d)
(Cont’d)

 Design Entry – the desired circuit is described using schematic

or/and a hardware description language (e.g., VHDL)
 Synthesis – the entered design is synthesized into a circuit that
consists of LEs provided in the FPGA chip
 Functional Simulation – the synthesized circuit is tested to
verify its functional correctness
 Place & Route/Fitting – this tool determines the placement of
the LEs defined during synthesis into the LEs in an actual FPGA
chip
o It also chooses routing wires in the chip to make the required
connections between specific LEs
o Each FPGA vendor has its own fitting tools

16
 FPGA design flow (Cont’d)

 Timing Analysis – propagation delays along the various paths in

the fitted circuit are analyzed to provide an indication of the
expected performance of the circuit
 Timing Simulation – the fitted circuit is tested to verify both its
functional correctness and timing
 FPGA Configuration – Once the fitting operation has been
successfully performed, a bitstream file can be generated
o The bitstream file contains all the FPGA configuration
information
o This file can be used for FPGA configuration

17
 Hardware/Software
Hardware/Software to
Teaching (Cont’d) to be
be Used
used

Software
 Intel Quartus Prime Design Suite
(Lite Edition) is the software to be
used in all labs for this course

Hardware
 The Cyclon V GX Starter kit is the
hardware to be used for the remaining
labs

Cyclon V GX Starter kit

18
 Intel
Intel Quartus
Quartus Prime–
Prime– FPGA
FPGA Project
Project

FPGA Project

VHDL Schematic (Logic Diagram)

Functional /timing
simulation Components from
Altera libraries

19
 Intel
Intel Quartus
Quartus Prime–
Prime– Schematic
Schematic

Quartus Prime Graphic Editor

Can be Described
using VHDL

20
VHDL: The Very Basics

21
Content:
• What is VHDL?

• VHDL design units

• VHDL data types

• VHDL conventions, reserved words and

comments

• VHDL operators

22
 What is
What is VHDL?
VHDL?

 HDL: Hardware Description Language

o Most used: VHDL, Verilog

 VHDL : Very high-speed integrated circuit

 Originally developed for the US Department of Defense, first

released in 1987 as an IEEE standard (VHDL-87), last major
revision VHDL-2019 (Sep 2019)

 A technology independent, standard language for describing

digital electronic systems

23
 VHDL design
VHDL design units
units

 “Design Units” are used to describe logic

Design Units

Defines the names, input/output signals of a

Entity
hardware module

Architecture Describes a particular implementation of an entity

Package Allows a convenient way to define and group

declaration functions, procedures, types, components, etc.

Contains the implementation of the functionality

Package body exposed by package declaration

24
 VHDL design units (Cont’d)
The entity

Libraries &  Libraries and packages provides the

incorporation of external functions, data types
packages and components to the circuit to be described

Entity  Defines the I/O ports as well as the name of the

I/O component

 It is where the hardware behavior and/or

Architecture structure is described
Functionality

25
 The entity
The entity

Libraries &  A black box, this defines the circuit’s

packages Input/Output ports

Entity  Ports are interfaces through which an

I/O entity can communicate with its
environment

Architecture
Functionality

26
Entity declaration
Entity declaration (Cont’d)
(Cont’d)

A
B
1
1
2:1 4:1
0 X
MUX MUX
C
0

27
 Entity declaration
Entity declaration
Entity name Port names

Port type
ENTITY Ahmad IS
PORT(
A A: IN Bit;
Ahmad C B: IN Bit;
Semicolon
B C: OUT Bit
);
END Ahmad; No semicolon

Port modes
 Simplified syntax:
ENTITY entity_name IS
PORT(
port_name: signal_mode signal_type;
port_name: signal_mode signal_type;
………
port_name: signal_mode signal_type
);
END entity_name;

28
 TheThe
architecture
entity

Libraries &
packages
Entity  Describes what the circuit actually does
I/O o Internal implementation

Architecture
Functionality

29
 The The
architecture (Cont’d)
architecture

Architecture name Entity name

Ahmad architecture And_arch of Ahmad is

A begin
C C <= A and B;
B
end AND_arch;

 Simplified syntax:

ARCHITECTURE arch_name of entity_name is

[declarations]
BEGIN [ ] used for optional parts
code
END architecture_name;

30
Entity declaration
Entity declaration &
& architecture
architecture -- Example
Example

entity Ahmad is
port( A: in Bit;
Ahmad B: in Bit;
C: out Bit
);
A end Ahmad;
C
B architecture AND_arch of Ahmad is
begin
C <= A and B;
end AND_arch;

31
 Libraries, packages
Libraries, packages &
& package
package bodies
bodies

Libraries &  VHDL library files allow the storage of

commonly used packages that can be
packages used in VHDL programs. There are two
types:
Entity
I/O o Standard library: used to store predefined
packages
o User-defined library: holds user-defined
Architecture packages
Functionality

32
 Libraries, packages
Libraries, & package
packages bodies
& package (Cont’d)
bodies

library library_name;
use library_name.package_name.package_part;

 USE The keyword LIBARARY makes the packages contained in

the library_name libarary available or visible to the VHDL program
 The keyword identifies what is to be used from the library

Example

library ieee;
use ieee.std_logic_1164.all;

33
 Libraries, Packages
packages &
& package
package bodies
bodies (Cont’d)
 Packages hold reusable code such as LIBRARY
components, functions and procedures and PACKAGE 1 PACKAGE 2
to make them available to VHDL program Types Types
Constants Constants
o Can be defined by the user or supplied by an Functions Functions
Procedures Procedures
outside source in the form of standard Components Components
packages

package user-defined name is

package declarations
end package user-defined name

 The package body is where the items listed in the package

declaration are defined

package body user-defined name is

package body definitions
end package body user-defined name
34
Library declaration
Library declaration -- Example
Example
AND Gate
A
C
B

library ieee;
use ieee.std_logic_1164.all;
entity AND_ent is Use all definitions from the
port( A: in Bit; package std_logic_1164
B: in Bit;
C: out Bit
);
end AND_ent;
architecture AND_arch of AND_ent is
begin
C <= A and B;
end AND_arch;

35
 Data objects
Data objects &
& identifiers
identifiers

 Four Classes of Data objects:

o Constant: Holds a single value of a given type

o Variable: Holds a value of a given type where a value of
same type can be assigned
o Signal: Used to define a data pathway between two
functional units
o File: Contains a sequence of value of one or more types
 Used for simulation only
 Identifiers are used as variable, signal or constant names,
as well as names of design units (entities, architectures, etc.)

36
 Data objects
Data objects declaration
declaration

Constant

constant constant_name : type := value;

Variable

variable variable_name : type [ := initial_value ];

Signal

signal signal_name : type [ := initial_value ];

37
 Data types
Data types

The type of a signal, variable, or constant

Data Types
object specifies the range of values it may
take and the set of operations that can be
Access performed on it

Composite

Array Reccords

Scalar

Physical Real Integer Enumerated

38
 Data types
Data types (Cont’d)
(Cont’d)
 CHARACTER - one of the ASCII set
 BOOLEAN - can be FALSE or TRUE
 BIT – can be '0' or ‘1’
 STD_LOGIC - signal or variable of this type can take on the
following values:
'U': uninitialized. This signal hasn't been set yet
'X': unknown. Impossible to determine this value/result
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care
39
 Data types
Data types (Cont’d)
(Cont’d)

 An array of type BIT is called a BIT_VECTOR

 e.g., signal MYSIG : bit_vector(0 to 3); -- in architecture
 An array of type STD_LOGIC is called a STD_LOGIC_VECTOR
 e.g., A: out std_logic_vector(31 downto 0); -- in entity
 A STRING is a character array
 e.g., Constant GREETING : string := "Hello!";

Signal a: STD_LOGIC; Signal b: STD_LOGIC_VECTOR(7 DOWNTO 0);

a b

1 8
wire bus

40
 Data types
Data types (Cont’d)
(Cont’d)

Examples
signal: X std_logic_vector(3 downto 0):= "0000";
or
signal: X std_logic_vector(3 downto 0):= (others =>'0');

X is initially "0000"

signal X: std_logic_vector(0 to 3) := (0 => '1', others => '0');

signal Y: std_logic_vector(3 downto 0) := (0 => '1', others => '0');

X is initially "0001" and Y is initially "1000"

41
 Port modes
Port modes

 IN means input-ONLY
o You cannot use a mode IN signal on the LEFT of an
equation (you cannot assign a new value to INPUTS)

 OUT means output-ONLY

o You cannot use a mode out signal on the RIGHT side of
an equation (you cannot “use” the OUTPUTS)

 INOUT means bi-directional

o Like a three-state bus, for example. This type of signal
may appear on the left OR right side of equations

42
 Port modes
Port modes (Cont’d)
(Cont’d)

Exercise
Write the VHDL code (Entity part) to implement the
following 4:1 multiplexer:

D0
8
D1
8 Mux_4to1 D_out
D2 8
8 Entity??
D3
8

2
SEL

43
 Port modes
Port modes (Cont’d)
(Cont’d)

Solution

entity mux_4to1 is

D0 port ( D0: in std_logic_vector(0 to 7);

8
D1 D1: in std_logic_vector(0 to 7);
8 Mux_4to1 D_out D2: in std_logic_vector(0 to 7);
D2 8 D3: in std_logic_vector(0 to 7);
8
D3
8 SEL: in std_logic_vector(0 to 1);

2 D: out std_logic_vector(0 to 7)
SEL );
end mux_4to1;

44
 Conventions –– naming
Conventions naming and
and labelling
labelling

 VHDL is not case sensitive

Example
and_gate
AND_GATE
AND_Gate

are all equivalent

45
 Conventions –– naming
Conventions naming and
and labelling
labelling (Cont’d)
(Cont’d)

 General rules:

1. All names should start with an alphabet character (a-z or

A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and
underscore (_)
3. Do not use any punctuation or reserved characters within
a name (!, ?, ., &, +, %, etc.)
4. Do not use two or more consecutive underscore
characters (__) within a name
5. All names and labels in a given entity and architecture
must be unique

46
 Conventions –– free
Conventions free format
format

 VHDL is a “free format” language

o Space and carriage return are treated the same way

Example

if (a=b) then

or

if (a=b) then
are all equivalent
or

if (a =
b) then

47
 Comments
Conventions – comments

 Comments in VHDL are indicated with a “double dash” “--”

o Comment indicator can be placed anywhere in the line
o Any text that follows in the SAME line is treated as a comment
o Carriage return terminates a comment

Example

-- this is an example
Data_in <= Data_bus; -- reading data from the bus

48
 Reserved
Conventions words words
– reserved
 Reserved words are keywords that have a predefined meaning
in the language
o They are essential for the syntax and functionality of VHDL code
o You cannot use these as identifiers
Example
acces exit mod return while
after file new signal with
alias for next shared
all function null then
attribute generic of to
block group on type
body in open until
buffer is out use
bus label range variable
constant loop rem wait
49
 Exercise
Conventions – exercise

Find the errors in the following VHDL code and correct them.

library ieee;
use ieee.std_logic_1164.all;
-- This is a 2-input
Or gate
entity 2_OR_GATE is
port( A: in std_logic;
B: in std_logic;
C: out std_logic;
);

architecture behavioral of 2_OR_GATE is

begin
C <= a or B;
end behavioral;

50
 Solution
Conventions – solution

library ieee;
use ieee.std_logic_1164.all;
-- This is a 2-input
Or gate
entity 2_OR_GATE is
port( A: in std_logic;
B: in std_logic;
C: out std_logic;
);
End missing

architecture behavioral of 2_OR_GATE is

begin
C <= a or B;
end behavioral;

51
 Operators
Operators
 Operators are used in expressions involving signal, variable, or
constant object types
Logical Operators Relational Operators Assignment Operators
Symbol Function Symbol Function Symbol Function

and Logical and = Test for Equality Assignment of

<=
signals
nand Logical nand /= Test for Inequality
Assignment of
or Logical or < Less than :=
variables
nor Logical nor <= Less than or equal
> Greater than
<= is also a relational operator
xor Logical xor
xnor Logical xnor >= Greater than or equal

Shift Operators
Multiplying Operators Addition Operators
Symbol Function Symbol Function Symbol Function
sll Logical left shift * Multiplication + Addition
srl Logical right shift / Division
- Subtraction
sla Arithmetic left shift mod* Modulus
& Concatenation
sra Arithmetic right shift rem* remainder
rol Rotate left logical *check YouTube video under ‘Online Resources’
ror Rotate right logical

52
 Operators (Cont’d)
Operators (Cont’d)

Example

 Let A="1100", B="1110"

Example expression Result

Value <= A and B "1100"

Value <= A & B "11001110"
Value <= (A & B) sll 2 "00111000" -- shift left logical, filled with ‘0’
Value <= (A & B) srl 3 "00011001" -- shift right logical, filled with ‘0’
Value <= (A & B) rol 2 "00111011"
Value <= (A & B) sra 3 "11111001" -- shift right arithmetic,
filled with left bit (MSB)

53