2024 IEEE EDKCON, 30th Nov -1st Dec 2024, Kolkata, India

A Low Leakage Variations and High Stability 9T

SRAM Cells
Guguloth Anjaneyulu M Durga Prakash
Department of ECE Department of ECE
School of Engineering and Sciences School of Engineering and Sciences
SRM University AP SRM University AP
Andhra Pradesh, India Andhra Pradesh, India
guguloth a@srmap.edu.in durgaprakasah.m@srmap.edu.in

Mukku Pavan Kumar Shams UI Haq

Electrical Engineering Department of ECE
IIT Gandhinagar Jamia Millia Islamia
Gujarat, India Jamia Nagar, New Delhi, India
pavansudarshi@gmail.com shamsulhaq034@gmail.com

Abstract—This paper introduces an alternative NLP-9T/PLP- consumption, such as bio-medical devices, battery-operated
9T SRAM cell designs that demonstrates improved stability devices, and wireless sensor devices, face a significant chal-
and low leakage power variations at worst case analysis. The lenge in reducing leakage current in the presence of low
suggested SRAM cells mitigate read disturbances by deactivating
the access transistors within the memory cell. Moreover, the voltage and process changes [5]. Thus far, several enterprises,
inclusion of extra PMOS read access transistors along the bitlines academics, and researchers have proposed various design ideas
helps to ensure a successful read operation. The results indicate as alternatives to using a pre-existing 6T-SRAM cell. However,
that the suggested PLP-9T memory cell exhibit stability that is a persistent challenge arises in striking a balance between the
1.31 times greater than 6T-SRAM, 1.05 times higher than CONV- instability and performance of memory cells.
8T, 1.27 times higher than WU-Z8T, 1.25 times higher than
LIU-D10T, and 1.022 times higher than the proposed NLP-9T Several literature articles offer a concise overview of other
memory cells. Furthermore, the proposed cells in standby mode design alternatives for the current 6T-SRAM system. One of
effectively limits leakage power, even under the most adverse the design options for low power applications is the deteriora-
process fluctuations. However, the suggested NLP-9T/PLP-9T tion of its supply voltage [6]–[10]. However, this results in a
design takes about 1.7 times/1.3 times more layout area than decrease in the cell performance. Alternative approaches, such
the traditional 6T-SRAM.
Index Terms—Failure probability, leakage Power, monte-carlo
as single-ended schemes and read/write decoupled systems,
analysis, PVT analysis, read access transistors, robust SRAM. have been shown to suffer from bitline leakage caused by
inadequate noise immunity of the array [11]–[16]. Several
I. I NTRODUCTION read or write-back techniques can be used as a solution for
low-power applications. However, it is important to note that
VLSI chip designers included memory chips into CPUs to these schemes are also affected by bigger layout regions and
address the bottleneck problem associated with Von-Neuman process changes, which in turn impact the stability of the cell.
architecture. On-chip cache memories are often constructed The separate transistors for bitline access and buffer functions
using SRAM circuits rather than DRAMs due to their superior are added to the other additional node, in order to improve
characteristics of high-speed data retention and reduced charge the performance. This leads, the capacitance of the bitline is
leakage across the storage nodes. Based on the ITRS, the increased, which in turn leads to a further rise in the data
memory area occupancy in a SoC exceeds 96% because of retention time of the memory cell.
the need for larger storage capacity. Consequently, designers This study proposes the use of an NMOS-low power 9T
reduce the size of transistors and increase the number of (NLP-9T) and PMOS low power 9T (PLP-9T) to address
memory arrays inside a given space. This causes the stability the shortcomings in existing SRAM design methodologies
of the memory to degrade under process variations thereby related to low leakage and high stability at worst-case scenario.
yield of read and write failure increases [1], [2]. Isolating the bitline voltages from the storage nodes during the
However, the usage of scaled MOS transistors in the SRAM read operation will improve the read static noise margin by
array leads to a significant rise in leakage current compared to including extra PMOS buffer transistors alongside the driver
active current. This is mostly because the majority of memory transistors. The access transistors of the NLP-9T and PLP-
cells in the design remain in an idle state [3], [4]. Mod- 9T designs are made using NMOS and PMOS, respectively.
ern applications that need high performance and low power PLP-9T is crucial in enhancing the stability curve’s zeroth line

979-8-3503-7464-3/24/$31.00 ©2024 IEEE

margin. Furthermore, including an extra NMOS transistor with stability of the memory cell. The author included two NMOS
read access into the driver transistors lowers the memory cell’s transistors in parallel with the bitline to facilitate data access in
leakage power. read mode, and employed regular NMOS access transistors for
The structure of the paper is as follows: Section II pro- write analysis. The use of the super cut-off system across the
vides an brief overview of the current advanced and efficient tail transistor reduces leakage fluctuations when the memory
SRAM designs, along with their merits and demerits. Section cell is in a hold state. The problem with this design lies is its
III presents the suggested designs for NLP-9T and PLP-9T lower write stability and write failure probability during worst
SRAM, along with their fundamental functioning using a 1- case analysis.
bit thin-cell layout and transient simulations. Additionally, Based on the evaluation of the aforementioned dependable
Section IV covers simulations and discussions focused on and advanced SRAM cell designs, we have introduced an
performance analysis. Section V is conclusion. alternative NLP-9T and PLP-9T SRAM cell that enhances
stability and minimizes the zeroth line margin. Furthermore,
II. E XISTING R ELIABLE SRAM D ESIGNS employing PMOS as the access and read buffer network
In this section, a conventional 6T-SRAM [17] along with results in a decrease in leakage power during ideal condition
reliable SRAM cells for low leakage and high stability are and reduces process fluctuations, particularly at low supply
considered i.e. CONV-8T SRAM cell [18], WU-Z8T SRAM voltages.
cell [19], and LIU-D9T SRAM cell [20]. All the simulations
of the proposed SRAM cells are compared with these reliable III. P ROPOSED NLP/PLP-9T SRAM C ELL W ORKING AND
SRAM cells. I TS A NALYSIS
In the conventional 6T-SRAM cell read operation, the stored An NMOS access transistors low power 9T (NLP-9T) and
data is affected by voltage division across the back-to-back PMOS access transistors low power 9T (PLP-9T) SRAM cells
inverters. Moreover, it is susceptible to decreasing the noise is offered as an alternative for the demerits of the mentioned
immunity across the stored nodes as a result of direct access existing SRAM cells.
transistors connection to read/write the data. To ensure optimal The Fig. 1(a) and (b) shows the proposed NLP-9T and PLP-
stability, it is necessary to take into account differences in 9T schematics, further Fig. 1(c) and (d) shows the 1-bit thin-
the size of the transistor in the circuit. The size of the cell layouts of the respective cells. The NLP-9T design, as
array’s resulting region is enlarged. Furthermore, when supply shown in Fig. 1(a), has NMOS access transistors MN4 and
voltages are reduced, the stability and leakage fluctuations of MN5, which are regulated by the wordline (WL) to enable data
lowest sized transistors are affected. Therefore, the current 6T- writing. Additionally, MP3 and MP4 refer to PMOS access
SRAM is not ideal for low power applications. transistors that are regulated by stored data Q and QB. The
The author Liang et al. [18] introduced an 8T-SRAM cell. transistor MN3 functions as a source for discharging the data
This cell consists of regular 6T-SRAM cell and two additional on the bitlines during the write mode. In order to enable read
read decoupled transistors (RDT) that function as a read mode, MN3 needs to be disabled via the CSL control signal.
enhanced buffer network. The RDT’s are governed by the The schematic design of PLP-9T, as shown in Fig. 1(b),
storage node QB and an extra Read Word Line (RWL) row- includes MP3 and MP4 PMOS access transistors. These tran-
based signal. When activate RWL signal leads to enhance sistors are controlled by the wordline (WL) and are enable for
the read stability of the cell and deactivate the Word Line writing data. In addition, MP5 and MP6 serve as PMOS read
(WL) signal. Subsequently, RBL will handle the process of access transistors that are regulated by the stored data Q and
either charging or discharging the voltage. However, the major QB. In the read mode, transistor MN3 functions as a source
problem is its leakage current in the bitline when the cell reads to discharge the data on the bitlines. To disable the writing
a logic 0 at lower supply voltages. This results in a decrease mode, MN3 can be deactivated using the CSL control signal.
in the ratio between the on state and the off state current. The corresponding transistors widths of the proposed NLP-
The author WU et al. [19] introduced a novel 8T SRAM 9T and PLP-9T are considered as follows: The MN3, MP3
cell design, which successfully resolves the read and write and MP4 transistors in NLP-9T are 2x times larger than other
problems encountered in previous designs. This is achieved by mentioned transistors dimension. Whereas in PLP-9T MN3,
using decoupled NMOS transistors and distinct read bitlines. MP5 and MP6 are 2x times larger than other transistor to
These transistors are regulated by the storage nodes of the achieve strong storage values.
memory cell. Partitioning the bitlines to enhance read and
write capabilities results in improved noise margins compared A. Proposed NLP-9T and PLP-9T SRAM Cells Working
to the typical 6T design. However, this modification leads to If a logic 1 data is stored in a cell, then Q will have a value
increased data retention time and active power consumption, of 1 and the complementary output QB will hold a value of 0.
as well as increased power consumption during read and write When we write the stored data to logic 0, the wordline must
operations. Furthermore, concerns with half-select and leaking be in an enabled state, meaning WL=VDD for NLP-9T and
power emerge. WL=0 for PLP-9T. In this instance, the control signal (CSL)
The author LIU et al. [20] introduced a 9T SRAM cell that is deactivated for both of the SRAM cells. In addition, the
successfully resolves leakage problem and enhances the read bitline (BL) is set to a ground voltage while the BLB is set
 WL WL

VDD VDD

MP1 MP2 MP1 MP2

Q Q
MN4 QB MP3 QB
MN5 MP4
MN1 MN2 MN1 MN2

MP3 MP4 MP5 MP6

BL BLB BL BLB
CSL MN3 CSL MN3

GND GND

a) b)

c) d)

Fig. 1. Proposed memory cells a) NLP-9T schematic b) PLP-9T schematic c) 1-bit thin-cell layout of NLP-9T d) 1-bit thin-cell layout of PLP-9T

to a VDD voltage in order to store a logic 0 in the cell. The IV. P ERFORMANCE ANALYSIS S IMULATIONS &
stored data is changed from logic 1 to 0 by forcing logic 0 via D ISCUSSIONS
the enable access transistor. Similarly, the process described The performance parameters simulations of both the pro-
above may be applied to write the stored data as a logic 1. posed and existing SRAM cells were confirmed by post-layout
simulations in a 45nm CMOS bulk technology node. The
In read operation, the bitlines are charged to the supply simulations were conducted using a standard supply voltage
voltage, the wordline is deactivated, and the control signal is of 1V and a room temperature of 27°C. The performance of
in activate state. If logic 0 state is at memory cell, the voltage the proposed NLP-9T and PLP-9T SRAM cells was evaluated
across the bitline (BL) begins to decrease as it discharges by comparing them with existing 6T-SRAM, CONV-8T, WU-
through MP3 to MN3 in the NLP-9T design and MP5 to Z8T, and LIU-D9T SRAM cells. The size of transistors are
MN3 in the PLP-9T design. The minimum potential difference examined in relation to the existing SRAM cells.
detected by sense amplifier and provide required logic state. A. Static Noise Margin Analysis
The primary benefit of deactivating the wordline during the
read operation is the direct isolation of disturbances in the The static noise margin (SNM) is a crucial parameter for
storage nodes via the bitlines. This leads to the emergence assessing the stability of a memory cell against external noise
of robust logical values throughout the storage nodes, hence interference on the storage nodes [21]. The term SNM is
enhancing the stability of the memory cell [20]. defined as minimum external noise voltage required to upset
the stored data of a memory cell [20], [22]. In order to produce
a butterfly curve, a constant DC external voltage injected at
In hold operation, the wordline (WL) and control signal the Q and QB, which is sweep from 0 to vdd and observe the
(CSL) are deactivated. Suppose the cell holds 0, the MP2 voltage transfer curve across it. The RSNM is determined by
transistor is in an active mode and QB charges to the VDD measuring the greatest square which equip within the small
voltage. This results in the occurrence of MN1 when the ON lobe voltage differential of a butterfly curve.
condition is met, and the memory cell remains in a logic 0 We conducted a comprehensive examination of all exist-
state. ing available and suggested SRAM cells’ Read Static Noise
Fig. 2. Read stability comparison (a) RSNM at constant VDD (b) RSNM at various VDD (c) RSNM at different process corners (d) WSNM at constant
VDD (e) WSNM at various VDD (f) WSNM at different process corners

Margin (RSNM) under a consistent 1V power supply and the TT corner at room temperature. Figure 2(d) shows all
at a typical-typical (TT) process corner, while maintaining mentioned memory cells WSNM. Among all cells, NLP-9T
ambient temperature. Figure 2(a) shows the RSNM of all has the highest WSNM of all memory cells due to its robust
mentioned memory cells. Due to weak storage node value at stored data writing process. WSNM values vary slightly for the
QB, conventional 6T SRAM shows lower RSNM. The CONV- 6T-SRAM, CONV-8T, PLP-9T, and NLP-9T. The LIUD9T has
8T SRAM incorporated supplementary read stable circuitry a lower WSNM due to adding an extra write path and NMOS
along QB by isolating the read analysis with RWL and RBL transistors MN5 and MN6 to the WU-Z8T cell. Additionally,
control signals. This leads to an increase in the RSNM of the we tested all memory cells WSNM with different supply
memory cell. However, it also causes additional read latency in voltage and process corner adjustments. The recommended
the separation of the bitlines. In the Zig-Zag 8T design (WU- NLP-9T operates well even with lower VDD values. WSNM
Z8T), the author implemented a novel method including two scores are highest for Fast-Slow corners (FS) and lowest for
distinct NMOS read decoupled transistors that are activated Slow-Fast corners (SF).
and regulated by storage nodes. This technique was employed
B. Read and Write Access Time Analysis
to enhance the RSNM compared to the 6T-SRAM design,
although it did not surpass the performance of the CONV- We measured all mentioned memory cells read and write
8T design. However, WU-Z8T demonstrates that there are delay/access time under the variations of vdd and process
no issues with read stability process fluctuations, even when corners. Out of all the memory cell read delays, the CONV-8T
operating at a lower supply voltage, as shown in Fig. 2(b) exhibits the least delay because it has a single, separate access
and (c). we implemented a PMOS read-decoupled network to path for each bitline. The 6T-SRAM and LIU-D9T memory
mitigate the potential for noise. Furthermore, in PLP-9T, we cells are the second and third best SRAM cells for read
opted to use PMOS access transistors in order to minimize the delay. The NLP-9T and PLP-9T designs experience increased
detrimental effects of additional substrate noise. Therefore, the read delay because of the presence of PMOS as read access
suggested designs enhance the ability to retain data without transistors. The WU-Z8T SRAM cell exhibits a higher read
errors as contrast to the current cells. delay due to the presence of additional bitline access paths,
which result in increased bitline capacitance. From Fig. 3(a),
Moreover, the WSNM was measured at 1V VDD with the read delay of 6T-SRAM at 0.6V is increases by 1.5 times
Fig. 3. Read and write delay comparison (a) read delay at VDD variations (b) read delay at various process corners (c) write delay at different VDD (d)
write delay at various process corners

compared to the 0.7 supply voltage. The remaining memory

cells exhibit a linear correlation with the VDD. Furthermore, in
Fig. 2(b), the slow-slow (SS) corner and slow-fast (SF) corner
display reduced and increased read delays, respectively.
We measured all memory cells write delay/access time
(WAT). Out of all the memory cells, the WAT value of CONV-
8T is higher because it has a longer path for discharging to
the logic 0 storage node. Furthermore, the proposed NLP-9T
exhibits the second highest WAT, presence of an additional
discharge path along the bitlines and a voltage drop across
the internal node at the drain of the MN3 transistor. The WU-
Z8T demonstrates superior write speed compared to all current
and proposed memory cells, thanks to its separate write path
and efficient write back schemes. However, implementing an
additional write back scheme necessitates the use of distinct
circuitry, resulting in increased costs in terms of both area
and power consumption. The PLP-9T is suggested as having
the second lowest write delay, primarily because it utilities a
Fig. 4. Leakage power distribution comparison at worst case PVT analysis
PMOS transistor as the write access transistor. In addition, we
conducted verification of WAT under different supply voltage
and process corners variations, as depicted in Fig. 3(c) and 3 times reduced leakage compared to LIU-D9T and CONV-
(d). PLP-9T demonstrates superior write delay performance 8T, WU-Z8T, 6T SRAM cells, respectively. The cause of this
compared to all other existing and proposed NLP-9T cells, issue is the isolation of the bitline and the leakage control
except for WU-Z8T, even under worst case variations. over the inverter. In addition, PLP-9T significantly decreases
leakage power, similar to NLP-9T. However, its average value
C. Leakage Power Dissipation
is greater than NLP-9T because it has a larger number of
The primary measure of concern for low power SRAM ap- PMOS transistors in the circuit and smaller drain-to-source
plications is the dissipation of leakage power, due to advanced voltages across the off transistors.
technology nodes, static power dominates the total power
consumption of the cell [23], [24]. The primary contributors D. Enhanced Robust Trade-Off Metric (ERTM)
to power dissipation due to leakage in a memory cell are the Through our analysis of the literature, we consistently
sub-threshold, gate, and bitline leakages of the cross-coupled noticed there is always a compromising between the area and
inverters. To ensure accuracy, we conducted Monte-Carlo performance of a cell. Furthermore, the fluctuations in the
simulations with 20,000 steps to verify the leakage power of process, voltage, and temperature will also affect the durability
all specified memory cells. This analysis was performed under of a memory cell. So, we measured the ERTM parameter at all
worst-case conditions, including a VDD of 0.6V, FF corner, worst case values. Figure 5 displays the relative ERTM of the
and a temperature of 1200 C. The worst case PVT analysis, PLP-9T cell in relation to the ERTM of the compared memory
Fig. 4 shows, the CONV-8T, WU-Z8T, and 6T SRAM cells cell. All parameters in the ERTM were exclusively evaluated
have a higher leakage power per bit cell of over 60nW. based on the most unfavorable PVT fluctuation readings. The
However, the LIU-D9T demonstrates 1.5 times lower leakage proposed PLP-9T memory cell demonstrates a greater ERTM
power per bit cell as a result of reduced inverter leakage. In compared to both existing and NLP-9T memory cells. This is
addition, the suggested NLP-9T demonstrates 1.4 times and primarily due to its significantly reduced leakage power and
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