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CMEN501 Practice Second Part

The document contains a series of sample questions related to complementary CMOS logic, focusing on various aspects such as transistor behavior, logic implementation, propagation delay, and power dissipation. It covers topics like NMOS and PMOS functionality, logic gate design, and considerations for dynamic circuits. The questions aim to assess understanding of key concepts in digital integrated circuit design.

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14 views2 pages

CMEN501 Practice Second Part

The document contains a series of sample questions related to complementary CMOS logic, focusing on various aspects such as transistor behavior, logic implementation, propagation delay, and power dissipation. It covers topics like NMOS and PMOS functionality, logic gate design, and considerations for dynamic circuits. The questions aim to assess understanding of key concepts in digital integrated circuit design.

Uploaded by

Muhammad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CMEN501 SAMPLE QUESTIONS FOR LECTURES 5 AND 6

Q81. what the advantages of complentary Q82. What are the roles of PUN and PDN in
CMOS logic that made it most used? complementary CMOS logic?
Ans: Ans:

Q83. When is NMOS and PMOS transistors Q84. when NMOS are connected in series and
respectively ON in complementary CMOS? parallel, when kind of logic is implemented
Ans: respectively?

Q85. when PMOS are connected in series and Q86. Why is the number of transistors required
parallel, when kind of logic is implemented to implement an N-input logic gate is 2N in
respectively? complementary CMOS logic?
Ans: Ans:

Q87. Transistor is modeled as a resistor in Q88. List the four techniques for reducing
series with an ideal switch, give the parameters propagation delay in complementary CMOS
on which the resistance depends. logic.
Ans: Ans:

Q89. Write the formula of propagation delay in Q90. Give the parameters that affect power
combinational logic networks. dissipation in CMOS Logic Gates.
Ans: Ans:

Q91. The dynamic power of gate is reduced by Q92. The physical capacitance can be
minimizing which parameters: minimized in a number of ways, list them:
Ans:

Q93. Switching activity can be minimized at all Q94. Time-multiplexing a logic unit over number
levels of design abstraction. Give the main functions has effects, list them.
methods used. Ans:
Ans: a.

Q95. Ratioed logic reduces number of Q96. Draw the generic and a typical logic
transistors to implement a logic function, but diagrams of ratioed logic gate
what the two major disadvantages of this?
Ans:

Q97. What parameters is sizing of load device Q98. Give the reason for which ratioed gate is
relative to pull-down devices is used to trade- so named.
off with? Ans:
Ans:

Q99. Draw the generic logic diagram of dynamic Q100. What is the Boolean function being
logic gate of n-type implemented by the logic diagram below?
Ans:
Ans:
Q101. What is the major cause of clock Q102. What do you understand by the term
misalignment in cascaded dynamic logic ‘set-up time’ of concurrent logic system?
system? Ans:
Ans:

Q103. Give the mathematical expressions of Q104. Why is it necessary for the timing to be
the minimum clock period T, required for accurate in concurrent logic system?
proper operation of the sequential circuit and Ans:
hold time.
Ans:
Q105. Give two causes of vvariations to exist in Q106. Clock-overlap can cause two types of
the ideal clock failures, list them:
Ans:

Q107. Give the four important considerations Q108. The two components of coupling
for dynamic circuits to function properly. capacitance are:

Q109. State the factors of consideration when Q110. How do the presence of pre-charge and
selecting logic type to be used for design of evaluation transistors in dynamic logic system
digital integrated circuits. prevent the consumption of static power?
Ans: Ans:

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