School of Computer Engineering
Kalinga Institute of Industrial Technology (KIIT)
Deemed to be University
Bhubaneswar-751024
LESSON – PLAN
School : School of Computer Engineering
Program : B. Tech. CSE
Academic Session : Autumn Semester 2023 (July. - November)
Subject : High Performance Computing (HPC) (CS 3010)
Course Cridit : 4 (L-T-P) (3-1-0) (Weekly 4 Hours)
Semester : 5th Semester(2021 admitted batch)
Instructor Name : Dr. Subhasis Dash (sdasfcs@kiit.ac.in)
Time Table:-
CSE - 19 Class Timing CSE – 36 Class Timing
Tuesday 10-11 AM Monday 3 – 4 PM
Wednesday 10-11 AM Tuesday 8 – 9 AM
Thursday 3 – 4 PM Thursday 9 – 10 AM
Friday 8 – 9 AM Friday 10-11 AM
Introduction to the course:-
This is a core course, open to 3rd year B.Tech.(CSE) students.
High-Performance Computing refers to the practice of aggregating computing
power to deliver much higher performance for solving large problems in science,
engineering, or business.
This course provides a deeper insight into the design of high-end modern
computers concerning their performance which will support real-time applications.
Application of the Course:-
Modern CPU designing with higher Performance
Handling the challenges imposed by applications with cost-effective architectural
enhancements
Course Outcomes/Learning Objectives:
1. Analyze different quantitative techniques used to measure the performance of the
system with various criteria like CPI, CPU time, speed up, throughput, efficiency,
etc.
2. Apply the concept of different types of hazards along with their structural
implementation and applications.
3. Identify different functional criteria to enhance the performance of pipelined
processors.
4. Analyze memory hierarchy and various Cache optimization techniques.
5. Design different ILP techniques to exploit ILP in scalar, superscalar, super
pipelined processors, and the VLIW processor.
6. Classify various parallel architectures like centralized and distributed memory
architecture
Prerequisite: Computer Architecture (CS-2006)
Lecture-wise plan
Module No. & No. of
name / Section Topics/ Coverage Class
no. Name
1. Overview of 1. Introduction To HPCA
Computer I. Moore’s Law
Architecture II. Classes of Computers
III. Computer Architecture Overview
2. Performance Measurement
I. Performance Measurement concerning execution 8
time, CPU time
II.
Performance Measurement concerning the basic
performance equation
III. Amdahl’s law (Exercises Based on Amdahl’s Law)
3. Introduction to the instruction set architecture (ISA)
4. CISC & RISC processor
ACTIVITY-1 (ASSIGNMENT 1) - (5 Marks)
2. Pipelining 1. Introduction to parallel processing & pipelining Concept.
2. Introduction to MIPS Architecture with its data path
3. A brief introduction to Hazard and its possible effects on
performance due to pipeline stalls
4. Types of Hazards and Pipeline Stall Cycles
I. Structural Hazard
12
II. Data Hazard
III. Control Hazard
5. A technique for overcoming or reducing the effects of
Various hazards (Solutions to different Hazards)
I. Operand forwarding and Instruction Scheduling
II. Flush pipeline, Branch Prediction, Delay Slot
Tutorial Doubt Clearance 2
ACTIVITY-2 (ASSIGNMENT 2) - (5 Marks) 1
3. Instruction 1. Concepts of instruction-level parallelism (ILP)
Level 2. Techniques for increasing ILP
Parallelism I. Dynamic branch prediction
(ILP) II. Loop unrolling
III. Static scheduling
10
Scoreboard approach (With Numerical)
IV. Dynamic scheduling
Tomasulo’s approach (With Numerical)
3. Superscalar & Super pipelined
4. VLIW processor architecture
Tutorial Doubt Clearance 2
ACTIVITY- 3 ( Quiz 1) - (5 Marks) 1
Mid-Semester Examination
4. Hierarchical 1. Memory hierarchy
Memory 2. Cache memory organization
Technology I. Block Placement
II. Block Identification
III. Block Replacement
IV. Write Strategy
V. Numerical examples of cache Memory
performance
3. Cache Memory Performance Evaluation
4. Cache Memory Optimization Techniques 8
I. Reduce miss rate.
Larger block size
Larger cache size
Higher associativity
II. Reduce miss penalty.
Multilevel caches
Priority to Read Misses over Writes
III. Reduce hit time.
Avoiding address translation
Tutorial Doubt Clearance 2
ACTIVITY- 4 (ASSIGNMENT 3) - (5 Marks)
ACTIVITY- 5 (Quiz 2) - (5 Marks)
5. Multiprocessor 1. Taxonomy of Parallel Architecture 6
Architecture 2. Types of Interconnection Networks
I. Time shared common Bus, multiport, Crossbar
II. Multistage switch network, and Hypercube System
3. Multiprocessor Systems
I. Centralized Shared-memory architecture (Tightly
coupled multiprocessor like UMA)
II. Distributed Shared memory architecture (Loosely
coupled multiprocessor like NUMA)
4. Cache coherence protocol
I. Snooping protocol
II. Directory-based protocol
ACTIVITY- 6 (QUIZ 3) - (5 Marks)
Tutorial Doubt Clearance 2
End-Semester Examination
Text Book :
1. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative
Approach, Morgan Kaufmann.
References Books :
1. John Paul Shen and Mikko H. Lipasti, Modern Processor Design: Fundamentals
of Superscalar Processors, Tata McGraw-Hill.
2. M. J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design,
Narosa Publishing House.
3. Kai Hwang, Advanced Computer Architecture: Parallelism, Scalability,
Programmability, McGraw- Hill.
Pedagogy: Lecture, Assignments, Quiz.
Grading Policy:- (Total 100 Marks)
Assignments/quizzes/activities: 30% (Inside-class 20%)
Activity Calendar:-
Type of Activity Schedule Type of Activity Schedule
Assignment 1 31st July 23 Assignment 3 30th Sept. 23
Assignment 2 15th Aug. 23 Quiz 2 18th Oct. 23
Quiz 1 4th Sept. 23 Quiz 3 10th Nov. 23
Dates may change (information will be given to students in class) depending
on course coverage.
Activity (Quiz) will be taken using KIIT Moodle.
Mid-semester Exam: 20% (syllabus upto Instruction Level Parallelism (ILP) i.e. Loop
Unrolling)
End-semester Exam: 50%.
All examinations will be closed notes and closed books. There will be no make-up
exams for quizzes. Any form of cheating will not be tolerated during the tests.
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