Họ và tên : Phạm Thị Mỹ Duyên
MSSV: QE180145 CEA201: 18C02
Part 1: Knowledge Base (4 points)
1. List and briefly define the main structural components of a computer.
The main structural components of a computer are:
- CPU (Central Processing Unit): This is the brain of the computer that controls the
operation of the computer and performs its data processing functions. It consists of
three subcomponents: the control unit, the arithmetic and logic unit (ALU), and the
registers
- Main memory: This is the storage device that stores data and instructions that are
currently being used by the CPU. It is also known as RAM (Random Access Memory)
because it can be accessed randomly by the CPU
- I/O (Input/Output): These are the devices that allow the computer to communicate
with its external environment, such as users, networks, or other computers. Some
common input devices are keyboard, mouse, scanner, etc. Some common output
devices are monitor, printer, speaker, etc
- System interconnection: This is the mechanism that provides for communication
among the CPU, main memory, and I/O devices. It consists of three types of buses: the
address bus, the data bus, and the control bus
2. What are the differences among sequential access, direct access, and random
access?
- Sequential access is a method of accessing data in a specific linear sequence, such as
tapes or magnetic disks. To access a particular record, the device has to read or skip over
all the preceding records. Sequential access is suitable for scenarios that involve
processing data sequentially, such as backup or logging.
- Direct access is a method of accessing data based on a physical location or a unique
identifier. The device can directly access any record without the need to traverse
through the entire file. Direct access is suitable for scenarios that involve frequent direct
access or modification of specific records, such as databases or file systems.
- Random access is a method of accessing data in any order based on their position or
key. The device can randomly access any record without the need to traverse through
the entire file. Random access is suitable for scenarios that involve searching, updating,
and retrieving specific records, such as memory or cache.
3. What is the distinction between spatial locality and temporal locality.
- Spatial locality refers to the tendency of execution to involve a number of memory
locations that are clustered or close in storage locations.
- Temporal locality refers to the tendency of execution to involve memory locations that
have been used recently or will be used soon.
4. What is a parity bit?
A parity bit is a check bit that is added to a string of binary code for error detection
purposes. It is set to either 0 or 1 to make the total number of 1-bits in the string either
even (even parity) or odd (odd parity). The parity bit ensures that the total number of 1-
bits in the string is consistent with the agreed parity, and any change in the parity bit
indicates an error in transmission or storage.
Part 2: Multiple Choice (6 points)
1. During the _________ the opcode of the next instruction is loaded into the
IR and the address portion is loaded into the MAR.
a. execute cycle
b. fetch cycle
c. instruction cycle
d. clock cycle
2. The use of multiple processors on the same chip is referred to as
__________ and provides the potential to increase performance without
increasing the clock rate.
a. multicore
b. GPU
c. data channels
d. MPC
3. The __________ measures the ability of a computer to complete a single
task.
a. clock speed
b. speed metric
c. execute cycle
d. cycle time
4. Virtually all contemporary computer designs are based on concepts
developed by __________ at the Institute for Advanced Studies, Princeton.
a. John Maulchy
b. John von Neumann
c. Herman Hollerith
d. John Eckert
5. A sequence of codes or instructions is called __________.
a. software
b. memory
c. an interconnect
d. a register
6. The processing required for a single instruction is called a(n) __________
cycle.
a. execute
b. fetch
c. instruction
d. packet
7. A(n) _________ is generated by a failure such as power failure or memory
parity error.
a. I/O interrupt
b. hardware failure interrupt
c. timer interrupt
d. program interrupt
8. A(n) _________ is generated by some condition that occurs as a result of an
instruction execution.
a. timer interrupt
b. I/O interrupt
c. program interrupt
d. hardware failure interrupt
9. A bus that connects major computer components (processor, memory, I/O) is
called a __________.
a. system bus
b. address bus
c. data bus
d. control bus
10. The __________ are used to designate the source or destination of the data
on the data bus.
a. system lines
b. data lines
c. control lines
d. address lines
11. Each data path consists of a pair of wires (referred to as a __________) that
transmits data one bit at a time.
a. lane
b. path
c. line
d. bus
12. The PCIe Transaction Layer supports which of the following address
spaces?
a. memory
b. I/O
c. message
d. all of the above
13. The QPI _________ layer is used to determine the course that a packet will
traverse across the available system interconnects.
a. link
b. protocol
c. routing
d. physical
14. __________ refers to whether memory is internal or external to the
computer.
a. Location
b. Access
c. Hierarchy
d. Tag
15. Internal memory capacity is typically expressed in terms of _________.
a. Hertz
b. Nanos
c. Bytes
d. LOR
16. For internal memory, the __________ is equal to the number of electrical
lines into and out of the memory module.
a. Access time
b. Unit of transfer
c. Capacity
d. Memory ratio
17. Individual blocks or records have a unique address based on physical
location with __________.
a. Associative
b. Physical access
c. Direct access
d. Sequential access
18. For random-access memory, __________ is the time from the instant that an
address is presented to the memory to the instant that data have been stored
or made available for use.
a. Memory cycle time
b. Direct access
c. Transfer rate
d. Access time
19. The ________ consists of the access time plus any additional time required
before a second access can commence.
a. Latency
b. Memory cycle time
c. Direct access
d. Transfer rate
20. A portion of main memory used as a buffer to hold data temporarily that is
to be read out to disk is referred to as a _________.
a. Disk cache
b. Latency
c. Virtual address
d. Miss
21. One distinguishing characteristic of memory that is designated as
_________ is that it is possible to both to read data from the memory and to
write new data into the memory easily and rapidly.
a. RAM
b. ROM
c. EPROM
d. EEPROM
22. Which of the following memory types are nonvolatile?
a. erasable PROM
b. programmable ROM
c. flash memory
d. all of the above
23. In a _________, binary values are stored using traditional flip-flop logic-
gate configurations.
a. ROM
b. SRAM
c. DRAM
d. RAM
24. A __________ contains a permanent pattern of data that cannot be changed,
is nonvolatile, and cannot have new data written into it.
a. RAM
b. SRAM
c. ROM
d. flash memory
25. With _________ the microchip is organized so that a section of memory
cells are erased in a single action.
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
