EC308 Embedded Systems (mod I &II)

1. Introduction to Embedded Systems

Embedded System Definitions:

1. “It is any device that includes a programmable computer but is not itself intended to be a general
purpose computer.” – Wayne Wolf

2. “An embedded system is a system that has software embedded into computer-hardware, which
makes a system dedicated for an application (s) or specific part of an application or product or part of a
larger system.”

3. “Embedded Systems are the electronic systems that contain a microprocessor or a microcontroller,
but we do not think of them as computers – the computer is hidden or embedded in the system.” –
Todd D. Morton

4. ……..

Three main embedded components

1. Embeds hardware to give computer like functionalities

2. Embeds main application software generally into flash or ROM and the application software performs
concurrently the number of tasks.

3. Embeds a real time operating system ( RTOS), which supervises the application software tasks running
on the hardware and organizes the accesses to system resources according to priorities and timing
constraints of tasks in the system

Sophisticated Embedded System Characteristics

(1) Dedicated functions

(2) Dedicated complex algorithms

(3) Dedicated (GUIs) and other user interfaces for the application

(4) Real time operations— Defines the ways in which the system works, reacts to the events and
interrupts, schedules the system functioning in real time and executes by following a plan to control the
latencies and to meet the deadlines. [Latency — Waiting interval between the instance at which a need
to run the codes arises for task (or interrupt service routine) following an event and instance of start
executing the codes]

(5) Multi-rate operations — Different operations may take place at distinct rates. For example, the
audio, video, network data or stream and events have the different rates and time constraints to finish
associated processes.
Constraints of an Embedded System Design

1. Available system-memory
2. Available processor speed
3. Limited power dissipation when running the system continuously in cycles of the system start,
wait for event, wake-up and run, sleep and stop
System design constraints

Performance, power, size, non-recurring design cost, and manufacturing costs.

2. Components of embedded system hardware

1. Processor
Program Flow and data path Control Unit (CU) —includes a fetch unit for fetching instructions from the
memory

Execution Unit (EU) —includes circuits for arithmetic and logical unit (ALU), and for instructions for a
program control task, say, data transfer instructions, halt, interrupt, or jump to another set of
instructions or call to another routine or sleep or reset

System designer considerations: Clock frequency in MHz and processing speed , Processor Instructions
in the Instruction set , Processor ability to solve the complex algorithms used in meeting the deadlines
for their processing, Maximum bits in operand (8 or 16 or 32) in a single arithmetic or logical operation,
Internal and External bus-widths in the data-path

Processors can be A) General purpose microprocessor like Intel 80x86, Sparc etc

B) Application Specific Instruction Set Processor (ASIP like a)Microcontroller — Intel, Motorola, Hitachi,
TI, Philips and ARM etc. b) DSP or (c) Media processor or (d) IO processor or (e) Network processor

Single purpose processor Application Specific Instruction processor

• Floating point Coprocessor • CCD Pixel coprocessor and image codec in digital camera • Graphic
processor

2. Power Source
1. System own supply with separate supply rails for IOs, clock, basic processor and memory and
analog units, or 2. Supply from a system to which the embedded system interfaces, for example
in a network card, or Charge pump concept used in a system of little power needs, for examples,
in the mouse or contact-less smart card.
2. Clock Oscillator Circuit and Clocking Units
1. Appropriate clock oscillator circuit 2. Real Time Clock *( System Clock) and Timers driving
hardware and software
3. Reset Circuit
1. Reset on Power-up 2. External and Internal Reset circuit 3. Reset on Timeout of Watchdog timer
4. Memory

a)Functions Assigned to the ROM or EPROM or Flash

1. Storing 'Application' program from where the processor fetches the instruction codes 2. Storing
codes for system booting, initializing, Initial input data and Strings. 3. Storing Codes for RTOS. 4. Storing
Pointers (addresses) of various service routines.

b)Functions Assigned to the Internal, External and Buffer RAM

1. Storing the variables during program run, 2. Storing the stacks, 3. Storing input or output buffers for
example, for speech or image

c. Functions Assigned to the EEPROM or Flash

Storing non-volatile results of processing

d. Functions Assigned to the Caches

1. Storing copies of the instructions, data and branch-transfer instructions in advance from external
memories and 2. Storing temporarily the results in write back caches during fast processing

5. Interrupts Handler
Interrupt Handling element for the external port interrupts, IO interrupts, timer and RTC interrupts,
software interrupts and exceptions

6. Linking and interfacing circuit for the Buses by using the appropriate multiplexers, and decoders,
demultiplexers Interface the various system units

7. IO communication elements: buses (serial and parallel), interfaces for network interface, ADC, DAC,
pulse dialer, modem, Bluetooth, 802.11, … as per the application

Software embedded into the system

1. ROM Image
Final stage software also called ROM image (Just as an image is a unique sequence and
arrangement of pixels, embedded software is also a unique placement and arrangement at
each ROM address of bytes for instructions and data. )
Final machine software

Bytes at each address defined for creating the ROM image. By changing this image, the same hardware
platform work differently and can be used for entirely different applications or for new upgrades of the
same system.

Hardware elements between the distinct systems can be identical but it is the software that makes a
system unique and distinct from the other.
 1. Machine Language Coding
Programmer defines the addresses and the corresponding bytes or bits at each address.

Used in configuring some specific physical device or subsystem like transceiver, the machine code-
based

coding is used

2. Assembly Language Coding

Needed for Invoking Processor Specific Instructions. Requires understanding of the processor and
instruction set. A program or a small specific part coded in the assembly language using an Assembler

Three steps when using assembly language

'Assembler','Linker' and 'Locator' before finally burned at the ROM

Compiler Generates an object file. Using linker and locator, the file for ROM image is created for the
targeted hardware. C++ and Java are other languages used for software coding.
Devices

In an embedded system, there are number of physical devices.Physical devices – keypad, LCD

display or touch screen, memory stick (flash memory), wireless networking

device, parallel port and network card.

In an embedded system, there are number of virtual devices.

Virtual devices – pipe, file, RAM disk, socket, …

A device driver is software for controlling (configuring), receiving and sending a byte or a stream of
bytes from or to a device.

Device Management software (usually a part of the OS) provide codes for detecting the presence of
devices, for initializing (configuring) these and for testing the devices that are present.

RTOS is needed when the tasks for the system have real time constraints and deadlines for finishing
the tasks

Challenges in Embedded System Design: Optimizing the Design Metrics and Formalism of System
Amount and type of hardware needed

Optimizing the microprocessors, ASIPs and single purpose processors in the system

Optimizing according to the performance, power dissipation, cost and other design

metrics the system

Optimizing hardware (memory RAM, ROM or internal and external flash or secondary

memory in the system, peripherals and devices internal and external to the system,

ports and buses in the system and power source or battery in the system).

Taking into account the design metrics

Design metrics examples –power dissipation, physical size, number of gates and engineering, prototype

development and manufacturing costs.

Optimizing the Power Dissipation

1.Clock Rate Reduction

2. Operating Voltage Reduction

3. Wait, Stop and Cache Disable Instructions –

Clever real- time programming. It is by using of 'Wait' and 'Stop' instructions and

disabling or controlling certain units when not needed is one method of saving power

during program execution

Disable use of certain structural units of the processor to reduce power dissipation

Caches—when not necessary and Keep in disconnected state those structure units that are not needed
during a particular software-portion execution, for example,display screen, timers or IO units Control of
power requirement, for example, by screen auto-brightness control

Meeting the deadline of all processes in the system while keeping the memory, power dissipation,
processor clock rate and cost at minimum is a challenge

Flexibility and Upgradeability

Ability to offer the different versionsnof a product for marketing and offering the product in advanced
versions later on.

Reliability

Designing reliable product by appropriate design and thorough testing, verification and validation is a
challenge.

Testing, Verification and Validation

Testing – to find errors and to validate that the implemented software is as per the specifications and
requirements to get reliable product.

Verification – refers to an activity to ensure that specific functions are correctly implemented.

Validation – refers to an activity to ensure that the system that has been created is as per requirements
agreed upon at the analysis phase, and to ensure its quality

Modules

Be clearly understood and maintain continuity. Appropriate protection strategies are necessary for each
module. A module is not permitted to change or modify another module functionality. For example,
protection from a device driver modifying the configuration of another device

ARM architecture
• 32-bit RISC-processor core (32-bit instructions)

• 37 pieces of 32-bit integer registers (16 available)

• Pipelined (ARM9: 5 stages)

• Cached (depending on the implementation)

• Harvard (ARM9)

• 8 / 16 / 32 -bit data types • 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)

• Simple structure -> reasonably good speed / power consumption ratio

Architecture variants

T: 16-bit Thumb instruction D: On-chip Debug support M: Hardware long Multiplier I: Embedded
ICEE:
DSP extensionS: Synthesizable coreJ: Jazelle Java accelerator

General-purpose registers (GPR)

Visible registers:31 general-purpose registers, 6 program status registers. At any time, 16 general-
purpose registers and one or two status registers are visible according to processor mode.General-
purpose registers (GPR)Unbanked registers, R0-R7, R15 The same physical registers in all
processor modes. Banked registers, R8-R14The physical register referred to by each of them
depends on the current processor mode.Special function of R13-15 :Stack pointer (R13),Link
register (R14): save the return address.Program counter (R15): point to address of instruction to be
fetched

AMBA: Advanced Microcontroller Bus Architecture – It is a specification for an on-chip bus, to

enable macrocells (such as a CPU, DSP, Peripherals, and memory controllers) to be connected
together to form a microcontroller or complex peripheral chip. – It defines • A high-speed, high-
bandwidth bus, the Advanced High Performance Bus (AHB). • A simple, low-power peripheral bus,
the Advanced Peripheral Bus (APB). • Access for an external tester to permit modular testing and
fast test of cache RAM • Essential house keeping operations (reset/power-up, …)

Module II

UART

A basic UART system provides robust, moderate-speed, full-duplex

communication with only three signals: Tx (transmitted serial data), Rx
(received serial data), and ground. In contrast to other protocols, no clock
signal is required because the user gives the UART hardware the necessary
timing information.

ART characteristics:

● Start bit: The first bit of a one-byte UART transmission. It indicates

that the data line is leaving its idle state. The idle state is typically
logic high, so the start bit is logic low.
○ The start bit is an overhead bit; this means that it facilitates
communication between receiver and transmitter but does not
transfer meaningful data.
DATA BITS - 5-8 bits

P BIT - Programmable/parity bit - optional

● Stop bit: The last bit of a one-byte UART transmission. Its logic level is
the same as the signal’s idle state, i.e., logic high. This is another
overhead bit.

● Baud rate: The approximate rate (in bits per second, or bps) at which
data can be transferred. A more precise definition is the frequency (in
bps) corresponding to the time (in seconds) required to transmit one
bit of digital data. For example, with a 9600-baud system, one bit
requires 1/(9600 bps) ≈ 104.2 µs. The system cannot actually transfer
9600 bits of meaningful data per second because additional time is
needed for the overhead bits and perhaps for delays between one-byte
transmissions.
 ● Parity bit: An error-detection bit added to the end of the byte. There
are two types—“odd parity” means that the parity bit will be logic high
if the data byte contains an even number of logic-high bits, and “even
parity” means that the parity bit will be logic high if the data byte
contains an odd number of logic-high bits. This may seem
counterintuitive, but the idea is that the parity bit ensures that the
number of logic-high bits is always even (for even parity) or odd (for
odd parity). So if you’re using even parity and the byte has three logic-
high bits, the parity bit will be logic high, so that the total number of
logic-high bits in the transmitted data (i.e., the byte itself plus the
parity bit) is even.

HDLC

HDLC is a bit-oriented protocol. It was developed by the International Organization for Standardization
(ISO). It falls under the ISO standards ISO 3309 and ISO 4335. It specifies a packetization standard for
serial links. It has found itself being used throughout the world. It has been so widely implemented
because it supports both half-duplex and full-duplex communication lines, point-to-point (peer to peer)
and multi-point network.

HDLC Stations and Configurations

HDLC specifies the following three types of stations for data link control:

• Primary Station
It has the responsibility of controlling all other stations on the link (usually secondary stations). A
primary issues commands and secondary issues responses.

• Secondary Station

The secondary station is under the control of the primary station. It has no ability, or direct
responsibility for controlling the link. It is only activated when requested by the primary station. It only
responds to the primary station. The secondary station's frames are called responses. It can only send
response frames when requested by the primary station. A primary station maintains a separate logical
link with each secondary station.

• Combined Station

A combined station is a combination of a primary and secondary station. On the link, all combined
stations are able to send and receive commands and responses without any permission from any other
stations on the link. Each combined station is in full control of itself, and does not rely on any other
stations on the link. No other stations can control any combined station. May issue both commands and
responses

The three configurations defined by HDLC:

• Unbalanced Configuration: The unbalanced configuration in an HDLC link consists of a primary station
and one or more secondary stations. The unbalanced occurs because one stations controls the other
stations

• Balanced Configuration: The balanced configuration in an HDLC link consists of two or more combined
stations. Each of the stations has equal and complimentary responsibility compared to each other.

• Symmetrical Configuration: It consists of two independent point to point, unbalanced station

configurations. In this configuration, each station has a primary and secondary status. Each station is
logically considered as two stations.

These three modes of operations of HDLC are:

• Normal Response Mode (NRM): The primary station initiates transfers to the secondary station. The
secondary station can only transmit a response when, and only when, it is instructed to do so by the
primary station

• Asynchronous Response Mode (ARM): The primary station doesn't initiate transfers to the secondary
station. In fact, the secondary station does not have to wait to receive explicit permission from the
primary station to transfer any frames. The frames may be more than just acknowledgment frames.

• Asynchronous Balanced Mode (ABM): This mode uses combined stations. There is no need for
permission on the part of any station in this mode. This is because combined stations do not require any
sort of instructions to perform any task on the link.
HDLC Frame Structure

There are three different types of frames as shown in Fig. and the size of different fields are shown Tab.
I-Frame

S-Frame

U-Frame

Figure Different types of frames used in HDLC

Size of different fields

Field Name Size(in bits)

Flag Field( F ) 8 bits

Address Field( A ) 8 bits

Control Field( C ) 8 or 16 bits

Information Field( I ) OR Data Variable; Not used in some frames

Frame Check Sequence( FCS ) 16 or 32 bits

Closing Flag Field( F ) 8 bits

The Flag field

Every frame on the link must begin and end with a flag sequence field (F). Stations attached to the data
link must continually listen for a flag sequence. The flag sequence is an octet looking like 01111110.
Flags are continuously transmitted on the link between frames to keep the link active. Two other bit
sequences are used in HDLC as signals for the stations on the link. These two bit sequences are: • Seven
1's, but less than 15 signal an abort signal. The stations on the link know there is a problem on the link. •
15 or more 1's indicate that the channel is in an idle state.

The time between the transmissions of actual frames is called the interframe time fill. The interframe
time fill is accomplished by transmitting continuous flags between frames. The flags may be in 8 bit
multiples. HDLC is a code-transparent protocol. It does not rely on a specific code for interpretation of
line control. This means that if a bit at position N in an octet has a specific meaning, regardless of the
other bits in the same octet. If an octet has a bit sequence of 01111110, but is not a flag field, HLDC uses
a technique called bit-stuffing to differentiate this bit sequence from a flag field At the receiving end, the
receiving station inspects the incoming frame. If it detects 5 consecutive 1's it looks at the next bit. If it is
a 0, it pulls it out. If it is a 1, it looks at the 8th bit. If the 8th bit is a 0, it knows an abort or idle signal has
been sent. It then proceeds to inspect the following bits to determine appropriate action. This is the
manner in which HDLC achieves code-transparency. HDLC is not concerned with any specific bit code
inside the data stream. It is only concerned with keeping flags unique.

The Address field

The address field (A) identifies the primary or secondary stations involvement in the frame transmission
or reception. Each station on the link has a unique address. In an unbalanced configuration, the A field in
both commands and responses refer to the secondary station. In a balanced configuration, the
command frame contains the destination station address and the response frame has the sending
station's address.

The Control field

HDLC uses the control field (C) to determine how to control the communications process. This field
contains the commands, responses and sequences numbers used to maintain the data flow
accountability of the link, defines the functions of the frame and initiates the logic to control the
movement of traffic between sending and receiving stations. There three control field formats:

• Information Transfer Format: The frame is used to transmit end-user data between two devices.

First bit 0, next 3-bits N(S), next bit $P/F and last 3-bits N(R) in standard format

• Supervisory Format: The control field performs control functions such as acknowledgment of frames,
requests for re-transmission, and requests for temporary suspension of frames being transmitted. Its
use depends on the operational mode being used.

First two bits (10), next 2- bits # RR or RNR or REJ or SREJ, next bit P/F and last 3-bits N(R) in standard
format.

• Unnumbered Format: This control field format is also used for control purposes. It is used to perform
link initialization, link disconnection and other link control functions.
First two bits (11), next 2-bits ^M, next bit P/F and last 3-bit remaining bits for M

(N(R) sequence number of frame received earlier from a device to which this HDLC frame is being sent
N(S) sequence number of frame sending now to that device

RR- A message in control bits in case 2, which conveys ‘Receiver Ready’ RNR - ‘Receiver Not Ready

REJ – Reject (Sent when a message rejects). SREJ – ‘Selectively Reject’ Frame received out-of-sequence,
repeat suggested.)

The Poll/Final Bit (P/F) The 5th bit position in the control field is called the poll/final bit, or P/F bit. It can
only be recognized when it is set to 1. If it is set to 0, it is ignored. The poll/final bit is used to provide
dialogue between the primary station and secondary station. The primary station uses P=1 to acquire a
status response from the secondary station. The P bit signifies a poll. The secondary station responds to
the P bit by transmitting a data or status frame to the primary station with the P/F bit set to F=1. The F
bit can also be used to signal the end of a transmission from the secondary station under Normal
Response Mode.

The Information field or Data field

This field is not always present in a HDLC frame. It is only present when the Information Transfer
Format is being used in the control field. The information field contains the actually data the sender is
transmitting to the receiver in an I-Frame and network management information in U-Frame.

The Frame check Sequence field

This field contains a 16-bit, or 32-bit cyclic redundancy check bits. It is used for error detection

SPI

Serial Peripheral Interface or SPI is a synchronous serial communication protocol that

provides full – duplex communication at very high speeds. Serial Peripheral Interface
(SPI) is a master – slave type protocol that provides a simple and low cost interface
between a microcontroller and its peripherals.SPI is a Synchronous type serial
communication i.e. it uses a dedicated clock signal to synchronise the transmitter and
receiver or Master and Slave.

In SPI protocol, the devices are connected in a Master – Slave relationship in a multi –
point interface. In this type of interface, one device is considered the Master of the bus
(usually a Microcontroller) and all the other devices (peripheral ICs or even other
Microcontrollers) are considered as slaves.

In SPI protocol, there can be only one master but many slave devices.
The SPI bus consists of 4 signals or pins. They are

● Master – Out / Slave – In (MOSI)

● Master – In / Slave – Out (MISO)
● Serial Clock (SCLK) and
● Chip Select (CS) or Slave Select (SS)

Master – Out / Slave – In or MOSI, as the name suggests, is the data generated by the
Master and received by the Slave. Hence, MOSI pins on both the master and slave are
connected together. Master – In / Slave – Out or MISO is the data generated by Slave
and must be transmitted to Master.

MISO pins on both the master and slave are ties together. Even though the Signal in
MISO is produced by the Slave, the line is controlled by the Master. The Master
generates a clock signal at SCLK and is supplied to the clock input of the slave. Chip
Select (CS) or Slave Select (SS) is used to select a particular slave by the master.

Since the clock is generated by the Master, the flow of data is controlled by the master.
For every clock cycle, one bit of data is transmitted from master to slave and one bit of
data is transmitted from slave to master.

This process happen simultaneously and after 8 clock cycles, a byte of data is
transmitted in both directions and hence, SPI is a full – duplex communication.

If more than one slave has to be connected to the master, then the setup will be
something similar to the following image.
SERIAL BUSCOMMUNICATION PROTOCOLS– I2C

Interconnecting number of device circuits, Assume flash memory, touch

screen, ICs for measuring temperatures and ICs for measuring pressures at a
number of processes in a plant.

_ ICs mutually network through a common synchronous serial bus I2C An 'Inter
Integrated Circuit' (I2C) bus,a popular bus for these circuits.

_Synchronous Serial Bus Communication for networking

_ Each specific I/O synchronous serial device may be connected to other using
specific interfaces, for example, with I/O device using I2C controller

_ I2C Bus communication− use of only simplifies the number of connections and
provides a common way (protocol) of connecting different or same type of I/O
devices using synchronous serial communication
IO I2C Bus

_ Any device that is compatible with a I2Cbus can be added to the

system(assuming an appropriate device driver program is available), and a I2C
device can be integrated into any system that uses that I2C bus.

Originally developed at Philips Semiconductors

Synchronous Serial Communication 400kbps up to 2 m and 100 kbps for longer

distances

Three I2C standards

1. Industrial 100 kbps I2C,

 2. 100 kbps SM I2C,

3. 400 kbps I2C

I2C Bus

_ The Bus has two lines that carry its signals— one line is for the clock and
one is for bi-directional data.

_ There is a standard protocol for the I2Cbus.

Device Addresses and Master in the I2C bus

_ Each device has a 7-bit address using which the data transfers take place. _
Master can address 127 other slaves at an instance.

_ Master has at a processing element functioning as bus controller or a

microcontroller with I2C (Inter Integrated Circuit) bus interface circuit.

Slaves and Masters in the I2C bus

_ Each slave can also optionally has I2C (Inter Integrated Circuit) bus controller
and processing element.

_ Number of masters can be connected on the bus.

_ However, at an instance, master is one, which initiates a data transfer on
SDA(serial data) line and which transmits the SCL (serial clock) pulses.
From master, a data frame has fields beginning from start bit

Synchronous Serial Bus Fields and its length

_ First field of 1 bit─ Start bit similar to one in an UART

_ Second field of 7 bits─ address field. It defines the slave address, which is being
sent the data frame (of many bytes) by the master

_ Third field of 1 control bit─ defines whether a read or write cycle is in progress

_ Fourth field of 1 control bit─ defines whether is the present data is an

acknowledgment (from slave)
_ Fifth field of 8 bits─ I2C device data byte

_ Sixth field of 1-bit─ bit NACK (negative acknowledgement) from the receiver. If
active then acknowledgment after a transfer is not needed from the slave, else
acknowledgement is expected from the slave

_ Seventh field of 1 bit ─ stop bit like in an UART

Disadvantage of I2C bus

• Time taken by algorithm in the hardware that analyzes the bits throughI2C in
case the slave hardware does not provide for the hardware that supports it.

• Certain ICs support the protocol and certain do not.

• Open collector drivers at the master need a pull-up resistance of 2.2 K on each
line

SERIAL BUSCOMMUNICATION PROTOCOLS -

CAN

Distributed Control Area Network example - a network of embedded systems in

automobile

_ CAN-bus line usually interconnects to a CAN controller between line and host at
the node. It gives the input and gets output between the physical and data link
layers at the host node.
_ The CAN controller has a BIU (bus interface unit consisting of buffer and
driver), protocol controller, status-cum control registers, receiver-buffer and
message objects. These units connect the host node through the host interface
circuit

Three standards:

1. 33 kbps CAN,

2. 110 kbps Fault Tolerant CAN,

3. 1 Mbps High Speed CAN

CAN protocol
There is a CAN controller between the CAN line and the host node.

_ CAN controller ─BIU (Bus Interface Unit)consisting of a buffer and driver

_ Method for arbitration─ CSMA/AMP(Carrier Sense Multiple Access with

Arbitration on Message Priority basis)

Each Distributed Node Uses:

• Twisted Pair Connection up to 40 m –for bi-directional data

• Line, which pulls to Logic 1 through a resistor between the line and + 4.5V to
+12V.

• Line Idle state Logic 1 (Recessive state)

• Uses a buffer gate between an input p in and the CAN line

• Detects Input Presence at the CAN line pulled down to dominant (active) state
logic 0 (ground ~ 0V) by a sender to the CAN line

• Uses a current driver between the output pin and CAN line and pulls line down to
dominant

(active) state logic 0(ground ~ 0V) when sending to the CAN line Protocol defined
start bit followed by six fields of frame bits Data frame starts after first detecting
that dominant state is not present at the CAN line with logic 1 (R state) to 0 (D
state transition) for one serial bit interval
• After start bit, six fields starting from arbitration field and ends with seven logic0s
end-field

• 3-bit minimum inter frame gap before next start bit (R→ D transition) occurs

Protocol defined First field in frame bits

_ First field of 12 bits ─'arbitration field.
_ 11-bit destination address and RTR bit (Remote Transmission Request)
_ Destination device address specified in an11-bit sub-field and whether the data
byte being sent is a data for the device or a request to the device in 1-bit sub-field.

_ Maximum 211 devices can connect a CAN controller in case of 11-bit address
fieldstandard11-bit address standard CAN
_ Identifies the device to which data is being sent or request is being made.

_ When RTR bit is at '1', it means this packet is for the device at destination
address. If this bit is at '0' (dominant state) it means, this packet is a request for the
data from the device.

Protocol defined frame bits Second field _ Second field of 6 bits─ control field.
The first bit is for the identifier‘ s extension.

_ The second bit is always '1'.

_ The last 4 bits specify code for data Length

_ Third field of 0 to 64 bits─ Its length depends on the data length code in the
control field.

• Fourth field (third if data field has no bit present) of 16 bits─ CRC (Cyclic
Redundancy Check) bits.

• The receiver node uses it to detect the errors, if any, during the transmission

• Fifth field of 2 bits─ First bit 'ACK slot'

• ACK = '1' and receiver sends back '0' in this slot when the receiver detects an
error in the

reception.

• Sender after sensing '0' in the ACK slot, generally retransmits the data frame.
• Second bit 'ACK delimiter' bit. It signals the end of ACK field.

• If the transmitting node does not receive any acknowledgement of data frame
within a

Specified time slot, it should retransmit.

Sixth field of 7-bits ─ end- of- the frame specification and has seven '0's

SERIAL BUSCOMMUNICATION PROTOCOLS– USB

USB Host Applications Connecting

• flash memory cards,

• pen-like memory devices,

• digital camera,

• printer,

• mouse-device,

• Pocket PC,

• video games,
 • Scanner

Universal Serial Bus (USB)

_ Serial transmission and reception between host and serial devices

_ The data transfer is of four types: (a)Controlled data transfer, (b) Bulk data
transfer, (c) Interrupt driven data transfer, (d) Iso-synchronous transfer

_ A bus between the host system and inter connected number of peripheral devices

USB Protocol Features

_ Maximum 127 devices can connect a host.

_ Three standards: USB 1.1 (a low speed1.5 Mbps 3 meter channel along with a
high speed 12 Mbps 25 meter channel),USB 2.0 (high speed 480 Mbps 25meter
channel), and wireless USB(high speed 480 Mbps 3 m)

Host connection to the devices or nodes

_ Using USB port driving software and host controller,

_ Host computer or system has a host controller, which connects to a root hub. _ A
hub is one that connects to other nodes or hubs.
_ A tree- like topology

USB Device features

_ Can be hot plugged (attached), configured and used, reset, reconfigured and used

_ Bandwidth sharing with other devices: Host schedules the sharing of bandwidth
among the attached devices at an instance.

_ Can be detached (while others are in operation) and reattached. _ Attaching and
detaching USB device or host without rebooting
USB device descriptor

_ Has data structure hierarchy as follows:

_ It has device descriptor at the root, which has number of configuration

descriptors, which has number of interface descriptor and which has number of end
point descriptor.

Powering USB device

_ A device can be either bus-powered or self- powered.

_ In addition, there is a power management by software at the host for USB ports

USB protocol

_ USB bus cable has four wires, one for+5V, two for twisted pairs and one for
ground.
_ Termination impedances at each end as per the device-speed.

_ Electromagnetic Interference (EMI)-shielded cable for the 15 Mbps USB

devices.
_ Serial signals NRZI (Non Return to Zero (NRZI)

_ The synchronization clock encoded by inserting synchronous code (SYNC)field

before each USB

packet
_ Receiver synchronizes its bits recovery clock continuously

USB Protocol

• A polled bus

• Host controller regularly polls the presence of a device as scheduled by the

software.

• It sends a token packet.

• The token consists of fields for type, direction, USB device address and device
end-point number.

• The device does the handshaking through a handshake packet, indicating

successful or unsuccessful transmission.

• A CRC field in a data packet permitserror detection

USB supported three types of pipes

1. 'Stream' with no USB- defined protocol. It is used when the connection is

already established and the data flow starts

2. 'Default Control' for providing access.

3. 'Message' for the control functions for of the device.

• Host configures each pipe with the data bandwidth to be used, transfer service
type and buffer

sizes.

PARALLEL BUSDEVICE PROTOCOLS – PCI Bus

_ Parallel bus enables a host computer or system to communicate simultaneously

32-bit or 64-bit with other devices or systems, for example, to a network interface
card (NIC) or graphic card

Computer system PCI

• When the I/O devices in the distributed embedded subsystems are networked all
can communicate through a common parallel bus.

• PCI connects at high speed to other subsystems having a range of I/O devicesat
very short distances (<25 cm) using a parallel bus without having to implement a
specific interface for each I/O device.

PCI bus Applications

Connects

_ display monitor, printer, character devices, network subsystems, video card,

modem card, hard disk controller,

PCI bus connects

_ Card with 16 MB Flash ROM with a router gateway for a LAN and _ Card using
DEC 21040 PCI Ethernet LAN controller.

• When the I/O devices in the distributed embedded subsystems are networked, all
can communicate through a common parallel bus.

• PCI connects at high speed to other subsystems having a range of I/O devicesat
very short distances (<25 cm) using a parallel bus without having to implement a
specific interface for each I/O device.

PCI Bus Feature

_ 32- bit data bus extendible to 64 bits.

_ PCI protocol specifies the ways of interaction between the different components
of a computer.

_ A specification version 2.1─synchronous/asynchronous throughput is up to 132/

528 MB/s [33M × 4/ 66M× 8 Byte/s], operates on 3.3V to 5Vsignals.

_ PCI driver can access the hardware automatically as well as by the programmer
assigned addresses.

_ Automatically detects the interfacing systems and assigns new addresses

_ Thus, simplified addition and deletion(attachment and detachment) of the system

peripherals.

FIFO in PCI device/card

_ Each device may use a FIFO controller with a FIFO buffer for maximum
throughput. Identification Numbers

_ A device identifies its address space by three identification numbers, (i) I/O port
(ii) Memory locations and (iii)Configuration registers of total 256Bwith a four 4-
byte unique ID. Each PCI device has address space allocation of256 bytes to
access it by the host

Computer

PCI device identification

_ A sixteen16-bit register in a PCI device identifies this number to let that device
auto- detect it.

_ Another sixteen16-bit register identifies a device ID number. These two numbers

let allow the device to carry out its auto-detection by its host computer.

Peripheral Component Interconnect (PCI) Bus

_ Independent from the IBM architecture.

_ Number of embedded devices in a computer system use PCI _ Three standards

for the devices interfacing with the PC

_ PCI 32bit/33 MHz, and 64bit/66 MHz

_ PCI Extended (PCI/X) 64 bit/100 MHz ,

_ Compact PCI (cPCI) Bus
Two super speed versions

_ PCI Super V2.3 264/528 MBps 3.3V (on64- bit bus), and 132/264 (on 32-bit
bus)and _ PCI-X Super V1.01a for 800MBps 64- bitbus 3.3Volt.

PCI bridge

_ PCI bus interface switches a processor communication with the memory bus to
PCI bus.
_ In most systems, the processor has a single data bus that connects to a switch
module

_ Some processors integrate the switch module onto the same integrated circuit
asthe processor to reduce the number of chips required to build a system and thus
the system cost.

_ Communicates with the memory through a memory bus (a set of address, control
and data buses), a dedicated set of wires that transfer data between these two
systems.

_ A separate I/O bus connects the PCI switch to the I/O devices.

Advantage of Separate memory and I/O buses

_ I/O system generally designed for maximum flexibility, to allow as many

different I/O devices as possible to interface to the computer

_ Memory bus is designed to provide the maximum-possible bandwidth between

the processor and the memory system.
PCI-X (PCI extended)

• 133 MBps to as much as 1 GBps

• Backward compatible with existing

PCI cards

• Used in high bandwidth devices(Fiber Channel, and processors that are part of a
cluster and Gigabit Ethernet)

• Maximum 264 MBps throughput, uses 8,16, 32, or 64 bit transfers

• 6U cards contain additional pins for user defined I/Os

Live insertion support (Hot-Swap),

• Supports two independent buses on the back plane (on different connectors)

• Supports Ethernet, Infiniband, and StarFabric support (Switched fabric based

systems) Compact

PCI (cPCI)

Each PCI device on Bus

_ Perform a specific function,

_ May contain a processor and software to perform a specific function.

_ Each device has the specific memory address-range, specific interrupt-

vectors(pre-assigned or auto configured) and the device I/O port addresses.

_ A bus of appropriate specifications and protocol interfaces these to the host

computer system or compute

Configuration address space

_ Unique feature of PCI bus unique feature is its configuration address space.

PCI controller Features

• Accesses one device at a time

• All the devices within host device or system can share the I/O port and memory
addresses, but

cannot share the configuration registers

• Device cannot modify other configuration registers but can access other device
resources or share the work or assist the other device

• If there are reasons for doing it so, a PCI driver can change the default bootup
assignments on configuration transactions