MODULE 2

Register transfer logic: inter register transfer – arithmetic, logic

and shift micro-operations. Processor logic design: - processor
organization – Arithmetic logic unit - design of arithmetic circuit
- design of logic circuit - Design of arithmetic logic unit - status
register – design of shifter - processor unit – design of
accumulator.

Register Transfer logic

A digital system is a collection of hardware components that work together
to process data. These systems use flip-flops (to store data) and logic gates
(to perform operations). Since large systems have many possible states,
describing them in detail using a state table can be very complex.
Why Use Register Transfer Logic (RTL)?
Instead of dealing with the entire system at once, we break it into smaller
functional units (modules). Each module performs a specific task, like
storing, counting, or processing data. Examples of such modules include:
 Registers (small storage units)
 Counters (for counting operations)
 Decoders and Multiplexers (for data selection)
 Arithmetic and Logic Units (for mathematical and logical
operations)
 Control Logic (to manage the sequence of operations)
What is Register Transfer Logic (RTL)?
Register Transfer Logic (RTL) is a method used to describe how data moves
between registers and how operations are performed on this data. Instead of
using complex circuit diagrams, RTL uses expressions and statements
(similar to a programming language) to represent these processes.
Main Components of Register Transfer Logic
1. Registers and Their Functions
o Registers are small memory units that temporarily store data.
o They include shift registers, counters, and memory units.
2. Binary Data Stored in Registers
o Registers store information in binary format (0s and 1s).
o The stored data can be:
 Numbers (binary or decimal-coded)
 Text characters (like letters and symbols)
 Control instructions (commands for processing data)
 3. Operations Performed on Data (Micro-Operations)
o Micro-operations are small actions performed on data in
registers.
o Examples include:
 Shift (move data left or right)
 Count (increase or decrease a value)
 Add (perform addition)
 Clear (reset data to zero)
 Load (store new data in a register)
4. Control Functions (Sequence of Operations)
o A digital system follows a step-by-step process.
o Control signals decide when and in what order operations
should happen.
o These signals work with timing signals to ensure each
operation is performed at the right time.
Register transfer language (Computer hardware description language)
Register Transfer Language (RTL) is a way to describe how data moves
between registers and how operations are performed on this data inside a
digital system. It uses a symbolic notation (similar to a programming
language) to specify:
1. Registers involved in the operation.
2. Actions (micro-operations) performed on the register contents.
3. Control functions that determine when and how operations are
executed.
What is a Micro-Operation?
A micro-operation is a small, basic action performed on data stored in
registers.
 It happens in one clock cycle if executed in parallel.
 If executed in a serial system, it may take multiple clock cycles
(depending on word length).
Examples of micro-operations:
 Shift – Move data left or right in a register.
 Count – Increase or decrease a value.
 Clear – Reset the data to zero.
 Add – Perform addition between registers.
 Load – Store new data in a register.
Types of Data Stored in Registers
Micro-operations depend on the type of binary information stored in
registers, which can be:
 1. Numerical Data – Binary numbers or binary-coded decimal (BCD)
numbers.
2. Non-Numerical Data – Letters, symbols, or other binary-coded
characters.
3. Control Information – Instruction codes, addresses, and other control
signals that manage data processing.
Types of Micro-Operations in a Digital System
1. Interregister Transfer Micro-Operations
 Move data from one register to another without changing it.
 Example: R1←R2 (copies data from R2 to R1).
2. Arithmetic Micro-Operations
 Perform mathematical operations like addition, subtraction,
increment, and decrement.
 Example: R1←R1+R2 (adds R1 and R2, stores result in R1).
3. Logic Micro-Operations
 Perform bitwise logical operations (AND, OR, XOR, NOT)
on register contents.
 Example: R1←R1 AND R2 (performs bitwise AND between
R1 and R2).
4. Shift Micro-Operations
 Move data left or right within a register.
 Example: R1←shl(R1) (shifts bits left by one position).

Inter Register Transfer

A register is a small, high-speed storage unit inside the CPU used to hold
temporary data and instructions. Registers are named using capital letters
(sometimes with numbers) to indicate their function.
Examples of Common Registers:
 R1, R2, R3 → General-purpose registers for storing temporary data.
 MAR (Memory Address Register) → Holds a memory address
(location of data in RAM).
 MBR (Memory Buffer Register) → Holds data read from or written
to memory.
 PC (Program Counter) → Keeps track of the next instruction in a
program.
 IR (Instruction Register) → Stores the current instruction being
executed.
 SR (Status Register) → Stores system status flags (e.g., Zero Flag,
each register consists of small storage units called flip-flops (bits).
If a register has n bits, the individual bits are numbered sequentially
from 1 to n (or from 0 to n-1), either from left to right or right to left.
 Four Ways to Represent Registers:
o Simple Representation:
 A rectangular box with the register name inside.
o Bitwise Representation:
  Each bit in the register is given a subscript (e.g., A₁,
A₂, A₃).
o Numbered Bit Representation:
 The bit positions are numbered on top of the box
(e.g., a 12-bit register MBR is labeled from 1 to 12).
o Divided Register Representation:
 A 16-bit register is split into two parts:
 Low part (L) → Bits 1 to 8
 High part (H) → Bits 9 to 16
 Carry Flag).

Registers can be specified in a register transfer language with a declaration

statement. For example: Registers in the above figure can be defined with
declaration statement such as
DECLARE REGISTER A(8), MBR(12), PC(16)
DECLARE SUBREGISTER PC(L) = PC(1-8), PC(H) = PC(9-16).
This means:
 Register A has 8 bits.
 Register MBR has 12 bits.
 Register PC has 16 bits, and it is divided into PC(L) (bits 1-8) and
PC(H) (bits 9-16).
Basic Register Transfer Statement:
A←B
Meaning:
 The contents of Register B are copied to Register A.
 The data in Register B remains unchanged.
 The previous contents of Register A are lost.
Conditional Transfer:
x’T1 : A ← B
Explanation:
 The data transfer happens only when the condition x’T1 = 1.
 Here, x’ (x NOT) is a Boolean condition (it must be 0 for transfer).
 T1 is a timing signal that must be 1 for transfer to occur.
 This means A ← B happens only when x = 0 and T1 = 1.
Hardware implementation of a controlled transfer: x’T1: A ← B is as
follows

For register-to-register transfer, the hardware consists of:

 Data lines connecting Register B's output to Register A's input.
 A load control signal for Register A (so it can receive data).
 Clock pulses that synchronize the transfer process.
 Logic gates (AND, NOT, etc.) to generate control signals.
When x’T1 = 1, the control signal activates Register A’s load input, allowing
it to receive data from Register B. The transfer happens in one clock cycle.
Handling Multiple Data Transfers to the Same Register
If a register receives data from two sources, a multiplexer (MUX) is used to
select the correct input.
T1 : C ← A
T5 : C ← B

 At T1, data from Register A moves to Register C.

 At T5, data from Register B moves to Register C.
 Since C cannot receive data from A and B at the same time, a
multiplexer (MUX) is used.
 When T5 = 1, Register B is selected.
 When T1 = 1, Register A is selected
The basic symbols of Register Transfer Logic are

Bus Transfer
In a digital computer, there are multiple registers, and data frequently needs
to be transferred between them. If each register were connected to every
other register with dedicated wires, the number of connections would be
excessive, leading to increased hardware complexity and cost.
To address this, a more efficient approach is used: the bus system.
What is a Bus?
A bus is a group of shared communication lines that multiple components
use to transfer binary information. Instead of having separate connections
between each register, a bus allows all registers to share a single data
pathway.
Each bit in a register is connected to a corresponding bus line, and control
signals determine which register is allowed to place data on the bus at a
given time.
Structure of a Bus System
A bus system consists of three main components:
1. Data Bus – Transfers actual data between components.
2. Control Bus – Carries control signals that specify read, write, or
transfer operations.
3. Address Bus – Holds the address of the memory location being
accessed (used for memory operations).
One way to construct a common bus system is by using multiplexers
(MUX). A multiplexer is a digital circuit that selects one input from multiple
sources and forwards it to the output.
In the context of a bus system, multiplexers control which register places its
data onto the bus at any given time.
Example of a 4-bit Bus System
Assume we have four registers (R1, R2, R3, and R4) each of 4 bits.
 Each register’s first bit (bit 0) is connected to MUX 0.
 Each register’s second bit (bit 1) is connected to MUX 1.
 Each register’s third bit (bit 2) is connected to MUX 2.
 Each register’s fourth bit (bit 3) is connected to MUX 3.
When a register is selected, its bits are transferred to the bus through the
multiplexers.
Working of the Bus Transfer System
 A control unit generates control signals that activate the correct
multiplexers and registers.
 The selected register places its data on the data bus.
 The destination register then loads the data from the bus.
This ensures that data is transferred efficiently without requiring direct
connections between all registers.
Advantages of the Bus System
 Reduces hardware complexity by minimizing the number of wires.
 Efficiently transfers data between multiple registers.
 Allows expansion without excessive rewiring.
Memory Transfer
Memory transfer refers to moving data between the CPU and memory.
There are two main types of memory operations:
1. Read Operation – Data is transferred from memory to a register.
Read: MBR←M
 2. Write Operation – Data is transferred from a register to memory.
Write: M ← MBR

Memory Transfer Notation

 Memory is represented by M.
 Memory Data Register (MDR) holds data during read/write
operations.
 Address Register (AR) holds the memory location to be accessed.
Memory Read Operation
Read: DR ← M [AR]
 The Address Register (AR) holds the memory address.
 The data at that address (M[AR]) is transferred to the Data Register
(DR).
 The CPU can then process the data in DR.
Example of Read Operation
If AR = 1000, the data stored in memory location 1000 is copied into DR.
DR ← M [1000]
Memory Write Operation
Write: M [AR] ← R1
 The CPU moves data from Register R1 to the memory location
specified by AR.
 This stores the contents of R1 into memory at address AR.
Example of Write Operation
If AR = 2000 and R1 = 11001100, the memory location 2000 will store the
value 11001100.
M [2000] ← 11001100
This ensures that the data in R1 is permanently stored in memory.
Interaction with Multiple Registers through Buses

A computer system typically has multiple registers (such as R1, R2, R3,
R4), and these registers communicate with memory using buses. Here's how
it works:

1. Address Bus:
o The Address Bus is responsible for carrying the memory
addresses.
o One of the registers connected to the address bus (such as
AR) can supply the address to the memory unit.
2. Data Bus:
o The Data Bus is used for transferring data between the
memory unit and the registers.
o The data can come from the memory and be transferred to a
register or vice versa.
3. Decoder:
o The Decoder is responsible for selecting which register will
receive the data from memory or which register will supply
the data to memory.
o The decoder ensures that only one register receives the data
at a time to avoid conflicts.

Here’s a simplified description of how these components interact:

 The address bus connects four registers (R1, R2, R3, R4), and any
one of these registers can supply the address to the memory unit.
 The memory unit sends data to the appropriate register through the
data bus. A decoder selects which register will receive the data.
 The data bus also connects to the memory unit, allowing data to be
written from one of the registers to memory.

Arithmetic, Logic and Shift Micro Operation

Arithmetic Micro-Operation
The basic arithmetic micro-operations are:
  Addition,
 Subtraction,
 Increment,
 Decrement
 Arithmetic shift.
The increment and decrement micro-operations are used to increase or
decrease the value in a register by one. These are simple operations,
typically executed using a combinational circuit or a binary up-down
counter. Here's an explanation of both:
 Increment (plus-one operation): This operation adds 1 to the value
stored in a register.
 Decrement (minus-one operation): This operation subtracts 1 from
the value stored in a register.
For the increment operation, a counter is often used, which is designed to
count up (increment) or down (decrement) based on control signals.
Arithmetic Add Micro-Operations
The arithmetic add micro-operation is an operation that adds the contents of
two registers and stores the result in a third register. This can be represented
in Register Transfer Language (RTL) as:
F←A+B
 A and B are the source registers containing the values to be added.
 F is the destination register where the sum is stored.
 The operation involves adding the contents of A and B and then
transferring the result into F.
To implement this, three registers (A, B, and F) are required, along with a
parallel adder that performs the addition operation.
Steps to Implement the Addition:
1. Registers A, B, and F are involved in the process.
2. The parallel adder takes the values from A and B as inputs and
produces a sum.
3. The sum is transferred to F via a load input in the register.
4. The control signal (timing variable) T2 triggers the transfer of the
sum from the parallel adder to F.
Example:
T2 : A ← A + B
T5 : A ← A + 1
 T2 (A ← A + B): This statement indicates that the contents of
register A will be added to the contents of register B using a parallel
adder. The result is then transferred back into A.
 T5 (A ← A + 1): This statement indicates that register A is
incremented by 1. This is typically done using a binary up-down
counter that increments the value in A.
Hardware Implementation of the Arithmetic Add:
1. The parallel adder takes the contents of A and B as inputs.
2. The sum produced by the adder is transferred into A when the T2
timing signal is activated.
3. For T5, register A is incremented by 1, using a counter that
increments the value and loads it back into A.

Multiplication and Division Micro-Operations

While the basic arithmetic micro-operations typically include addition,
multiplication and division are not included as basic operations in many
systems. These operations are implemented using sequences of other micro-
operations:
1. Multiplication: The multiplication operation is often implemented
using a sequence of add and shift operations. This is typically
referred to as repeated addition and shift-based multiplication.
o Multiplying a number by 2 can be achieved by shifting the
number left, and repeating the process can multiply by higher
powers of 2.
o For general multiplication, a series of shifts and additions are
used, such as in the shift-and-add multiplication algorithm.
2. Division: Division is usually implemented using a combination of
subtract and shift operations. This can be referred to as the restore
and non-restore division algorithms.
o Division by 2 can be achieved by shifting the number to the
right.
 o For general division, a sequence of subtract and shift
operations is used to repeatedly divide the dividend by the
divisor.
Logic Micro-Operations
Logic micro-operations specify operations that are performed on binary data
(strings of bits) stored in registers. These operations treat each bit of the
register separately and consider them as binary variables, meaning each bit
in the register is manipulated independently.

(XOR) operation, denoted by the symbol ⊕.

One of the most common logic micro-operations is the Exclusive-OR

Example of XOR Operation:

Consider two registers, A and B, each containing binary numbers. The
exclusive-OR micro-operation can be written as:
F←A⊕B
This means that the contents of registers A and B will undergo the XOR
operation bit by bit, and the result will be stored in register F.
Step-by-step Example:
 Content of register A: 1010
 Content of register B: 1100
The XOR operation compares corresponding bits of the two registers and
outputs 1 if the bits are different, and 0 if the bits are the same.

A⊕B(
Bit Position A B
F)

1st bit 1 1 0

2nd bit 0 1 1

3rd bit 1 0 1

4th bit 0 0 0
Thus, after performing the XOR operation:
F = 0110
The result of F ← A ⊕ B is 0110, which is the bit-by-bit exclusive-OR of
the two registers. This kind of operation is particularly useful in bit
manipulation tasks and making logical decisions, though they are rarely
used in scientific computations.
Logic and Shift Micro-Operations:
Logic and shift operations refer to the manipulation of individual bits or
groups of bits in a register. Some common logic operations include:
1. AND Operation (∧): A bitwise AND operation compares each bit of
two registers and outputs 1 if both bits are 1, otherwise it outputs 0.
2. OR Operation (∨): A bitwise OR operation compares each bit of two
registers and outputs 1 if either bit is 1, otherwise it outputs 0.
 3. Exclusive-OR (⊕): As shown in the previous example, XOR outputs
1 if the bits are different, and 0 if they are the same.
4. NOT Operation (¬): A bitwise NOT operation inverts the bits,
turning 1 to 0 and 0 to 1.
5. Shift Operations: These operations move the bits of a register to the
left or right. For example, a left shift operation moves the bits to the
left by a specified number of positions, which is equivalent to
multiplying the value by 2.

Control Functions and the Plus (+) Symbol:

In register transfer languages (RTL), the + symbol has different meanings
based on context:
1. Arithmetic Operation: When the + symbol appears in a micro-
operation between registers, it denotes arithmetic addition. For
example:
A←A+B
This operation adds the contents of register A to the contents of register B,
and the result is stored back into register A.
2. Logical OR in Control Functions: When the + symbol is used
between two timing variables or in a Boolean control function, it
represents a logical OR operation. For example:
T1 + T2 : A ← A + B, C ← D ∨ F
o The + between T1 and T2 means that T1 OR T2 triggers the
operations.

operation, and the ∨ between D and F denotes a logical OR

o The + between A and B specifies an addition micro-

operation between the contents of registers D and F.

Thus, in control functions:
 T1 + T2 means that either T1 or T2 can trigger the actions.
 The + used in an arithmetic operation between two registers signifies
addition.
Shift Micro-Operations
Shift micro-operations involve the movement of data within registers,
specifically moving the bits to the left or right. These operations are useful
in many cases, including data serialization, as well as in arithmetic, logic,
and other data-processing operations. Shifting allows for efficient
manipulation of data by adjusting bit positions.
Shift operations don't have a standardized symbol like arithmetic or logical
operations. Instead, we use the following:
 shl (Shift Left): Shifts the bits in the register to the left.
 shr (Shift Right): Shifts the bits in the register to the right.
Basic Shift Operations:
1. Shift Left (shl):
o Operation: A ← shl A
o Description: This operation shifts the contents of register A
one bit to the left. The bit that is shifted out of the leftmost
position is discarded, and a 0 is inserted into the rightmost
position.
o Example: If A = 1011, after the shift left:
A ← shl A
A = 0110
Here, the leftmost bit 1 is discarded, and 0 is added to the right.
2. Shift Right (shr):
o Operation: B ← shr B
o Description: This operation shifts the contents of register B
one bit to the right. The bit shifted out of the rightmost
position is discarded, and a 0 is inserted into the leftmost
position.
o Example: If B = 1101, after the shift right:
B ← shr B
B = 0110
Here, the rightmost bit 1 is discarded, and 0 is added to the left.
Types of Shifts:
1. Logical Shift:
o Description: In a logical shift, bits are moved into the shifted
position from a fixed value (typically 0).
o Logical Shift Left (shl): The leftmost bit is discarded, and 0
is inserted into the rightmost bit.
o Logical Shift Right (shr): The rightmost bit is discarded, and
0 is inserted into the leftmost bit.
Example:
o A = 1011 (before)
o A ← shl A
  Result: A = 0110
o B = 1101 (before)
o B ← shr B
 Result: B = 0110

2. Circular Shift:
o Description: In a circular shift, the bit shifted out of the
register is reintroduced at the opposite end. This means the
data circulates around the register.
o Circular Shift Left (rotate left): The leftmost bit is transferred
to the rightmost position.
o Circular Shift Right (rotate right): The rightmost bit is
transferred to the leftmost position.
Example:
o A = 1011 (before)
o A ← shl (circular) A
 Result: A = 1101 (leftmost bit 1 is transferred to the
rightmost position)
o B = 1101 (before)
o B ← shr (circular) B
 Result: B = 1110 (rightmost bit 1 is transferred to the
leftmost position)
3. Arithmetic Shift:
o Description: Arithmetic shifts are used with signed binary
numbers (usually in 2's complement form). The main
difference with logical shifts is that the leftmost bit (sign bit)
is preserved during shifts to maintain the correct sign.
o Arithmetic Shift Left (shl): This is similar to the logical shift
left, where the leftmost bit is discarded and 0 is added to the
rightmost position.
o Arithmetic Shift Right (shr): In this case, the leftmost bit
(sign bit) is preserved, meaning that 1 will be added to the
left if the number is negative (sign bit is 1), and 0 if the
number is positive.
Example:
o A = 1011 (signed 2's complement representation of -5)
o A ← shr A (arithmetic)
 Result: A = 1101 (sign bit is preserved, negative
number remains negative)
o B = 0110 (signed 2's complement representation of +6)
 o B ← shr B (arithmetic)
 Result: B = 0011 (sign bit is preserved, positive
number remains positive)
Shift Operation and Timing:
 Timing Variable Example for Shift Left:
o T1: A ← shl A
 The contents of A are shifted left, and the new value
is stored in A.
 The bit from the serial input is transferred to the
rightmost bit of A.
 Timing Variable Example for Shift Right:
o T2: B ← shr B
 The contents of B are shifted right, and the new value
is stored in B.
 The bit from the serial input is transferred to the
leftmost bit of B.

Processor Organization
 Processor as Data Path:
o The processor in a CPU is often referred to as the data path
because it forms the pathways for data transfers between the
various registers within the CPU.
 Data Path Control:
o The data paths are controlled by gates that open specific
paths for data flow and close all other paths to prevent
interference.
 Design Flexibility:
o A processor unit can be designed to meet the specific
requirements of an application, enabling customized data
paths for different tasks.
 Formation of Data Paths:
o Data paths are formed using buses and other common lines,
which are shared communication channels for transferring
data between components.
 Control Gates:
o The control gates that regulate the data paths are primarily
multiplexers and decoders. These components decide which
path the data will take based on control signals.
 Multiplexers and Decoders:
o Multiplexers (MUX): Select which input line will be
connected to the output, based on control signals.
o Decoders: Help in selecting the right component (register,
memory, etc.) by interpreting the control signals.
 Data Processing:
o The actual processing of information is carried out by a
common digital function (e.g., the ALU) which performs
operations like arithmetic or logic operations.
  Selection Variables:
o The path for data to move through the processor is defined by
a set of common selection variables that dictate how data is
routed through the system. These variables help the processor
determine which registers or functional units should be used
for each operation.
Bus Organization
In a processor system with a bus organization, multiple registers are
connected to a shared set of buses and functional units. Here’s an
explanation of how it works, breaking down the process of performing
operations like R1 ← R2 + R3:
A. Registers and Multiplexers (MUX):
a. Each register is connected to two multiplexers (MUX) that
form two separate buses: bus A and bus B.
b. These multiplexers choose which register's data will be sent
to the respective bus (A or B). Each register has a selection
line that determines which register's value will be placed on
the bus.
B. Arithmetic Logic Unit (ALU):
a. The A and B buses are connected to the Arithmetic Logic
Unit (ALU). The ALU can perform operations (like addition,
subtraction, etc.) on the data that comes from these buses.
b. The operation to be performed in the ALU is determined by
the ALU function selector.
C. Shift Operations:
a. The processor may perform shift micro-operations using a
shifter. If no shift operation is needed, the data flows directly
from the ALU output to the S output bus.
D. Output Bus (S):
a. The result of the operation (whether from the ALU or shift
operation) goes through the output bus (S). This bus connects
the results to all the registers.
E. Register Selection:
a. To determine which register will receive the data from the
output bus, a decoder is used. The decoder activates the load
input of the selected register, allowing the transfer of the data
from the S bus into that register.
F. External Data Input:
a. One of the inputs of MUX A or MUX B can receive data
from an external source. This allows the processor to input
data from outside the CPU if needed.
G. Control Unit:
a. The control unit manages the entire process. It sends out
control signals to direct the flow of information in the
 system. It sets the selection lines of the multiplexers, the
ALU function, the shifter, and the destination register
decoder.
H. Example: Performing R1 ← R2 + R3
I. MUX A Selection:
a. The MUX A selector will be set to choose R2 (the contents of
register R2) to place it on bus A.
II. MUX B Selection:
a. The MUX B selector will be set to choose R3 (the contents
of register R3) to place it on bus B.
III. ALU Operation:
a. The ALU function selector will instruct the ALU to perform
the addition (A + B) operation using the values from buses A
and B.
IV. Shift Selector:
a. Since no shift operation is required for this example, the shift
selector is set for direct transfer from the ALU output to the
output bus S (no shift).
V. Destination Register:
a. The decoder destination selector will activate the load input
of R1, which will receive the result from bus S. In this case,
R1 ← R2 + R3 will be executed.
Scratchpad Memory

 It is a small memory unit embedded within the processor, typically

used to temporarily store data during processing. This small memory
serves as an alternative to a bus system, reducing the need for
complex and expensive bus structures.

How Scratchpad Memory Works:

 Registers and ALU: In a processor using scratchpad memory,

registers are selected from memory and loaded into registers A and
B. These registers are then processed in the Arithmetic Logic Unit
(ALU) and shifter.
 Memory Operations: Once the operation is performed in the ALU
(e.g., an addition), the result is transferred back to a memory
register. This requires specifying the word address in memory and
activating the memory-write control input.
Steps for Performing an Operation (e.g., R1 ← R2 + R3):

1. T1: Load Data into Register A

o The memory address M[010] corresponds to R2, so the
control function T1 will:
 Provide the address 010.
 Activate the read and load A inputs, so the contents of
R2 are read and placed into Register A.
2. T2: Load Data into Register B
o The memory address M[011] corresponds to R3, so the
control function T2 will:
 Provide the address 011.
 Activate the read and load B inputs, so the contents of
R3 are read and placed into Register B.
3. T3: Perform the Addition in the ALU and Store the Result
o ALU Operation: The control function T3 will:
 Supply the necessary function code to the ALU to
perform the addition operation on the contents of
Register A and Register B.
 Apply the memory address 001, which corresponds to
R1.
 Activate the write input of the memory to store the
result in R1.
Key Points:

 Memory Addressing: The memory has 8 words, so each address

must be 3 bits long. Each control function specifies the memory
address for reading or writing data.
 Control Signals: The control unit manages the memory operations by
sending specific signals to:
o Memory read/write.
o Register loading.
o ALU operations.
o Memory address selection.

Two-Port Memory:

Some processors use 2-port memory to avoid delays when reading two
source registers. This type of memory has two separate address lines that
allow two memory locations to be accessed simultaneously, improving the
speed of read operations.

Example for 2-Port Memory:

 2-port memory: It allows two registers to be read at the same time.

Instead of waiting for one memory read to complete before starting
the next one, both memory reads can be done in parallel, thus
reducing delays.

Accumulator Register

An accumulator is a specialized register within a computer’s CPU used for

short-term, intermediate storage of data during arithmetic and logic
operations. The accumulator plays a critical role in handling sequential
operations, such as addition.

Primary Function:

 The accumulator is commonly used to add a sequence of numbers.

 As each new number is added to the accumulator, its value increases,
just like adding numbers on a calculator.
 Once the sum or result is determined, it can either be written to main
memory or transferred to another register for further use or
computation.
Characteristics:

 While its main function is to perform add operations, the

accumulator can perform a range of other operations as well, making
it a multipurpose register.

Example of How the Accumulator Works:

To add two numbers stored in processor registers, the following sequence of

micro-operations is used:

1. T1: A ← 0
o This step clears the accumulator (sets it to zero) before
starting the addition.
2. T2: A ← A + R1
o The contents of register R1 are added to the accumulator (A).
Now, A holds the value of A + R1.
3. T3: A ← A + R2
o The contents of register R2 are added to A. The accumulator
now holds the sum of A + R1 + R2.

Result Usage:

 The sum formed in A can now be used for further computation or

transferred to a required destination, such as memory or another
register, depending on the needs of the program.

Status Registers
A status register is a special-purpose register that holds flag bits, which are
used to indicate the result of an arithmetic or logical operation performed in
the ALU (Arithmetic Logic Unit). These bits, often referred to as condition-
code bits or flag bits, help determine the relative magnitude of two numbers
and provide information about the operation's result.

Flag Bits in the Status Register:

A status register typically consists of 4 bits, which are defined as follows:

1. C (Carry):
o Set if the ALU generates an output carry (i.e., if there is a
carry out of the most significant bit during an addition
operation).
2. S (Sign):
o Set to 1 if the highest order bit (most significant bit) of the
result is 1, indicating a negative number in a signed
operation.
3. Z (Zero):
o Set to 1 if the ALU output is all 0s (i.e., the result of the
operation is zero).
4. V (Overflow):
o Set if the exclusive-OR of the carry bits C8 and C9 is 1,
indicating an overflow condition when the numbers are in
signed 2's complement representation.
o For example, for an 8-bit ALU, V is set if the result is greater
than 127 or less than -128.

How Status Flags Are Used:

The status bits can be used to understand the relationship between two
values (A and B) after an operation. Here's how each flag bit is used:

 C (Carry):
o C = 1: A ≥ B (A is greater than or equal to B).
o C = 0: A < B (A is less than B).
 Z (Zero):
o Z = 1: A = B (The result of A - B is zero, so A and B are
equal).
 o Z = 0: A ≠ B (A is not equal to B).
 S (Sign):
o S = 1: The result is negative (the most significant bit is 1).
o S = 0: The result is positive (the most significant bit is 0).
 V (Overflow):
o V = 1: Overflow condition for signed 2's complement
numbers, indicating that the result is out of the representable
range (greater than 127 or less than -128 in an 8-bit system).
o V = 0: No overflow condition.

Example: Using Status Register to Check Relative Magnitudes

When performing a compare operation, the following conditions can be

checked using the status bits after performing A - B for two unsigned
numbers:

 Z = 1: A = B (The result of A - B is zero, so A equals B).

 Z = 0: A ≠ B (The result is non-zero, so A is not equal to B).
 C = 1: A ≥ B (If there is a carry, A is greater than or equal to B).
 C = 0: A < B (If there is no carry, A is less than B)

Arithmetic and Logic Unit

An Arithmetic Logic Unit (ALU) is a fundamental component of a CPU that

performs arithmetic and logic operations. It is a combinational logic circuit
capable of executing multiple operations based on the control signals it
receives.

Functions of ALU

The ALU typically performs two main types of operations:

1. Arithmetic Operations: Addition, subtraction, multiplication,

division, increment, and decrement.
2. Logic Operations: AND, OR, XOR, NOT, and bitwise shifting
operations.

Selection of Operations

 The ALU has a set of selection lines that determine which operation
will be performed.
 These selection lines are decoded internally, allowing the ALU to
execute up to 2ᵏ operations, where k is the number of selection lines.

The figure shows the block diagram of 4-bit ALU.

ALU Design Stages

The design of a typical ALU involves three main stages:

1. Designing the Arithmetic Section:

o This section handles operations like addition, subtraction,
and other arithmetic functions.
2. Designing the Logic Section:
o This section is responsible for performing logical operations
such as AND, OR, and XOR.
3. Combining Arithmetic and Logic Functions:
o The arithmetic section is modified so that the ALU can
switch between arithmetic and logic operations using control
signals.

By integrating both arithmetic and logic functions into a single unit, the
ALU enables a processor to execute a wide range of computations
efficiently.

Design of Arithmetic Circuit

The arithmetic section of an Arithmetic Logic Unit (ALU) is primarily built

using a parallel adder, which is a combination of multiple full-adder circuits
connected in cascade.

Parallel Adder and Arithmetic Operations

 A parallel adder allows multi-bit binary addition by using full adders

for each bit position.
 It takes two binary numbers as inputs and produces their sum along
with a carry-out (Cout) if needed.
Control of Input B for Different Arithmetic Operations

 The B input to the parallel adder is modified externally to perform

different arithmetic operations.
 The input carry (Cin) is fed into the least significant bit (LSB) full
adder, while the output carry (Cout) is generated from the most
significant bit (MSB) full adder.

Working of the Arithmetic Circuit

 The number of bits in the parallel adder determines how many bits
can be processed simultaneously.
 The input A is fed directly into the parallel adder.
 The input B is modified based on the required arithmetic operation.
 The function table for the arithmetic circuit is given below.

Design of Logic Circuit

The logic micro-operations manipulate individual bits of the operands,

treating each as a separate binary variable. These operations are
implemented using logic gates and selected using multiplexers.

Logic Circuit and Selection Variables

 A logic circuit can generate 16 logic operations, but a practical

approach is to implement just AND, OR, NOT, and XOR, since all
others can be derived from them.
 A multiplexer (MUX) with two selection variables (S1, S0) is used
to choose among four logic operations.
 If we need both arithmetic and logic operations, a third selection
variable (S2) is introduced to switch between them.

Basic Logic Circuit Design

 The circuit consists of four logic gates: AND, OR, NOT, and XOR.
 The multiplexer selects one of these operations based on the
selection variables.
 For an n-bit logic unit, the circuit is repeated n times to process all
bits simultaneously.

Combining Arithmetic and Logic Circuits

 The arithmetic unit (parallel adder) and logic unit (logic circuit) can
be merged into a single ALU.
 The selection variable S2 is used to choose between the two:
o S2 = 0 → Selects arithmetic operation.
o S2 = 1 → Selects logic operation.
Optimizing the ALU Design

 Instead of using separate hardware for logic operations, we can

modify the arithmetic circuit to generate logic operations.
 The full-adder output (sum function) is:

F=X⊕Y⊕Cin

 If we force the carry-in (Cin) to 0 when S2 = 1, the equation

simplifies to:

F=X⊕Y

 This effectively implements the XOR operation, showing how logic

operations can be derived from an arithmetic circuit.

This optimization reduces hardware complexity and results in a more

efficient ALU design.

Design of Arithmetic Logic Unit

An Arithmetic Logic Unit (ALU) is the core computational component of a

processor, capable of performing both arithmetic and logic operations.
Instead of designing separate circuits for arithmetic and logic, they are
combined into a single efficient unit using selection variables.

ALU Design Approach

The ALU is designed using three selection variables (S2, S1, S0):

 S1, S0: Common to both arithmetic and logic sections.

 S2: Determines whether the operation is arithmetic (S2 = 0) or logic
(S2 = 1).

The design steps are:

1. Design the arithmetic section separately from the logic section.

2. Analyze the logic operations that can be obtained naturally from the
arithmetic circuit (assuming all input carries are 0).
3. Modify the arithmetic circuit to incorporate required logic functions.

This final step is not always straightforward and often requires innovative
thinking.

Boolean Expressions for ALU Design

Each bit position in the ALU consists of a full-adder circuit, where the
inputs are controlled based on the selection variables.

The Boolean expressions defining the ALU’s input signals at each bit
position are:

1. Xi = Ai + S2 S1’ S0’ Bi + S2 S1 S0’ Bi

2. Yi = S0 Bi + S1 Bi’
3. Zi = S2’ Ci
Behaviour of the ALU Based on Selection Variables

Case 1: Arithmetic Operations (S2 = 0)

When S2 = 0, the ALU operates in arithmetic mode, and the expressions

simplify to:

 Xi = Ai (Directly passes operand A)

 Yi = S0 Bi + S1 Bi’ (Implements arithmetic control over operand B)
 Zi = Ci (Carries are propagated normally, enabling addition)

Case 2: Logic Operations (S2 = 1)

For S2 = 1, the ALU operates in logic mode, and for specific values of S1,
S0, we get:

 Xi = Ai (Same as arithmetic mode)

 Yi = S0 Bi + S1 Bi’ (Implements logical operations)
 Zi = 0 (Carry input is suppressed, ensuring logical operations)

Final ALU Structure

 The first two stages of the ALU are illustrated in the block diagram
(which can be extended for more stages).
 The full-adder circuits are controlled by the selection variables,
allowing seamless switching between arithmetic and logic operations
 The function table for the Arithmetic and Logic Unit is shown below

Design Of Combinational Logic Shifter

combinational logic shifter is a circuit that transfers data from the ALU to
the output bus while also providing shifting operations. It eliminates the
need for sequential clock pulses, making shifting operations faster and more
efficient compared to using shift registers.

Functions of the Shifter

The shifter can operate in four different modes, depending on the control
signals:

1. No Shift (H1 H0 = 00)

o The data from the ALU is directly transferred to the output
bus without any changes.
2. Shift Right (H1 H0 = 01)
o Each bit in the data moves one position to the right.
o The rightmost bit (LSB) is usually replaced with 0 or a carry
bit, depending on the design.
3. Shift Left (H1 H0 = 10)
o Each bit moves one position to the left.
o The leftmost bit (MSB) is typically filled with 0 or another
control value.
4. No Operation (H1 H0 = 11)
o No data is transferred from the ALU to the output bus.
Implementation Using a Combinational Circuit

Instead of using a shift register, which requires multiple clock pulses for
loading and shifting data, a combinational shifter can be built using
multiplexers (MUX). This design:

 Reduces the number of clock cycles required for shifting.

 Allows immediate data transfer from the ALU to the output bus.
 Simplifies control logic with two selection variables (H1, H0).

Each bit of the data is passed through a multiplexer, which selects one of the
four possible operations based on the values of H1 and H0.

Advantages of a Combinational Shifter

 Faster Execution – No need for extra clock cycles.

 Simplified Control Logic – Only two control bits are required.
 Efficient Design – Uses multiplexers instead of shift registers,
reducing hardware complexity.

This design ensures that data shifting is performed instantly without

unnecessary delays, making it ideal for high-speed processors.

Processor Unit

This processor unit consists of multiple registers, an ALU, multiplexers, a

shifter, and external input and output connections. The primary function of
this unit is to perform arithmetic and logic operations on data stored in
registers and transfer the processed data either to another register or to an
external output.

Components of the Processor Unit

1. Registers (R1 – R7) and Status Register

o Seven general-purpose registers store data for processing.
o The status register holds condition flags like Carry (C), Zero
(Z), Sign (S), and Overflow (V).
2. Multiplexers for Register Selection
o There are two multiplexers to select the inputs to the ALU.
o These multiplexers allow selecting either register values or
external input data.
o The A and B selection variables determine the two input
operands for the ALU.
3. Arithmetic Logic Unit (ALU)
o Performs arithmetic and logic operations based on the control
signals.
o The F field (3-bit control) along with the carry input (Cin)
selects one of 12 possible operations.
o Some operations depend on whether the carry flag (C) is set
or cleared.
4. Shifter
o The output from the ALU passes through a shifter before
reaching the external output.
o The shifter can shift left, shift right, or pass data unchanged.
 5. Output Selection
o The D selection variable decides the destination register.
o If D = 000, no destination register is selected, meaning the
operation result is not stored in any register.
o The processed data can also be sent to external output
terminals.

The functions of all selection variables are specified in table below.

Selection Codes and Functions

 The 3-bit binary codes control the selection of registers and

operations.
  A, B, and D fields select registers based on their corresponding
binary values.
 The F field, combined with the carry input, determines ALU
operations.

This structure allows efficient manipulation of data, with flexible input

selection, arithmetic and logic processing, and controlled output transfer.

Design Of Accumulator

An accumulator is a special-purpose register in a processor used for

intermediate storage of arithmetic and logic data. It consists of an A register
and an associated combinational circuit, which together form a sequential
circuit. The accumulator plays a key role in performing arithmetic and logic
operations efficiently.

Structure of the Accumulator

 The A register stores the current value and updates it based on

microoperations.
 The combinational circuit performs arithmetic and logic operations
using external inputs.
 The accumulator cannot be separated from the combinational circuit,
as they function together as a single unit.
 In many processors, the accumulator is denoted as AC.

Inputs to the Accumulator

 Data Input (B Register): The second operand in arithmetic

operations.
 Control Variables (P1 to P8): Determine the specific
microoperation to be executed.
 Clock Pulses (CP): Synchronize the updates in the accumulator.
 Zero Detect Chain: Helps identify whether the accumulator

contains a zero value.

Operations Performed by the Accumulator

A total of nine microoperations are considered in this design. Each

microoperation modifies the contents of the accumulator register.

 The source register is always A (accumulator itself).

 The B register serves as the second operand.
  The destination register remains A, meaning all results are stored
back in the accumulator.

Accumulator can also perform data processing operations. Total of nine

operations is considered here for the design of accumulator circuit.

Design of a 4-bit Accumulator

 A 4-bit accumulator consists of four interconnected stages.

 Each stage processes a single bit and passes data to the next stage.
 The zero detect chain connects the stages in sequence, generating a
final zero detect output (Z).

IC Design Considerations

 A 4-bit accumulator requires 25 terminals (including power supply).

 By incorporating a decoder, the number of control terminals can be
reduced from 9 to 4.
 A decoder-based design allows up to 16 microoperations without
adding extra IC pins.
 This reduces the total IC pin count to 22 while extending the
functionality of the accumulator.