DSD ASSIGNMENT 3
Q1:
Working Principle of Basic Flip-Flops Using FSM Modelling
Finite State Machines (FSMs) are a mathematical way to model the behaviour of flip-
flops. A flip-flop is a bistable device, meaning it has two stable states (0 and 1), and it
changes state based on input and a clock signal.
a. D-Flip Flop (Data Flip-Flop)
Working Principle:
The D-Flip Flop captures the value of the D (data) input at the rising or falling edge of
the clock and holds it until the next clock cycle.
It eliminates any ambiguity by directly controlling the state.
FSM Modelling:
State Diagram (FSM):
Fig.1 (state diagram of d flip-flop)
1. States: Two states S0 (Q=0) and S1 (Q=1).
2. Inputs: Clock (triggered on rising or falling edge) and Data input D.
3. Transitions:
If D = 0, the next state is Q = 0 (regardless of the current state).
If D = 1, the next state is Q = 1 (regardless of the current state).
4. Output Function: Q= D after the clock edge.
State table:
Current state Input D Next state Qn Output Q
0 0 0 0
0 1 1 1
1 0 0 0
1 1 1 1
b. T-Flip Flop (Toggle Flip-Flop)
Working Principle:
The T flip-flop toggles its output state Q whenever the T input is 1, on the triggering
clock edge.
If T=0, the output Q remains unchanged.
FSM Modelling:
State diagram:
Fig.2 (state diagram of T flip-flop)
1. States: Two states S0 (Q=0) and S1 (Q=1).
2. Inputs: Clock and Toggle input T.
3. Transitions:
If T=0, remain in the current state.
If T=1, toggle to the other state.
4. Output Function: Qn=Q⊕T.
State table:
Current state Input T Next state Qn Output Q
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
c. J-K Flip Flop
Working Principle:
The J-K flip-flop combines the functionality of the S-R flip-flop but resolves
the ambiguity when S=R=1.
It toggles the output when J=K=1.
When J=0, K=1, it resets Q.
When J=1, K=0, it sets Q.
FSM Modelling:
State diagram:
1. States: Two states S0 (Q=0) and S1 (Q=1).
2. Inputs: Clock, J, and K.
3. Transitions:
o J=0, K=0: No change in state.
o J=0, K=1: Move to S0.
o J=1, K=0: Move to S1.
o J=1, K=1: Toggle the state.
4. Output Function: Qnext=J(~Q)+(~K) Q.
State table:
Current state Input J Input k Next state Qn Output Q
0 0 0 0 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 0
1 1 0 1 1
1 1 1 0 0
Q2:
D Flip-Flop:
Design code:
module d_flip_flop (
input wire D, // Data input
input wire clk, // Clock input
input wire rst, // Reset input (active high)
output reg Q // Output
);
always @(posedge clk or posedge rst) begin
if (rst)
Q <= 1'b0; // Reset output to 0
else
Q <= D; // Capture D on clock edge
end
endmodule
Testbench code:
module tb_d_flip_flop;
reg D, clk, rst; // Testbench signals
wire Q; // Output wire
Output:
Fig1. (monitor output output)
Fig2. (Waveform output)
Explanation:
The output Q follows the input D at every rising edge of the clock signal (clk), as
long as the reset (rst) is not active. If reset is active, Q is set to 0.
If reset is not active, and clock is high the Output Q equals input D.
b. T flip-flop
design code:
`timescale 1ns / 1ps
`timescale 1ns / 1ps
module tb_t_flip_flop;
module t_flip_flop (
reg T, clk, rst; // Testbench signals
input wire T, // Toggle input
wire Q; // Output wire
input wire clk, // Clock input
input wire rst, // Reset input (active high)
t_flip_flop DUT (
output reg Q // Output
.T(T),
);
.clk(clk),
always @(posedge clk or posedge rst) begin
.rst(rst),
if (rst)
.Q(Q)
Q <= 1'b0; // Reset output to 0
);
else if (T)
initial begin
Q <= ~Q; // Toggle output
clk = 0;
end
forever #5 clk = ~clk;
endmodule
end
initial begin
rst = 1; T = 0;
#10
rst = 0; T = 1;
#10 T = 0;
#10 T = 1;
#10 T = 1;
#10
$finish;
end
initial begin
$monitor("clk = %b | T = %b | rst = %b | Q = %b", clk, T, rst, Q);
end
endmodule
Fig1. (monitor output output)
Fig2. (Waveform output)
Explanation:
The output Q toggles its state at each rising clock edge when T=1. If T=0, Q
remains unchanged. Reset (rst) forces Q to 0 when active.
If reset is low and clock is high and T = 1 the output toggles, if output Q = 0 it
toggles to 1 and if the output Q = 1 it toggles to 0.
c. JK Flip-flop:
design code:
`timescale 1ns / 1ps
module jk_flip_flop (
input wire J, // J input
input wire K, // K input
testbench code:
`timescale 1ns / 1ps
module tb_jk_flip_flop;
reg J, K, clk, rst; // Testbench signals
wire Q; // Output wire
jk_flip_flop DUT (
.J(J),
.K(K),
.clk(clk),
.rst(rst),
.Q(Q)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1; J = 0; K = 0;
#10 rst = 0; J = 1; K = 0; // Set
#10 J = 0; K = 1; // Reset
#10 J = 1; K = 1; // Toggle
#10 J = 0; K = 0; // No change
#10 J = 1; K = 1; // Toggle again
#10 $finish;
end
initial begin
$monitor("clk = %b | J = %b | K = %b | rst = %b | Q = %b", clk, J, K, rst,
Q);
end
endmodule
Output:
Fig.1 Monitor Output
Fig.2 Waveform Output
Explanation:
When both J=1 and K=1, Q toggles its state on the rising clock edge. For other J
and K combinations, Q either sets, resets, or holds its previous state. If reset (rst)
is active, Qs reset to 0.
If clock is high, reset is low and j = 1, k = 0, the output Q=1, if j = 0, k=1, the
output is Q=0.
