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I/O:
Serial Communication
Protocols

COEN 421/6341: Embedded Systems Design

Serial Communication
• Transfer a single bit each time
• UART
• I2C
• SPI

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UART

• Universal Asynchronous Receiver and Transmitter

• Bits are transmitted in a serial fashion
• It does not require the sender to provide a clock signal to the receiver
• Sender and receiver must agree on the data transmission rate before
communication starts

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UART: Connections
• Data transmitted from Tx pin and received at Rx pin in the receiver
• The protocol is point-to-point
- No addressing is needed

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UART: Connections

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UART: Frame
• Data to be transmitted is divided into frames
• Frame:
- Start bit: Represented by a low-level voltage
- Data length (7, 8 or 9 bits)
- Parity bit (even, odd, none):
• High-level voltage - logic 0/low-level voltage – logic 1
- Stop bit(s) (0.5, 1, 1.5, or 2 bits):
• Represented by a high voltage
• The voltage of the transmission line remains high if no further data is transmitted

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UART: Baud Rate

• It is the measure of the number of changes to the signal (per second) that
propagate through a transmission medium
• Speed in which signal levels can change
• Baud rate ≠ bit rate
- Bit rate: number of bits per seconds that the user can push through the transmission
system
• Bit rate ≠ data bit rate
- Data bit rate: number of data bits per seconds.
• E.g., baud rate of 9600. For an 8-N-1 frame, data bit rate:
= (# data bits/# frame bits)*baud rate

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UART
• E.g., 8-N-1. Transmission of two data bytes: 0x32 and 0x3C. LSB is
transmitted first

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UART baud rate

• Baud rate is different from bit rate
• Baud rate
- Represents the number of pulses or transitions physically transferred by
second
• Bit rate can be higher than baud rate when multiple binary bits can be
represented in a pulse
• Bit rate can be lower than baud rate when each pulse represents a
single bit
- Baud rate is the number of bits physically transferred per second (data
content + protocol overhead)

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UART Baud Rate

• Example:
- Baud rate -> 9600
- UART configuration: 8-N-1
• Frame: Start bit + 8 data bits + Stop bit (no parity bit)

- Transmission rate of data is not 9600 bits per second / - 1200 bytes

- Since each frame has 10 bits (Start + 8D + Stop), 960 frames will be
transferred per second

- Since each frame has 1 byte, 960 bytes will be transferred per second
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UART Communication
• Check pinout of the MCU to see how the connection will be made
between the UART ports of the communicating entities
- Dev. 1 Tx connects with Dev. 2 Rx
- Dev. 1 Rx connects with Dev. 2 Rx
- GND to GND
• Check the pin functions
• Example:

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UART Communication

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Registers
• GPIO port mode register (GPIOx_MODER) (x =A to I) – AO: 0x00
• GPIO port output type register (GPIOx_OTYPER) (x = A to I) - AO: 0x04
• GPIO port output speed register (GPIOx_OSPEEDR) (x = A to I) - AO: 0x08
• GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to I) - AO: 0x0C
• GPIO port input data register (GPIOx_IDR) - AO: 0x10
• GPIO port output data register (GPIOx_ODR) (x = A to I) - AO: 0x14
• GPIO port bit set/reset register (GPIOx_BSRR) (x = A to I) - AO: 0x18
• GPIO port configuration lock register (GPIOx_LCKR) (x = A to I) – AO: 0x1C
• GPIO alternate function low register (GPIOx_AFRL) (x = A to I) – AO: 0x20
• GPIO alternate function high register (GPIOx_AFRH) (x = A to I) – AO: 0x24
• GPIO port bit reset register (GPIOx_BRR) (x = A to I) – AO: 0x24
• GPIO port analog switch control register (GPIOx_ASCR)(x = A to H(a)) – AO: 0x2C

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Registers Map
Not all of them use the 32 bits

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Registers Map

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UART
1. Define the pointer for the port you will use
- Port A
#define GPIOA ((GPIO_TypeDef *) 0x48000000

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UART
2. Clear MODE register for the pins to be used and set the alternate
function mode in the MODE register for the pins to be used

GPIOA->MODER &= ~(0b11 << (2*pin)); //zero the bits for the pin ``pin’’
GPIOA->MODER |= 0b10 << (2*pin); //10 -> alternate function

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UART 2

3. Configure the alternate functions

register
1

4
GPIOA->AFR[1] |= 1UL << 4; 3

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UART

4. Configure the other GPIO registers

- E.g., OSPEEDR, PUPDR, OTYPER

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UART

5. Find the memory base address for the UART port to be used

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UART

6. UART/USART registers
- Data frame 7, 8, or 9 bits

This information is set

in the Control
Register 1 (CR1)

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UART

6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)

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UART

6. UART/USART registers stm32f4xx.h

- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Disable UART port
UARTx->CR1 &= ~USART_CR1_UE;

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UART

6. UART/USART registers stm32f4xx.h

- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
UARTx->CR1 &= ~USART_CR1_M;

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UART

6. UART/USART registers stm32f4xx.h

- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
UARTx->CR2 &= ~USART_CR2_STOP;

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UART

6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
- Set parity control (no parity in this case)
UARTx->CR1 &= ~USART_CR1_PCE;

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UART

6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
- Set parity control (no parity in this case)
- Set oversampling
UARTx->CR1 &= ~USART_CR1_OVER8;

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UART

6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
- Set parity control (no parity in this case)
- Set oversampling
- Set baud rate BRR register stores the USARTDIV
UARTx->BRR = 0x208D; //For a targeted 9600 baud rate when clock is 80MHz
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UART

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UART
6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
- Set parity control (no parity in this case)
- Set oversampling
- Enable transmission and reception

USARTx->CR1 |= (USART_CR1_TE | USART_CR1_RE);

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UART
6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
- Set parity control (no parity in this case)
- Set oversampling
- Enable transmission and reception
- Enable USART
USARTx->CR1 |= USART_CR1_UE;

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UART
6. UART/USART registers
- Data frame 7, 8, or 9 bits
- USART_CR1 (address offset: 0x00)
- Set data length (8 bits in this case)
- Select the stop bit configuration (1 in this case)
- Set parity control (no parity in this case)
- Set oversampling
- Enable transmission and reception
- Enable USART
- Verify if the configured port is ready for transmission and reception

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UART

6. Read function

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UART

6. Write function

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UART

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UART via Interrupt

An USART interrupt can be generated upon the occurrence of
several events, such as transmission data register empty (TxE),
transmission complete (TC), received data register not empty
(RXNE), overrun error detected (ORE), idle line detected (IDLE),
and parity error (PE).

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UART via Interrupt

1. Enable UART interrupts to send or receive data

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UART via Interrupt

2. Write the handlers

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UART via Interrupt

2. Write the handlers

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Inter-Integrated Circuit (I2C)

• Enables communication between microprocessor and their peripheral devices by
using two wires
- Serial data line (SDA)
- Serial clock line (SCL)
• Each device has a unique address
- 7, 10, or 16 bits
• Each device can serve as a transmitter, a receiver, or both
- a digital temperature sensor may operate only as a transmitter
- an LCD driver may operate only as a receiver
- a memory device can be both a transmitter and a receiver
• Master device:
- 1) Initializes a data transfer on the bus
- 2) Generates the clock signals to permit that data transfer
- 3) Terminates the transfer after receiving all requested information

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Inter-Integrated Circuit (I2C)

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Inter-Integrated Circuit (I2C)

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Inter-Integrated Circuit (I2C)

• The communication begins with a START bit (S) and terminates by a
STOP bit (P)
- A START bit is defined as a high-to-low transition of SDA while SCL is high
- A STOP bit is defined as a low-to-high transition of SDA while SCL is high.
• The master generates both START and STOP bits

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Inter-Integrated Circuit (I2C)

• The master begins to send data byte by byte after the START bit
• For each byte, the most significant bit is transferred first
• The slave sends an acknowledge bit to the master, informing the master that the
slave has successfully received a byte
- The receiver should answer the transmitter with either an acknowledge (ACK) bit or a not
acknowledge (NACK) bit
When a master sends data to a slave, a NACK answered by the
slave means that the communication has failed. The master
needs to either generate a STOP to abort the current transfer or a
START to restart the transfer.

When a slave is transferring to a master, a NACK answered by the

master means that the master sends a stop bit to terminate the
communication after the current byte is transferred
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Inter-Integrated Circuit (I2C)

• Clock Stretching
- Used by the receiver to control the transfer speed indirectly
- If the slave is too busy to receive another byte, it holds the SCL line low to
force the master to wait
- The master resumes data transfer after the slave releases SCL

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Inter-Integrated Circuit (I2C)

• Simplified diagram of I2C
When the master is transmitting a byte to a slave, the master's
PC hardware automatically sets the TxE (transmitter buffer
empty) flag in the status register if the master has received an
acknowledge pulse (ACK) from the slave
A TxE event can inform software to send the next byte

If the master has received a byte successfully, the master's PC

hardware then automatically sets the RxNE (receiver buffer not
empty) flag in the status register

A RxNE event can inform software to read the received byte

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Inter-Integrated Circuit (I2C)

• Events triggering interrupts (if enabled)
- An I2C master generates an interrupt if a start bit is sent, a slave address is
sent, hardware sets the TxE or RxNE flag, or the transfer of all data bytes
completes
- An I2C slave generates an interrupt if the address received matches its own
address, a stop bit is received, or hardware sets the TxE or RxNE flag

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Inter-Integrated Circuit (I2C)

• Arbitration when multiple Masters are requiring to the I2C bus
- Clock synchronization:
• The SCL interface of all devices performs a logic AND operation. When one
master pulls SCL low, no other masters can pull it high
- Bus arbitration:
• On the SCL rising edge, each master checks whether the SDA voltage level
matches what it has sent
• Whenever a master tries to transmit a high but detects a low on SDA, this
master loses the arbitration
• Each losing master immediately switches to slave receive mode because
the winning master may be addressing it
• A losing master will restart the transfer after it detects a STOP bit

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Inter-Integrated Circuit (I2C)

• Data Frame (7 bits address)

• The slave whose address matches the address sent by the master will answer with
an ACK bit
• After the slave acknowledges the addressing successfully, data transfer takes place
in the direction specified by the R/W bit
• Data are transferred byte by byte
• Each byte is followed by an ACK or NACK bit
• It takes 9 cycles to transfer one byte
• The master completes the communication by sending a STOP bit to the slave
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Inter-Integrated Circuit (I2C)

• Data Frame (10 bits address)

- E.g., writing two bytes to an I2C slave with 10-bit address

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Inter-Integrated Circuit (I2C)

• Data Frame (10 bits address)
- E.g., reading two bytes to an I2C slave with 10-bit address

(1)

• After the master sends out the first byte, all slave devices compare it to their own address. It is possible that
more than one device finds a match between the two leading bits of the 10-bit address. Therefore, multiple
ACK bits might be generated during the A l clock period
• After the master sends out the lower 8 bits of the slave address, at most one device finds an address match,
and thus no multiple ACK bits are generated during the A2 clock period

After sending two address bytes (R/W = 0), the master repeats the start bit and
sends again the first address byte, with R/W being 1 to indicate reading
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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- TC 74 sensor

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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- Configuration register

•The most significant bit of the configuration register sets the

sensor to either the standby state or the normal state
•Bit 6 indicates whether the temperature data is ready or not

•Standby mode: used when temperature acquisition is

suspended. Good to save energy.

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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- Temperature register

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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- Commands

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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- Communication sequence to write a byte to TC74

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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- Communication sequence to write a byte to TC74

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Inter-Integrated Circuit (I2C)

• Interfacing Serial Digital Thermal Sensor
- Communication sequence to read a byte to TC74

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Inter-Integrated Circuit (I2C)

• Polling (transmitting) Hardware automatically sets the TXIS flag after it receives the
acknowledgment bit from the slave, and clears the TXIS flag
when the byte to be transferred has been written to the transmit
data register (TXDR).

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Inter-Integrated Circuit (I2C)

• Polling (transmitting)

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Inter-Integrated Circuit (I2C)

• Polling (receiving) - The target slave responds with an acknowledgment bit (ACK)
and then starts to transfer the data to the master byte by byte
- When the master receives a byte, hardware sets the RXNE
flag.
- Before software can read the receive data register (RXDR),
software must wait until the RXNE flag is set
- Hardware automatically clears the RXNE flag when software
reads RXDR.

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Inter-Integrated Circuit (I2C)

• Polling (receiving)

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Inter-Integrated Circuit (I2C)

• Reading data from the TC74 sensor

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Serial Peripheral Interface (SPI)

• Synchronous
• Simple
• Supports high throughput
• Does not support multiple masters
• Slaves cannot start the communication or control data transfer speed

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Serial Peripheral Interface (SPI)

• Communication process:
- Master pulls down the select line (SS) corresponding to the slave it wishes to communicate
(active-low slave select line)
- Master then generates clock pulses to coordinate the data exchange on the MOSI and MISO
lines
- The selected slave device then listens for the clock and MOSI signals

• Data is sent and received based on the clock provided by the master
• One device writes a bit to the data line at the rising or falling edge of the clock,
the other device then reads the bit at the opposite edge of the same clock period
• Master can change the clock speed by programming the clock prescaler register

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Serial Peripheral Interface (SPI)

• When a bit is shifted out on the MISO line from the slave's data register during a
clock period, a new data bit is shifted into this register from the MOSI line in the same clock
period
- When a slave wants to send data to the master via the MISO line, the slave must wait for the clock signal
- The master must send some dummy data out via the MOSI line to generate the clock signal to initiate the
data transfer
• When one device writes a bit to the data line at the rising or falling edge of the clock, the
other device then reads the bit at the opposite edge of the same clock period
• The data transfer size is usually a byte or halfword (16 bits)

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Serial Peripheral Interface (SPI)

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Serial Peripheral Interface (SPI)

• The most significant bit of both data registers is sent out first

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• https://www.parlezvoustech.com/en/comparaison-protocoles-
communication-i2c-spi-uart/

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