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Dynamic Read Destructive Faults in Embedded-SRAMs: Analysis and March

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 Dynamic Read Destructive Faults in Embedded-SRAMs:
Analysis and March Test Solution
Luigi Dilillo Patrick Girard Serge Pravossoudovitch Arnaud Virazel
Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier – LIRMM
Université de Montpellier II / CNRS
161, rue Ada – 34392 Montpellier Cedex 5, France
Email: <lastname>@lirmm.fr URL: http://www.lirmm.fr/~w3mic

Simone Borri Magali Hage-Hassan

Infineon Technologies France
2600, Route des Crêtes – 06560 Sophia-Antipolis, France
Emails: simone.borri@infineon.com magali.hage@infineon.com
URL: http://www.infineon.com

Abstract: This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are
the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the
study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we
demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line.
This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we
propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect
them. This is obtained by changing its addressing order with the purpose of producing the maximal number of
RES. This modification does not change the complexity of the algorithm and its capability to detect the former
target faults.

Keywords: Memory testing, SRAM core-cell, dynamic faults, resistive-open defects, March test.

Proposed Topic: Memory Test.

Corresponding author
Dr Arnaud VIRAZEL
Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier,
Université Montpellier II / CNRS
161 rue Ada, 34392 Montpellier Cedex 5 FRANCE
Tel.: (+33) 467 41 85 76 Fax: (+33) 467 41 85 00
Email: virazel@lirmm.fr URL: http://www.lirmm.fr/~virazel

Proposed to
th
9 IEEE European Test Symposium
Congress Center, Ajaccio, Corsica, France
May 23-26, 2004

1
 Dynamic Read Destructive Fault in Embedded-SRAMs:
*
Analysis and March Test Solution
Luigi Dilillo Patrick Girard Serge Pravossoudovitch Arnaud Virazel
Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier – LIRMM
Université de Montpellier II / CNRS
161, rue Ada – 34392 Montpellier Cedex 5, France
Email: <lastname>@lirmm.fr
URL: http://www.lirmm.fr/~w3mic

Simone Borri Magali Hage-Hassan

Infineon Technologies France
2600, Route des Crêtes – 06560 Sophia-Antipolis, France
Emails: simone.borri@infineon.com magali.hage@infineon.com
URL: http://www.infineon.com

Memory test solutions are mostly oriented to static fault

Abstract* detection. These faults are sensitized by only one
This paper presents an analysis of dynamic faults in operation. Recent works show that VDSM (Very Deep
core-cell of SRAM memories. These faults are the Sub-Micron) technologies more frequently involve
consequence of resistive-open defects that appear more dynamic faults [2, 3]. They can be sensitized only by
frequently in VDSM technologies. In particular, the study performing more than one operation in sequence and
concentrates on those defects that generate dynamic Read traditional tests are not made to detect them [4].
Destructive Faults, dRDFs. In this paper, we demonstrate Among the known dynamic faults that may affect SRAM
that read or write operations on a cell involve a stress on memories, we concentrate on those that concern the core-
the other cells of the same word line. This stress, called cell. One of these faults is the dynamic Read Destructive
Read Equivalent Stress (RES), has the same effect than a Fault (dRDF) [2]. It has the following behavior: a write
read operation. On this basis, we propose to modify the operation immediately followed by a read operation causes
well known March C-, which does not detect dRDFs, into the flip of the logic value stored in the cell. So, such a fault
a new version able to detect them. This is obtained by requires a specific read/write sequence to be detected.
changing its addressing order with the purpose of Recently, a test solution, referred as March RAW (Read
producing the maximal number of RES. This modification After Write) [5], has been proposed to detect all single-cell
does not change the complexity of the algorithm and its dynamic faults in core-cells. Its complexity is 13N
capability to detect the former target faults. including the initialization. This algorithm detects dRDFs
by March elements that perform a write operation
followed by a read operation, e.g. 1w0r0. It has been
1 Introduction shown in [6] that this test can be improved by applying the
M M
sequence of operations 1w0r0 , where r0 denotes a
Embedded memories will continue to dominate the sequence of M successive r0 operations, e.g. 1w0r0 =
2

System-on-Chip silicon area in the next years. This is 1w0r0r0. In this case, multiple read operations are
confirmed by the SIA Roadmap which forecasts a memory performed after the write operation, allowing a more
density approaching 94% in about ten years [1]. efficient fault detection. However, if a large number of
Consequently, memories will be the main responsible of read operations is needed, the test complexity increases
the overall System-on-Chip yield. It therefore becomes drastically.
evident that the development of efficient test solutions and In this paper we propose a more efficient alternative to
repair schemes for memories are essential. March RAW. Without increasing its complexity, we
improve the standard March C- algorithm (10N
complexity) [7, 8] in order to make it able to detect also
*
This work has been partially funded by the French government dynamic faults in the core-cell. Our modified March C-
under the framework of the MEDEA+ A503 “Associate” detects dRDFs by using a particular addressing sequence.
European program.

2
This modification is allowed by the first of the six Degrees • Temperature: - 40°C, 27°C, 125°C
of Freedom (DOF) [9] of March tests, and does not alter
• Resistance values have been chosen IURP IHZ V
the capability to detect the former target faults.
XS WR VHYHUDO 0 V VLQFH D ODUJH UDQJH RI SRVVLEOH
Multiple read operations after a write operation can be values have been reported [10].
achieved by the March C- (with the address modification)
In the following, the most significant simulation results
for the following reason: during a read or write operation
are presented, with particular emphasis on dynamic fault
the pre-charge circuit is turned off in the selected column;
models. Table 1 shows a summary of the fault models
the others columns have the pre-charge left on.
identified for each injected resistive-open defect,
Consequently, all the cells on the same word line of the
according to the conditions which maximize the fault
selected cell fight against the pre-charge circuit. In this
detection, i.e. the minimum detectable resistance value.
paper we show that this event, that we call Read
The faults have been detected by 1w0r0 or 0w1r1
Equivalent Stress (RES), is equivalent to a read operation
sequences.
for the non-selected cells. In other word, a read or write
operation on a certain cell involves a stress (RES) on the Dfi Process Voltage Temp Min Res Fault
other cells of the same row. This phenomenon can be used corner (V) (°C) :
(k ) Model
for dynamic fault sensitization. 1 Fast 1.6 -40 ∼25 TF
The rest of the paper is organized as follows. Section 2 2 Fast 1.6 - ∼8 RDF
gives an overview of our study presented in [6] with the DRDF
defect insertion in the core-cell. Section 3 provides 3 Fast 1.6 125 ∼3 RDF
explanations and electrical simulations of the RES. In DRDF
Section 4, a March test solution is presented. Concluding 4 Fast 1.6 125 ∼130 dRDF
remarks and future works are given in Section 5. 5 Fast 1.6 -40 100/140 IRF/TF
6 Fast 1.6 125 ∼2 M TF
2 Dynamic faults in the core-cell
Table 1: Summary of worst-case PVT corners
In this section we synthesize the main results of our for the defects of Figure 1 and corresponding minimum
previous study in core-cell faulty behavior [6]. This study detected resistance and fault models [6]
was oriented to the characterization of some faults induced
Definitions of the fault models reported in Table 1 are
by the injection of resistive-open defects in the core-cell of
the following ones:
an SRAM memory core-cell. Figure 1 depicts the scheme
of a standard 6-transitors cell where six different resistive- • Transition Fault (TF): A cell is said to have a TF if
open defects have been placed. The defects are not it fails to undergo a transition (0 → 1 or 1 → 0)
injected into all possible locations due to the symmetry of when it is written.
the structure.
• Read Destructive Fault (RDF) [11]: A cell is said to
BL BLB have an RDF if a read operation performed on the
Df5
WLS
Vdd cell changes the data in the cell and returns an
Df4 incorrect value on the output.
Mtp2 • dynamic Read Destructive Fault (dRDF) [2, 5]: A
Df2
cell is said to have an dRDF if a write operation
SB immediately followed by a read operation
Mtn2 Df1
Mtn3 Vdd Mtn4 performed on the cell changes the logic state of this
Df3
cell and returns an incorrect value on the output.
Mtp1
S Df6 • Deceptive Read Destructive Fault (DRDF) [11]: A
Mtn1
cell is said to have a DRDF if a read operation
performed on the cell returns the correct logic
value, and it changes the contents of the cell.
Figure 1: Resistive-open defects injected
into the memory core-cell • Incorrect Read Fault (IRF): A cell is said to have an
IRF if a read operation performed on the cell
The whole operating environment range has been returns an incorrect logic value, and the correct
selected in order to maximize the fault detection value is still stored in the cell.
probability. Hence simulations have been performed by
the variation of the following parameters: On the bases of these results, a dynamic Read
Destructive Fault (dRDF) occurs in presence of Df4. This
• Process corner: slow, typical, fast fault is detectable by a read after write operation.
• Supply voltage: 1.35V, 1.5V, 1.6V However, in case of a little defect size, multiple read
operations are needed. This statement is confirmed by the

3
waveforms presented in Figure 2 which shows that a same word line. Moreover, we demonstrate that RESs are
sequence of five r0 operations, is needed to detect the fault more effective to sensitize dRDFs than read operations.
carried by D0 UHVLVWDQFHGHIHFW For this purpose, it is useful to remember that when a
cell is selected for a read or write operation the pre-charge
circuit is normally turned off in its bit line. For the bit lines
that are not involved in the operation, the pre-charge
circuit is commonly left on. With the pre-charge active and
the word line being high on the unselected columns, the
cells fight against the pre-charge circuit. A consequent
deduction is that the stress produced by a read operation
on a cell is equivalent to the stress caused by a read or
write operation performed on whatever cell on the same
word line. It is also possible that in the latter case the
stress is larger. In fact, during a read action the
w0 r0 r0 r0 r0 r0
perturbation of the cell is produced by the charge stored
Figure 2: A destructive read occurring after the 5
th previously on its two bit lines, while in the other case the
consecutive r0 operation cell is stressed by the same bit line charge, but with the
(typical process, T=125°C, V=1.6V, Tcyc QV5 0 pre-charge circuit still on. In order to simplify what
exposed above we produce the example referred to the
In general, the dependence of dRDF has been studied in scheme in Figure 4.
relation to the cycle time and the defect size. The results
BL0 BLB0 BL1 BLB1 BL2 BLB2 BL3 BLB3 BL4 BLB4 BL5 BLB5
are presented in the graph of Figure 3 where each point
WLi-1
corresponds to a determined couple (cycle time, defect
size) and is placed in a certain area corresponding to a
M
sensitization sequence like 1w0(r0) , where M = 1 to 5. WLi

9
w-r Ci,0 Ci,1 Ci,2 Ci,3 Ci,4 Ci,5
8 WLi+1
w-r-r
Defect size (MOhms)

7
w-r-r-r
6
w-r-r-r-r
5
w-r-r-r-r-r
4 No Fault Figure 4: A portion of an SRAM block
3
2
This scheme depicts a section of an SRAM block, and in
1
particular in the middle there are the first six cells of the
0
word line WLi. We assume that on WLi the first cell on the
1,8 2 2,5 3 3,5 4 6 8 10 left Ci,0 is affected by a resistive-open defect in the pull-up
Cycle tim e (ns )
transistor of one of the two inverter (as Df4 in Figure 1).
This defect may cause a dRDF. This fault is detectable
Figure 3: Fault detection as a function of the cycle time and when, immediately after a write data on cell Ci,0, one or
defect size (typical process, T=125°C, V=1.6V) multiple read operations are performed on the same cell.
An equivalent faulty behavior can also occur when the
It should be observed that the minimal detected
write data in cell Ci,0 is followed by read or write
resistance value depends on the cycle time. The fault
operations on the other cells of the same world line. This is
detection is two times more effective when we pass from
5 possible because, if for example cell Ci,1 is selected, the
1w0r0 to 1w0r0 .
pass transistors (Mnt3 and Mnt4 in Figure 1) of all the
cells on the same word line, in particular the faulty cell
3 Read Equivalent Stress Ci,0, are saturated. So, Ci,0 fights against the pre-charge
In the previous section it has been shown that a dRDF circuit that is in on state as for all the non-selected
can be the consequence of resistive-open defects in the columns. Consequently, the faulty cell Ci,0 undergoes a
core cell of SRAMs. In particular it has been empathized stress (RES) similar to a read operation.
that in presence of the resistive-open defect Df4 depicted In order to give a formal confirmation to the previous
in Figure 1, the action of single or multiple read assumptions and assertions, electrical simulations have
immediately after a write operation may cause the been performed on Infineon 0.13µm embedded-SRAM
inversion of the value stored in the cell. In this section, we family with the Infineon internal SPICE-like simulator. It
show that a cell can undergo a stress equivalent to a read has been considered a reference 8kx32 memory, organized
operation (Read Equivalent Stress, RES) when a as an array of 512 word lines x 512 bit lines. The cell array
read/write operation is performed on other cells of the of this memory is split in 128 blocks. When a word line is

4
selected all the 512 cells on this word line are connected to (WLEN0, WLEN1 and BLEN0). The voltage values of S
respective bit lines. The bit line selection is performed by and SB nodes (see core cell presented in Figure 1) are
a pre-decoder, that selects a column for each block (for reported in Figure 6.b, for the comparison of case a and b
example the first column of each block), followed by (b1 and b2) and in Figure 6.c for a comparison between
different lines of multiplexers. cases a, b1 and c. These waveforms show that after a w0
In Figure 5 there is an example of a two-block SRAM operation the fault free inverter of the cell has its output
with the column decoding made by a pre-decoder and (node S) normally switched to ‘0’ logic, that is an effective
multiplexers. Consequently, when a read operation is done electrical 0V. The other inverter has its output switched to
on a cell, it is actually performed on all the correspondent ‘1’ logic, that does not correspond to an exact Vdd value,
cells for each block, and after, there is a further selection due to the delay effect involved by defect Df4.
made by multiplexers. Thus in the considered Infineon
architecture, when a cell is selected to be read or written,
512 cells are contemporarily selected because they are on
the same word line. For 128 of them the pre-charge circuit
(a)
is off, because they are in the same position of the selected
cell in the different blocks. In term of stress for each read
or write operation there are128 cells with a actual read b1

stress, because they are selected by word line and bit lines, b2
SB
and 384 (= 512-128) cells that undergo a RES, because
they are selected only by the world line signal.
a

(b)

w0 r0 (case a) r0 (case a)
RES (case b1 and b2) RES (case b1 and b2)

MUX 4:1 MUX 4:1 b1

c
SA Sense Amplifier SA SB

a
MUX 2:1
Data output S

Figure 5: Scheme of a two-block SRAM memory

(c)
The simulations have been performed to estimate and
confront the stresses produced in the following situations: w0 r0 (case a)
RES (case b1 and c)
r0 (case a)
RES (case b1 and c)
a. On the faulty cell a w0 operation is performed,
immediately followed by one r0 operation.
Figure 6: Waveforms of simulations
b. On the faulty cell a w0 operation is done,
immediately followed by read (b1) or write (b2) In all cases a, b and c, the disturb operations performed
operations on the cells placed on the same immediately after the w0 made on the same cell or in other
word line. cells of the same word line, produce an abnormal swap of
c. On the faulty cell a w0 operation is performed, the faulty cell after two cycles. This is a confirmation of
immediately followed by read or write the assumptions proposed at the beginning of this section,
operations on the cells on the same word line, i.e. the effects produced by the read equivalent stress in
but placed in other blocks in the same position term of sensitization of dRDF are very similar to actual
of the faulty cell (highlighted cells in Figure 5). read stresses. In fact, in both graphs (Figure 6.a and 6.b)
the waveforms show different cases of RES (b1, b2 and c)
The waveforms in Figure 6 refer to the electrical which are very similar to a read after write (case a).
simulations made with the previous conditions in the case
of a faulty cell, where the defect Df4 is present and has a Considering Figure 6.b, it can also be observed that in
size of 1.4 MΩ. The waveforms in Figure 6.a represent the case of read operation the word line enable signal is on for
control signals; CLK, RWB which is the read/write a period a little bit longer than for the write operation. This
selection, and the word line and bit line enable signals involves that b1 produces a more prolonged stress. In fact,
the cell swaps before.

5
 Now we evaluate the RES in terms of sensitization 4 March test solutions for dRDF testing
performance. For this purpose, parametrical simulations
have been made with different cycle time and with a In this section we use the results presented above in
reasonable resistive range for the size of the resistive-open order to produce an efficient test for dRDF detection.
defect Df4 on the Infineon SRAM memory structure. The Among the various types of algorithm we choose March
results, summarized on the graph of Figure 7 are referred test that allows to reach a good effectiveness among with
only to case b1. These results are clearly very similar to of its small complexity. For this purpose, our March test
those shown in Figure 3 that refer to the read after write has to have some requirements.
method. The analysis of the two graphs of Figure 3 and i. It is necessary that the read/write operations are
Figure 7 also confirms that the sensitization effect of the performed with a particular addressing order with
RESs is higher than that produced by read operations on the purpose to execute the March elements on the
the faulty cell. memory array by acting on word line after word
7 line. This is necessary because the RESs are
w-RES
produced only by operating on the cells of the same
6
2 word line. For example, let us consider again the
w-RES
Defect size (MOhms)

5 w-RES3
Infineon 0.13µm embedded-SRAM architecture.
w-RES4
The read and write operations of the March
4
w-RES
5 elements have to be operated firstly on all the 512
3 No Fault cells of the first word line, then on the 512 cells of
the second word line, and so on.
2
ii. The elements of our March test have to include w0
1 operations, necessary for sensitization, and r0
necessary for observation.
0
1,8 2 2,5 3 3,5 4 6 8 10
iii. Additional elements with w1 and r1 are needed in
Cycle tim e (ns ) order to detect similar faults generated by resistive-
open defects placed symmetrically in reference
Figure 7: Fault detection as a function of the cycle time, with Df4 (see Figure 1).
defect size and RES (typical process, T=125°C, V=1.6V) iv. All the elements, in particular the sensitization
ones, need to be performed in ⇑ and ⇓ sequence.
In order to highlight the higher efficacy of RESs for
sensitization of dRDF, we propose in Table 2 the results of The last statement is based on some considerations. For
read after write operations and RESs. example we still use the same Infineon SRAM
th
architecture. If the faulty cell is Ci 0, the first cell of the i
cycle time
(ns)
1.8 2 2.5 3 3.5 4 6 8 10 word line, an element like ⇑w0 operates a w0 on this cell
w-r 1.7 2 2 3 3.5 4 5.5 8 9.5 and is immediately followed by w0 operations performed
Minimal resistance size, MOhm

w-RES 1.4 1.4 2 2 2.3 3 4.5 6 7 on the following 511 cells of the same word line. These
w-r2 1.2 1.2 1.7 2 2.5 3 4 6 7 w0 operations imply 511 RESs on the faulty cell. If the
w-RES2 0.95 1.1 1.4 1.7 2 2.2 3.5 4.7 5.5 faulty cell is the second one, Ci 1 , the same March element
w-r3 0.95 1.1 1.4 1.7 2 2.5 3.5 5 6 ⇑w0 involves 510 RESs on the faulty cell. In case the
w-RES3 0.85 0.95 1.3 1.55 1.8 2.1 3.2 4.3 5
defective cell is the last of its word line the element ⇑w0
w-r4
involves any RES on it. The introduction of ⇓ elements
0.9 1 1.3 1.55 1.9 2.2 3.3 4.4 5.5
w-RES4 0.8 0.9 1.22 1.5 1.75 2 3 3.5 4.8
w-r5 0.85 1 1.25 1.5 1.9 2.2 3.3 4.3 5.5
allows that the sensitization phase is performed with the
w-RES5 0.8 0.9 1.22 1.5 1.75 2 3 3.5 4.8
opposite addressing sense of the word line. In these
conditions the cells that endure the maximum number of
Table 2: Comparison between read after write and RES RESs are those placed in the extremes of the word line,
while those placed in the middle of the word line undergo
In Table 2, the values represent the size of defects that
the smallest number of RESs, i.e. 512/2=256 of RESs. In
lead to dRDFs. These values are the minimal ones
M
sensitized by read after write operations (w-r ) or RESs general if nb_cell is the number of cells of each word line
M
(w-RES ) for different cycle time. For example, for the and nb_op the number of operations (read/write) of the
cycle time March element (⇑w0 → nb_op=1; ⇑r1w0 → nb_op=2),
3
4 ns, the sequence w-r sensitizes a dRDF, consequent to a the maximum number of RESs that a cell undergoes is:
minimal defect size of 2.5 MΩ, while in same conditions, RESmax = (nb_cell - 1) x nb_op
3
w-RES allows to sensitize dRDF involved by a 2.1 MΩ and the minimum one is:
defect. In other words, RES is more effective than read
RESmin = (nb_cell x nb_op) / 2
after write operation because it can sensitize dRDFs due to
a smaller resistive defect. This is illustrated in Figure 9, where the color of cells is
darker if they endure a higher number of RESs.

6
 number of read operations increasing dramatically its
complexity.

5 Concluding remarks and future works

The present study has focused on dynamic faults that
RESmax RESmin RESmax
may occur in core-cells of SRAM memories. In particular,
we have focused our attention on dynamic Read
Figure 9: Distribution of RESs on a word line Destructive Faults.
with the modified March C- We have shown that a cell undergoes a stress equivalent
Now we propose a modification of known March tests, to a read operation, when a read/write operation is
which have the characteristics exposed above, with the performed on a cell of the same word line. We have called
objective to detect dRDFs. For this purpose, we consider this phenomenon Read Equivalent Stress (RES), and
the well known March C-. This is a 10N linear test, which shown that they are more efficient than read after write.
is effective to detect stuck-at, transition and 2-coupling On these bases, we have modified the March C- to make it
faults and that normally cover 0% of dRDFs [5]. March C- able to detect dRDFs, without changing its complexity and
has the structure shown in Figure 8. capabilities.

{  (w0 ) ⇑ (r0, w1) ⇑ (r1, w0 ) ⇓ (r0, w1) ⇓ (r1, w0 )  (r0) } We intend to prosecute this study by analyzing the
capability of RES to sensitize all the other dynamic faults
M0 M1 M2 M3 M4 M5 in core cells.

Figure 8: March C- structure References

We can observe that the first five elements (M0 up to M4) [1] Semiconductor Industry Association (SIA), “International
could be effective for dRDF sensitization because they Technology Roadmap for Semiconductors (ITRS)”, 2003
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