| RISC and CISC
Reduced Instruction Set Architecture (RISC) –
The main idea behind this is to make hardware simpler by using an instruction set composed of a few
basic steps for loading, evaluating, and storing operations just like a load command will load data, a
store command will store the data.
Complex Instruction Set Architecture (CISC) –
The main idea is that a single instruction will do all loading, evaluating, and storing operations just like
a multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s complex.
Both approaches try to increase the CPU performance
RISC: Reduce the cycles per instruction at the cost of the number of instructions per program.
CISC: The CISC approach attempts to minimize the number of instructions per program but at the
cost of an increase in the number of cycles per instruction.
Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction comes undersize of one word.
3. Instruction takes a single clock cycle to get executed.
4. More general-purpose registers.
5. Simple Addressing Modes.
6. Fewer Data types.
7. A pipeline can be achieved.
Characteristic of CISC –
1. Complex instruction, hence complex instruction decoding.
2. Instructions are larger than one-word size.
3. Instruction may take more than a single clock cycle to get executed.
4. Less number of general-purpose registers as operations get performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.
Difference –
RISC CISC
Focus on software Focus on hardware
Uses both hardwired and microprogrammed
Uses only Hardwired control unit control unit
Transistors are used for storing complex
Transistors are used for more registers Instructions
Fixed sized instructions Variable sized instructions
Can perform only Register to Register Can perform REG to REG or REG to MEM or
Arithmetic operations MEM to MEM
Requires more number of registers Requires less number of registers
RISC CISC
Code size is large Code size is small
An instruction executed in a single clock cycle Instruction takes more than one clock cycle
Instructions are larger than the size of one
An instruction fit in one word word
Addressing modes of 8086
The way for which an operand is specified for an instruction in the accumulator, in a general
purpose register or in memory location, is called addressing mode.
The 8086 microprocessors have 8 addressing modes. Two addressing modes have been
provided for instructions which operate on register or immediate data.
These two addressing modes are:
Register Addressing: In register addressing, the operand is placed in one of the 16-bit or 8-bit
general purpose registers.
Example
o MOV AX, CX
o ADD AL, BL
o ADD CX, DX
Immediate Addressing: In immediate addressing, the operand is specified in the instruction
itself.
Example
o MOV AL, 35H
o MOV BX, 0301H
o MOV [0401], 3598H
o ADD AX, 4836H
Direct Addressing: In direct addressing mode, the operand?s offset is given in the instruction as
an 8-bit or 16-bit displacement element.
Example
o ADD AL, [0301]
The instruction adds the content of the offset address 0301 to AL. the operand is placed at the
given offset (0301) within the data segment DS.
Register Indirect Addressing: The operand's offset is placed in any one of the registers BX, BP,
SI or DI as specified in the instruction.
Example
o MOV AX, [BX]
It moves the contents of memory locations addressed by the register BX to the register AX.
Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit displacement and the
contents of the base register BX or BP. BX is used as base register for data segment, and the BP
is used as a base register for stack segment.
Effective address (Offset) = [BX + 8-bit or 16-bit displacement].
Example
o MOV AL, [BX+05]; an example of 8-bit displacement.
o MOV AL, [BX + 1346H]; example of 16-bit displacement.
Indexed Addressing: The offset of an operand is the sum of the content of an index register SI
or DI and an 8-bit or 16-bit displacement.
Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]
Example
o MOV AX, [SI + 05]; 8-bit displacement.
o MOV AX, [SI + 1528H]; 16-bit displacement.
Based Indexed Addressing: The offset of operand is the sum of the content of a base register
BX or BP and an index register SI or DI.
Effective Address (Offset) = [BX or BP] + [SI or DI]
Here, BX is used for a base register for data segment, and BP is used as a base register for stack
segment.
Example
o ADD AX, [BX + SI]
o MOV CX, [BX + SI]
Based Indexed with Displacement: In this mode of addressing, the operand's offset is given by:
Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement
Example
o MOV AX, [BX + SI + 05]; 8-bit displacement
o MOV AX, [BX + SI + 1235H]; 16-bit displacement
