COURSE PACK

SCHEME
The scheme is an overview of work-integrated learning opportunities and gets students out into
the real world. This will give what a course entails.

Course Title Digital Computer Organization Course Type Theory

Course Code E1PA107T Class MCA
Activity Credits Credit Hours Total Number of Assessment in
Classes per Semester Weightage
Lecture 3 3
Instruction Tutorial

Practical
Tutorial
- -

Theory
delivery

study
Self-

SEE
Practical

CIE
- -
Self-study - -
Total 3 3 100 50% 50%
Course Lead Prof. Uday Kumar Singh Course Prof. Mukesh Mishra
Coordinator:
Names Theory Practical
Course Prof. Uday Kumar Singh NA
Instructors Prof. Maneesh Upadhyay
Prof. Mukesh Mishra

COURSE OVERVIEW
Computer Organization and Architecture course is designed to disseminate the knowledge of
Computer Organization and Architecture. It will comprehensively cover bus organization, stack
organization, register organization, addressing modes, look ahead carry adder, multiplication and
division algorithms, array multiplier, pipelining, Memory management, Input/output interface,
direct memory access, synchronous and asynchronous communication.

PREREQUISITE COURSE

PREREQUISITE COURSE YES

REQUIRED
If, yes please fill in the Details Prerequisite course code Prerequisite course
name
E1PA102T Introduction to Digital System

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COURSE OBJECTIVE
 To understand the state-of-the-art design of computer architectures in terms of micro-operations,
micro-programmed control unit, memory and I/O organization of a typical computer system.
 To analyze the system performance.
 To apply the knowledge on designing hardware of the computers.
 To learn & use the new technologies in computers

COURSE OUTCOMES (COs)

After the completion of the course, the student will be able to:

CO E1PA102T.1 Explain bus architecture of a computer and the function of the instruction
execution cycle, RTL interpretation of instructions, addressing modes,
instruction set, control unit
CO E1PA102T.2 Apply various arithmetic operations on fixed point representation of binary
numbers and design the ALU.
CO E1PA102T.3
Design a memory module and analyze its operation by interfacing with the CPU
and understand the different ways of communicating with I/O devices

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 BLOOM’S LEVEL OF THE COURSE OUTCOMES

Bloom's taxonomy is a set of hierarchical models used for the classification of educational learning objectives
into levels of complexity and specificity. The learning domains are cognitive, affective, and psychomotor.

THEORY

Remember Understand Apply Analyze Evaluate Create

CO No.
KL1 KL2 KL3 KL4 KL5 KL6
CO E1PA102T.1 √
CO E1PA102T.2 √
CO E1PA102T.3 √ √

PROGRAM OUTCOMES (POs):

PO1: Computational Knowledge: Apply knowledge of computing fundamentals, computing specialization,
mathematics, and domain knowledge appropriate for the computing specialization to the abstraction and
conceptualization of computing models from defined problems and requirements.

PO2: Problem Analysis: Identify, formulate, research literature, and solve complex computing problems reaching
substantiated conclusions using fundamental principles of mathematics, computing sciences, and relevant domain
disciplines.

PO3: Design /Development of Solutions: Design and evaluate solutions for complex computing problems, and
design and evaluate systems, components, or processes that meet specified needs with appropriate consideration for
public health and safety, cultural, societal, and environmental considerations.

PO4: Conduct investigations of complex Computing problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid
conclusions.

PO5: Modern Tool Usage: Create, select, adapt and apply appropriate techniques, resources, and modern computing
tools to complex computing activities, with an understanding of the limitations.

PO6: Professional Ethics: Understand and commit to professional ethics and cyber regulations, responsibilities, and
norms of professional computing practices.

PO7: Life-long Learning: Recognize the need, and have the ability, to engage in independent learning for continual
development as a computing professional.

PO8: Project management and finance: Demonstrate knowledge and understanding of the computing and
management principles and apply these to one’s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.

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 PO9: Communication Efficacy: Communicate effectively with the computing community, and with society at large,
about complex computing activities by being able to comprehend and write effective reports, design documentation,
make effective presentations, and give and understand clear instructions.

PO10: Societal and Environmental Concern: Understand and assess societal, environmental, health, safety, legal, and
cultural issues within local and global contexts, and the consequential responsibilities relevant to professional
computing practices.

PO11: Individual and Team Work: Function effectively as an individual and as a member or leader in diverse teams
and in multidisciplinary environments.

PO12: Innovation and Entrepreneurship: Identify a timely opportunity and using innovation to pursue that
opportunity to create value and wealth for the betterment of the individual and society at large.

Program Specific Outcomes (PSO’s)

PSO1: Have the ability to work with contemporary technologies in computing requisite toIndustry 4.0 developing and
implementing solutions to real life problems.
PSO2: Demonstrate application development skills learned through technical training and projects to solve real world
problems.

COURSE ARTICULATION MATRIX

The Course articulation matrix indicates the correlation between Course Outcomes and Program Outcomes and
their expected strength of mapping in three levels (low, medium, and high).

COs/

PSO1

PSO2
PO10

PO11

PO12
PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9

POs
2 1
E1PA102T.1 2 2 1
2 1
1 2
E1PA102T.2 2 2- 2
1 2
2
E1PA102T.3 2 2 2
1 2 2 1

Note: 1-Low, 2-Medium, 3-High

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COURSE ASSESSMENT

The course assessment patterns are the assessment tools used both informative and summative examinations.

* Assignment, Quiz, Class test, SWAYAM/NPTEL/MOOCs and etc.

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 COURSE CONTENTTHEORY

Content
Computing Fundamentals:Logic Gates, Boolean Algebra, K-Maps, Maps Simplification, Combinational circuit
Design – Half adder, full adders, Decoders, Encoder, Flip-Flops, Registers, shift registers, Types of Registers,
Register Transfer and Micro operations, instruction codes and formats.

Basic Computer Organization and Arithmetic: Functional units of digital system and their interconnections,
buses, common bus system, bus architecture, types of buses and bus arbitration. Register, bus and memory transfer.
Processor organization: general registers organization, stack organization and addressing modes, Arithmetic
Operations: Addition and Subtraction, Multiplication, Booth’s algorithm and array multiplier

Control Unit: Instruction types, formats, instruction cycles and sub cycles (fetch and execute etc), micro-operations,
execution of a complete instruction. Introduction to Assembly Language, Program Control, Reduced Instruction Set
Computer, Pipelining, Parallel Processing, Hardwired and Microprogrammed control unit.

Input / Output: Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of interrupts and
exceptions. Modes of Data Transfer: Programmed I/O, interrupt initiated I/O and Direct Memory Access.. Serial
Communication: Synchronous & asynchronous communication.

Memory:Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D memory organization. ROM
memories. Cache memories: concept, design issues & performance, address mapping and replacement Auxiliary
memories: magnetic disk, magnetic tape and optical disks Virtual memory: concept implementation.

LESSON PLAN FOR THEORY COURSES (THEORY AND TUTORIAL CLASSES)

FOR THEORY 15 weeks * 3 Hours = 45 Classes (1credit = 1 Lecture Hour)

L. No T/L Topics Skills Competency

1 L Computing Fundamentals: Logic Gates,
Boolean Algebra
2 L K-Maps, Maps Simplification
To understand about
the functional unit,
3 L Combinational circuit Design – Half adder, interconnections of
full adders, buses, data transfer Apply the arithmetic
4 L Decoders, Encoder through bus. operations on
hardware and
5 L Flip-Flops, Registers Also, to understand interconnect the
about the Registers, components through

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6 L Types of Registers, Register Transfer and system bus.
Micro operation

7 L instruction codes and formats

8 L Basic Computer Organization and

Arithmetic:Functional units of digital
system and their interconnections
9 L buses, common bus system, ,

10 L types of buses and bus arbitration

11 L
To know about the
bus and memory transfer. Processor organization:
addition, subtraction,
general registers organization
multiplication,
12 L Register, bus and memory transfer
division operations
13 L Processor organization: general registers and also know about
organization, stack organization and addressing the representation of
modes floating-point
14 L Arithmetic Operations: Addition and numbers.
Subtraction,
15 L Booth’s algorithm and array multiplier And to understand
about stack
16 L Bus architecture organization and
Addressing Modes

17 L Control Unit: Instruction types, formats Analyze the

To understand about performance of
18 L Instruction cycles and sub cycles (fetch and
the control unit, pipeline and compare
execute etc) Hardwired and
microprogrammed
19 L Micro-operations, execution of a complete control unit and Microprogrammed
instruction. Control Unit
Parallel Processing.
20 L Introduction to Assembly Language,
Program Control
21 L Reduced Instruction Set Computer
22 L Parallel Processing
23 L Pipelining
24 L Hardwired & Microprogrammed control
unit.

25 L Input / Output: Peripheral devices, I/O Understand the I/O

interface, I/O ports transfer and memory
To understand the basics connections and find the
26 L Interrupts: interrupt hardware of I/O interface and their performance of memory
27 L types of interrupts and exceptions working also modes of units
data transfer.
28 L Modes of Data Transfer: Programmed I/O
29 L Interrupt initiated I/O

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30 L Direct Memory Access
31 L Serial Communication: Synchronous &
asynchronous communication
32 L Memory: Basic concept and hierarchy,
semiconductor RAM memories.

33 L 2D & 2 1/2D memory organization To know the inner part of

34 L
the memory. How the
ROM memories. Cache memories: concept
mapping is done in Cache
and design issues & performance,
Memory. Concept of
35 L Address mapping-Direct Addressing
Virtual Memory and Page
36 L Address mapping- Associative replacement in Virtual
Memory,
37 L Address mapping – Set Associative
38 L Auxiliary memories: magnetic disk,
magnetic tape and optical disks
39 L Virtual memory: concept implementation,
Page Replacement Policies
40 L Conclusion and problem discussion
41 L Advanced architecture topic
42 L Advanced architecture topic
43 L Advanced architecture topic
44 L Advanced architecture topic
45 L Advanced architecture topic

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BIBLIOGRAPHY

TextBook

1. Computer System Architecture - M. Mano

2. Carl Hamacher, ZvonkoVranesic, SafwatZaky Computer Organization, McGraw-Hill, Fifth Edition, Reprint 2012
3. William Stallings, Computer Organization and Architecture-Designing for Performance, Pearson Education, Seventh edition,
2006
Reference Books:

1. Hayes, John P. Computer architecture and organization. McGraw-Hill, Inc., 2002.

(https://eresources.nlb.gov.sg/printheritage/detail/113de262-0f99-43a3-a14d-fa67771619f6.aspx)
2. Heuring, Vincent P., Harry Frederick Jordan, and Miles Murdocca. Computer systems design and architecture. Addison-
Wesley, 1997. (https://dl.acm.org/doi/book/10.5555/996242)
3. Kai Hwang & Naresh Jotwani - Advanced Computer Architecture: Parallelism, Scalability, Programmability, Tata
McGraw Hill,2003 (https://www.expresslibrary.mheducation.com/product/advanced-computer-architecture-parallelism-
scalability-programmability)

SWAYAM/NPTEL/MOOCs Certification

https://www.coursera.org/learn/comparch

https://nptel.ac.in/courses/106105163

https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/

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PROBLEM-BASED LEARNING

Exercises in Problem-based Learning (Assignments)(Min 45 Problems*)

SNo Problem KL
1. Explain the primary function of a CPU in a computer system? 2

2. Describe four basic types of data storage in a computer system? 2

3. List the main components of a von Neumann architecture. 2
4. How to define the term "clock cycle" in computer architecture 2
5. Explain purpose of a cache memory in a CPU? 2
6. Explain the concept of pipelining in CPU architecture 2
7. Describe the difference between RISC and CISC processor architectures. 2
8. How does virtual memory work, and why is it important in modern computer architecture? 2
9. Evaluate the advantages and disadvantages of using a Harvard architecture vs. a von 2
Neumann architecture in embedded systems
10. Design a block diagram of a simple computer system, indicating the connections and flow 2
of data between components
11. Compare and contrast the performance implications of using a single-core CPU vs. a 2
multi-core CPU in a given computing task
12. Create a basic microarchitecture design for a simple CPU, including registers and control 2
unit.
13. Describe the role of the Arithmetic Logic Unit (ALU) in a CPU and how it performs 2
arithmetic and logical operations.
14. What is the purpose of the system bus in a computer architecture, and how does it 2
facilitate communication between components?
15. Describe the difference between Reduced Instruction Set Computing (RISC) and Complex 2
Instruction Set Computing (CISC) architectures, and provide examples of each
16. How does virtual memory work, and what are the benefits of using it in modern computer 2
systems?
17. Explain the concept of branch prediction in processors and how it helps in mitigating 2
branch instruction delays.
18. What is the role of the memory management unit (MMU) in virtual memory systems, and 2
how does it translate virtual addresses to physical addresses?
19. Explain the principles behind instruction-level parallelism (ILP) and how it is achieved in 2
modern processors
20. Define the concept of cache memory and its role in speeding up memory access. 2
21. How does pipelining improve the execution time of instructions in a processor, and what 2
are the potential drawbacks?
22. Given a specific instruction set architecture (ISA), design a program in assembly language 3
that performs a specific computational task, such as matrix multiplication or sorting
23. Develop a block diagram or schematic representation of a simple computer system, 3
including key components like the CPU, memory, I/O devices, and buses, and explain
how data flows between them during program execution
24. Design a multi-core processor architecture and describe how it would handle parallel 3

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 processing tasks, considering issues like thread synchronization and cache coherence
25. Create a memory hierarchy design for a computer system, specifying the size and 3
organization of cache levels, main memory, and secondary storage, and justify your design
choices.
26. Develop a pipeline diagram for a simplified CPU architecture and illustrate how different 3
stages of the pipeline process instructions
27. Design a memory management scheme for a virtual memory system, including page 3
replacement policies and address translation mechanisms, and simulate its performance for
various workloads.
28. Given a set of performance metrics and constraints, select and configure appropriate cache 3
replacement policies for a specific microprocessor design.
29. Propose a customized instruction set extension for a general-purpose CPU to accelerate a 3
particular type of computation, such as floating-point operations or encryption algorithms.
30. Develop a pipelined processor design for a specific set of instructions and pipeline stages, 3
and calculate the speedup achieved compared to a non-pipelined processor.
31. Create a detailed plan for upgrading an existing computer system, specifying the 3
components to be upgraded, the expected performance improvements, and the associated
costs.
32. Configure a computer system with a memory hierarchy to meet specific real-world 3
application requirements, such as real-time gaming or scientific simulations, and optimize
the design for performance.
33. Examine the differences in instruction-level parallelism (ILP) between superscalar and 4
VLIW processor architectures.
34. Compare the trade-offs between using static RAM (SRAM) and dynamic RAM (DRAM) 4
in computer memory subsystems.
35. Investigate the impact of branch prediction strategies on CPU performance and discuss 4
their relevance
36. Evaluate the role of cache memory in enhancing the performance of a computer system, 4
and discuss the trade-offs involved in cache design, such as size vs. associativity.
37. Evaluate the impact of pipelining hazards (e.g., data hazards, control hazards) on the 4
performance of a pipelined processor, and propose solutions to mitigate these hazards
38. Analyze the trade-offs between using a single-core CPU with high clock speed and a 4
multi-core CPU with lower clock speed in terms of power consumption and performance
for a given workload.
39. Investigate the impact of memory hierarchy design choices (e.g., inclusion/exclusion 4
policies, write policies) on cache coherence and memory consistency in multiprocessor
systems.
40. Evaluate the performance and energy efficiency trade-offs of using different memory 4
technologies (e.g., DRAM, SRAM, NVRAM) in computer memory subsystems
41. Analyze the design principles behind instruction set architectures (ISAs) and discuss how 4
different ISAs influence the development of compilers and software for a specific
architecture.
42. Compare and contrast the memory consistency models used in shared-memory 4
multiprocessor systems, and explain the implications of choosing one model over another
43. Analyze the advantages and disadvantages of different interconnection topologies (e.g., 4
bus, crossbar, mesh) in multiprocessor systems, considering scalability and fault tolerance
44. Develop a branch prediction algorithm for a processor, analyze its performance using 4
benchmark programs, and fine-tune the algorithm to improve accuracy
45. Design a custom instruction scheduling algorithm for a superscalar processor to optimize 4
the execution of a specific set of instructions.

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