This document outlines Lab 2 for the EE-221 Digital Logic Design course, focusing on an introduction to Verilog and hardware implementation of basic logic circuits. It details objectives, lab instructions, and tasks, including pre-lab preparation, modeling and simulating basic gates, and deriving algebraic expressions. Students are required to submit lab reports and participate in a viva session for grading.
This document outlines Lab 2 for the EE-221 Digital Logic Design course, focusing on an introduction to Verilog and hardware implementation of basic logic circuits. It details objectives, lab instructions, and tasks, including pre-lab preparation, modeling and simulating basic gates, and deriving algebraic expressions. Students are required to submit lab reports and participate in a viva session for grading.
This document outlines Lab 2 for the EE-221 Digital Logic Design course, focusing on an introduction to Verilog and hardware implementation of basic logic circuits. It details objectives, lab instructions, and tasks, including pre-lab preparation, modeling and simulating basic gates, and deriving algebraic expressions. Students are required to submit lab reports and participate in a viva session for grading.
This document outlines Lab 2 for the EE-221 Digital Logic Design course, focusing on an introduction to Verilog and hardware implementation of basic logic circuits. It details objectives, lab instructions, and tasks, including pre-lab preparation, modeling and simulating basic gates, and deriving algebraic expressions. Students are required to submit lab reports and participate in a viva session for grading.
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total Performance of data in Tool Usage Safety and Team marks Lab Report Work Obtained
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
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Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware Implementation of Basic Logic Circuit
This Lab has been divided into two parts.
In first part you will be introduced to Verilog and Gate-Level Modeling.
The next part is the hardware implementation of a Boolean function given to you.
Objectives:
Understand HDL and compare it with normal programming languages.
Simulate Basic Gates using Verilog with ModelSim Write stimulus using Verilog Derive algebraic expression for a Boolean function from the given schematics. Hardware Implementation of Logic Circuit
Lab Instructions
This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-lab viva session. The lab report will be uploaded on LMS before scheduled lab date. Each group to upload completed lab report on LMS for grading. The students failing to complete Pre-lab will not be allowed to attend lab session. The students will start lab task and demonstrate design steps separately for step-wise evaluation (teacher/lab engineer will sign each step after ascertaining functional verification). Any report submitted without teacher/lab engineer signatures will not be accepted. Remember that a neat logic diagram with pins numbered and nicely patched circuit will simplify trouble-shooting/fault diagnostic process. After completion of lab, the students are expected to unwire the circuit and deposit back components to lab staff. The students will complete lab task within the prescribed time and submit complete report to lab engineer before leaving the lab. There will be a viva session after demonstration for which students will be graded individually.
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Pre-Lab Tasks (0.5) 1. Read the manual Getting Started with Verilog and answer the following questions: (Handwritten) a) What does HDL stand for? What are its two standard versions?
b) Give the different levels of abstraction in Verilog HDL
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Lab Tasks (9.5) Lab Task 1 (3)
Model and simulate the basic gates i.e. NOT, AND & OR in Verilog (Gate level) using Modelsim. Compare the simulation waveform results with truth table in the space given below.
AND GATE Code (SS & Text)
Output Waveform
OR GATE Code (SS & Text)
Output Waveform
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NOT GATE Code (SS & Text)
Output Waveform
Lab Task 2 (3)
a. Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as well as stimulus below. b. Simulate below circuit on Proteus and perform it on hardware.
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Verilog Code (SS + Text) & Output Waveform
Proteus Simulation (SS for all 4 inputs)
Hardware (SS for all 4 inputs)
Lab Task 3 (1.5)
Label each gate output in the above circuit and derive algebraic expressions for SUM and Carry Out. Fill in the following truth table and determine the function performed by the circuit.
Truth Table:
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A B Sum Carry Out
Derivation for algebraic expressions & determining function:
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Lab Task 4 (2)
After determining the function performed by the circuit given in Lab Task 2, write the Verilog description of the circuit in dataflow. Comment on the two different modeling levels you used to model the same circuit. (Paste snapshots of the codes and stimuluses below)
