LOGIC SYNTHESIS:

DESIGN CYCLE, TYPES OF SYNTHESIZERS, DESIGN

OPTIMIZATION TECHNIQUES, TECHNOLOGY MAPPING

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design (PVL204) 1
DESIGN CYCLE

 The traditional way to design electronic circuits is:

• Specification of the behaviour of the systems
• Simulation of the behaviour
• Transform this behaviour description into dataflow
• Structural description
• Finally, transfer the structural description into the
actual technology.

 At each transformation, there is the possibility of

errors being introduced as a result of the manual
decomposition.

 In practice, getting the design wrong, having too big

or two slow a design, will result in further
modification of the description.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 2
SYNTHESIS

 Synthesis is often defined as the process of translating from a behavioural

to a structural description.

 Since VHDL allows the description of a system from many different

viewpoints, hence, a VHDL synthesis system must translate for any of
these descriptions into a technology netlist.

 In practice, this technology can be a generic or an actual technology.

 Why dataflow and structural approaches need to be used, when

behavioural description gives greatest design leverage?
• For example, if one can write 'c <= a*b;' and get that transformed into a
design, why should one bother to detail a structural description of a Baugh-
Wooley multiplier?

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 3
TYPES OF THE SYNTHESIZERS

 Various kinds of synthesizer exists.

1. Architectural synthesis tools
2. Datapath synthesis tools
3. Test synthesis tools

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 4
TYPES OF THE SYNTHESIZERS (CONT.)

 Architectural synthesis tool (AST)

• AST enable the synthesis of behavioural, dataflow and structural VHDL
into a general model comprising random logic, flip-flop based storage,
arithmetic circuits and control logic.

• They usually synthesize into a system with limited use of bus structures.

• ASTs have limitations in their ability to synthesize largely memory-based

structures and data-path structures, although the precise limitations vary
from tool to tool.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 5
TYPES OF THE SYNTHESIZERS

 Datapath synthesis tool (DST)

• These tools are typically used for synthesizing systems into bus-based
structures in which ALU and register-file-like structures are attached to a
common bus.

• These tools are often considerably more restrictive than the more general-
purpose architectural synthesizers,

• However, for many applications that map well to a bus structure DST can
be much more efficient.

• Often a suite of CAD tools provide both an architectural synthesizer and

data-path synthesis tools.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 6
TYPES OF THE SYNTHESIZERS (CONT.)

 Test synthesis tools

• The testing of complex electronic systems is a challenging problem.

• The test synthesis tool is an increasingly important and used to ease the
testing of circuits.

• Scan based testing results in shorter testing time and provide increased
fault coverage.

• Test synthesis software takes a design and automatically inserts scan flip
flops or converts existing scan flip flops to improve testability.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 7
DESIGN OPTIMIZATION TECHNIQUES

 All logic synthesis software provides the capability to optimize a circuit

for area and speed. As device technology improves it is likely that
optimization for power consumption is also necessary.

 Further, design-based optimization is often provided called resource

sharing.

 Finally, the way in which the VHDL code is written can have an
important impact on optimization
• some constructs synthesize into considerably more efficient structures than
others.

 All optimization techniques except the last are compute intensive,

requiring workstations with substantial memory capacity and processing
speed.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 8
DESIGN OPTIMIZATION TECHNIQUES (CONT.)

 A multiple optimization approach is often useful.

• Individual small circuits are optimized intensively.

 Intensive optimization refers to the number of separate attempts that

the optimizer makes at achieving a reduction.
• Many optimization techniques use Monte Carlo /heuristic algorithms,
increasing the number of trials to increase the chance of a better result.
• This is performed because intensive optimization on a large circuit can be
computationally costly.

 Usually speed optimization is applied after area optimization.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 9
AREA OPTIMIZATION TECHNIQUES

 Area optimization is a well-studied field in digital electronics.

 Optimization based on don't-care states (Initial version of tools).
 Boolean logic is easy to optimize, and most synthesizers perform close
to optimal.
• Knowledge of the underlying technology strongly affects the
optimization (e.g. whether or not four-input gates are available).
• State-machines are equally well optimized.
 The area optimization is more difficult when a particular device
technology is used.
• For example, the XILINX FPGA uses a number of CLBs. Each CLB can
compute up to five-input Boolean expressions. If the expression involves
six inputs then a second CLB is needed. If four inputs are needed, then
there is unlikely to be any area saving.
• Here the relationship between gate count and area is non-linear and thus
substantially harder to calculate.
• Special-purpose optimizers need to be used for these cases.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 10
SPEED OPTIMIZATION TECHNIQUES

 Some speed optimization is achieved through area optimization.

• The area optimization removes redundant circuitry and can shorten the
critical path of the circuit.
 A common approach is to identify the critical path and work to reduce it.
• A simple optimization might be to replace each component on the critical
path with a higher rated but functionally equivalent component from the
library.
• Other optimization techniques might be to strip out strings of inverters from
a design.
 Speed optimization will improve the performance but only to a certain
extent.
 If after speed optimization the circuit still does not meet the design
specification, then the designer must go back and restructure the VHDL.
 Often this approach involves replacing a behavioural specification with a
dataflow or structural one.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 11
RESOURCE SHARING

 There may be substantial opportunity to reduce the complexity of a

circuit by an examination of the function implemented in the code.
 For example, take the VHDL code fragment
IF sel = 1 THEN
c <= a * b;
ELSE
c <= a * d;

 It is clear by inspection that only one of the multiply operations is active

at any one instance. It would be wasteful to implement two large
multipliers when only one is needed (resource sharing).
• By creating a single multiplier with a permanent input 'a' with a selector
logic to select input 'b' if sel = 1 or 'd' otherwise would result in a smaller
circuit.
• The disadvantages of resource sharing include possible slower operating
speed and an increase in the time taken to perform the optimization task.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 12
VHDL CODING STYLE

 The coding style have substantial impact on the way in which the
circuit is transformed into a net-list by the synthesizer.
• For example, the CASE statement has an OTHERS option, which says 'if
none of the previous case conditions are true, then undertake the action
stated in the OTHERS clause'.
• Including such a clause in a CASE statement can result in substantial area
simplification.

 Further optimizations are possible by judicious use of brackets to

indicate an efficient ordering of evaluation.

 Further, consideration of appropriate datatypes, subtype significantly

reduces area, power and delay of the implemented design.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 13
TECHNOLOGY MAPPING

 A design needs to be mapped into a technology net-list and handed over to

the place and route software that provide the final design.
 Delay the choice of technology until the synthesis is complete.
• The synthesizer produces a generic technology output, which comprises a set
of gates and flip flops with particular delays.
• This generic description can then be transformed into a particular technology
by the use of a technology mapper.
• It is possible quickly to change designs into another or even many other
technologies, eliminating dependence on a supplier.
• The price to be paid of is efficiency.

 Knowing the technology chosen at a particular stage can aid the

optimization software to produce better results.
 Furthermore, technology mappers are not always perfect and they may fail
to map from generic to a particular technology.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 14