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DLF Lab - 6

The document outlines a lab focused on verifying the behavior of decoders and encoders, detailing assessment criteria and performance levels for students. It includes objectives, components, truth tables, and tasks related to 2-to-4 line decoders and 8-to-3 line encoders. The lab aims to enhance students' understanding of digital logic fundamentals through practical experimentation and teamwork.

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Muhammad Ali
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0% found this document useful (0 votes)
24 views6 pages

DLF Lab - 6

The document outlines a lab focused on verifying the behavior of decoders and encoders, detailing assessment criteria and performance levels for students. It includes objectives, components, truth tables, and tasks related to 2-to-4 line decoders and 8-to-3 line encoders. The lab aims to enhance students' understanding of digital logic fundamentals through practical experimentation and teamwork.

Uploaded by

Muhammad Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EE1407–Digital Logic Fundamentals

Lab
6
To verify the behavior of Decoders and Encoders.

PLO1–Engineering Knowledge C1 – Recall


PLO4–Investigation P3–Guided Response
PLO’s PLO8–Ethics Bloom’s Taxonomy P2 – Set
PLO9–Individual and Teamwork A3–Assume responsibility
LAB TASK PERFROMANCE
Excellent Average Poor
CLO’s Aspects of Assessments M
(75-100%) (50-75%) (<50%)
Complete understanding of
Recall:Recalltheassociatedconce UnderstandsEncoderandDecoder Studentlacksclearunderstandingof
theconcepts/actively
pts form theory concepts /participatesless in class Encoder
CLO1
participateduring lecture /read &
regardingthebehaviorofEncodera / read conditioningcircuits but andDecoder/Unabletoread&interprets
10% interpretsignalConditioningCircu
ndDecoder. unable to interpretaccurately. ignalconditioningcircuitcompletely.
its.
Observethebehaviorbyfollowing
Experimental Studentefficientlyobserve/ Encoder/Decoder / Circuit
ValidationObservetheworkingofE validate working by workingisvalidateaccuratelyonlywith
ncoderandDecoder schematicdiagrambutwithminor
followingEncoderandDecoder help from theteacher.
errors.
Conducts
DataAnalysisLogicalreasoningan Accuratelydoesdataanalysis
CLO4 analysiswithminorerror; and Abletoconductanalysisoncollecteddat
dexperimentalverificationsofEnco /
70% reasonably a,noattempttocorrelate experimental
der correlateexperimentalresultstoex
correlatesresultstoknowntheoreti results withknown theoreticalresults.
/Decoder pected theoreticalresults.
calresults.
CLO6 LabSafetyProperlyhandlelabinfra Properlyhandlelabequipment&ob Moderatelevellabhandlingand Minorornosafetymeasurementshasbe
10% structure/safetyprecautions eysafetymeasures. safetymeasurements enconsidered.

TeamWorkCompletionofLabtas Worked well with team but Very little, if any, contributions
CLO7 Proactivelyworkwithotherteamm
10%
kswithproperteamwork didnotoffermuchpositivefeedbac togroupandlesscontributionincomplet
emberstocompleteassignedtasks.
andcontribution. k. ionofoveralllabtasks.

Total Marks:10
OBJECTIVE 1:
To Verify the Behavior of 2 to 4 line Decoder.
Components:
74LS139x1

As a decoder, this circuit takes an n-bit binary number and produces an output on one of 2n
output lines. It is therefore commonly defined by the number of addressing input line and the
number of data output lines. Typical the decoder/de-multiplexer ICs might contain 2-to-4
line, 3-to-8 line or a 4-to-16 line circuit. One exception to the binary nature of this circuit is
the 4-to-10 line decoder/de-multiplexer, which is intended to convert a BCD(Binary Coded
Decimal) input to an output in the 0-9 range.

Figure5.1.1: Logic Symbol

Figure5.1.2: Logic Diagram


PIN CONFIGURATION:

Figure5.1.3:Pin Configuration

TRUTH TABLE:

Inputs Outputs
E’ A1 A0 O3’ O2’ O1’ O0’
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table5.1:Two-BitComparatorTruthTable
OBJECTIVE 2:
To Verify the Behavior of 8 to 3 line Encoder.

Components:

74LS148x1

Figure5.2.1: Logic Diagram


PIN CONFIGURATION:

Figure5.2.2: Pin Configuration

TRUTH TABLE:

Inputs Outputs
E1’ 0’ 1’ 2’ 3’ 4’ 5’ 6’ 7’ A2’ A1’ A0’
1 x x x x x X x x
0 1 1 1 1 1 1 1 1
0 x x x x x X x 0
0 x x x x x X 0 1
0 x x x x x 0 1 1
0 x x x x 0 1 1 1
0 x x x 0 1 1 1 1
0 x x 0 1 1 1 1 1
0 x 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
Table5.2: Encoder Truth Table
Lab Tasks:
1. Using 2 to 4 line decoder, show the result of all combinations on Proteus, by
solving logic expression.
2. Show conversion of data from Hexadecimal to binary using relevant encoder on
Proteus.
Home Tasks:
1. For conversion of bits from binary to decimal, what should be used encoder or
decoder and why?
2. Show conversion of bits from binary to decimal for the following inputs.
I. 1000
II. 0011
III. 0110

Conclusion:

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