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Lec-03-Data Representation

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15 views16 pages

Lec-03-Data Representation

Uploaded by

eternalnevzxy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Computer

Programming
CS F111
BITS Pilani
Dubai Campus
BITS Pilani
Dubai Campus

Data Representation (Cont.)


Word Sizes
• Computers have fixed (finite) word sizes
• Word size : 16 bits => ALU can perform operation on 16 bits of data in 1 go
• 32 bits => two 32 bits nos can be added in 1 go.
• Data fetched from Memory are word sized ( CPU ⬄ Memory data path size).

•
Unsigned Integer Bin Rep (min bits) Bin Rep (8 bit) Bin Rep (16 bit)
3 11 00000011 0000000000000011
10 1010 00001010 0000000000001010
15 1111 00001111 0000000000001111
255 11111111 11111111 1000000011111111
256 100000000 Not Possible 0000000100000000
65536 10000000000000000 Not Possible Not Possible

BITS Pilani, Dubai Campus


Signed Integer
Representation

BITS Pilani, Dubai Campus


Signed Integer
Representation

b3 b2 b1 b0 Decimal
0 1 1 1 +7 +(2(4-1)-1)
0 1 1 0 +6

0 0 0 1 +1
0 0 0 0 +0
1 0 0 0 -0
1 0 0 1 -1

1 1 1 0 -6
1 1 1 1 -7 -(2(4-1)-1)
BITS Pilani, Dubai Campus
Signed Integer
Representation
Signed Integer Bin Rep (min bits) Bin Rep (8 bit) Bin Rep (16 bit)
+5 0 101 00000101 0000000000000101
-5 1 101 10000101 1000000000000101
-127 1 1111111 11111111 1000000001111111
+0 00 00000000 0000000000000000
-0 10 10000000 1000000000000000

• Sign Magnitude Representation is easy to understand and encode


• Drawback : Two ways of representing 0 (+0 & -0) (Mathematically incorrect)

• Addition of K + (-K) does not give 0


• -5 + 5 = (10000101)2 + (00000101)2
= (10001010)2
= (-10)10 => Incorrect.

BITS Pilani, Dubai Campus


1’s Complement
Representation

b3 b2 b1 b0 Decimal
0 1 1 1 +7 +(2(4-1)-1)
0 1 1 0 +6

0 0 0 1 +1
0 0 0 0 +0
1 1 1 1 -0
1 1 1 0 -1

1 0 0 1 -6
1 0 0 0 -7 -(2(4-1)-1)

BITS Pilani, Dubai Campus


1’s Complement
Representation
Signed Integer Bin Rep (min bits) Bin Rep (8 bit) Bin Rep (16 bit)
+5 0101 00000101 0000000000000101
-5 1010 11111010 1111111111111010
+127 01111111 01111111 0000000001111111
-127 10000000 10000000 1111111110000000
+0 00 00000000 0000000000000000
-0 11 11111111 1111111111111111

•Drawback : two ways of representing 0 (+0 & -0) (Mathematically incorrect)

•Addition of K + (-K) gives 0


•-5 + 5 = (11111010)2 + (00000101)2 = (11111111)2 = (-0)10

• K + 0 = K only works if we use +0 and not – 0


• 5 + (+0) = (00000101)2 + (00000000)2 = (00000101)2 = 5 OK
• 5 + (-0) = (00000101)2 + (11111111)2 = (00000100)2 = 4 Incorrect

BITS Pilani, Dubai Campus


2’s Complement
Representation

b3 b2 b1 b0 Decimal
0 1 1 1 +7 +(2(4-1)-1)
0 1 1 0 +6

0 0 0 1 +1
0 0 0 0 +0
1 1 1 1 -1
1 1 1 0 -1

1 0 0 1 -7
1 0 0 0 -8 -(2(4-1))
BITS Pilani, Dubai Campus
2’s Complement
Representation
• Positional number representation with a twist
• The most significant bit has a negative weight
-2(n-1) 2(n-2) 2 1 20
• e.g.:-
0110 = -1x(0x23)+ 1x22 + 1x21 + 0x20 = 4+2 = 6
1010 = -1x(1x23)+ 0x22 + 1x21 + 0x20 = -8+2 = -6
• Another method
-6 1010
(1’s Comp)0101
( Add 1) +1
6 0110

BITS Pilani, Dubai Campus


2’s Complement
Representation
Signed Integer Bin Rep (min bits) Bin Rep (8 bit) Bin Rep (16 bit)
+5 0101 00000101 0000000000000101
-5 1011 11111011 1111111111111011
+127 01111111 01111111 0000000001111111
-127 10000001 10000001 1111111110000001
+0 00 00000000 0000000000000000
-0 00 00000000 0000000000000000

• Advantage: Only 1 way of representing 0 (Mathematically correct)


• Addition of K + (-K) gives 0
•-5 + 5 = (11111011)2 + (00000101)2 = (00000000)2 = (0)10

• K + 0 = K works if we use any +0 or -0


•5 + (+0) = (00000101)2 + (00000000)2 = (00000101)2 = 5 OK

BITS Pilani, Dubai Campus


2’s Complement Sign
extension
• A number can be made wider by replicating the most significant bit

• 6 ( 4 bits) = 0110
• 6 (8 bits) = 00000110

• -1 (4 bits) = 1111
•-1 (8 bits) = 11111111
•
• -2 (4 bits) = 1110 (0010 => 1101 + 1 => 1110)
-2 (8 bits) = 11111110 ( i.e. ~00000010 => 11111101 + 1 => 11111110)

BITS Pilani, Dubai Campus


Review (Total bits n = 3)
Unsigned Sign
Decimal binary Magnitude 1's Comp 2's comp
7 111
6 110
5 101
4 100
3 011 011 011 011
2 010 010 010 010
1 001 001 001 001
0 000 000 000 000
-0 100 111
-1 101 110 111
-2 110 101 110
-3 111 100 101
-4 100

Range 0 to 7 -3 to 3 -3 to 3 -4 to 3

BITS Pilani, Dubai Campus


Why is 2’s Complement
popular
• Simplifies logic circuit construction
• Addition & Subtraction can be done using the same circuit.
• No need to check signs and convert
• Operation are done on 2’s comp no. as its done in decimal

BITS Pilani, Dubai Campus


Overflow in 2’s Complement
• Overflow means the result does not fit in the capacity of ‘n’ bits
• ALU is designed to detect overflow.
• Rule. (either of the below conditions)
if both MSB are 0 (i.e +ve) and the MSB of result is 1
if both MSB are 1 (i.e -ve) and the MSB of result is 0

+ 2 = 0010 +5 = 0101 -2 = 1110 -5 = 1011


+ 4 = 0100 +6 = 0110 -4 = 1100 -6 = 1010
+6 = 0110 -5 = 1011 -6 = 1010 +5 = 0101
OK incorrect Ok Incorrect
• (11)10 & (-11)10 cannot be represented in 4 bits.
• One of the PSLV launches crashed because overflow condition
was not checked
•Overflow should be checked and handled separately.

BITS Pilani, Dubai Campus


2’s Complement Eg

BITS Pilani, Dubai Campus

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