- Following the undoped GaN channel, there is a 15-nanometer Al0.2Ga0.
8N
barrier. This barrier layer helps in controlling the flow of electrons in the
device.
**P-GaN Gate Layer with Mg Concentration**
- The text mentions a 70-nanometer p-GaN gate layer with a magnesium
(Mg) concentration of approximately 3 x 10^19 per cubic centimeter. This layer
acts as the gate electrode in the device.
- The p-GaN layer is doped with magnesium to introduce positive charge
carriers (holes) in the material, which is essential for the operation of the
device.
- The concentration of Mg dopants in the p-GaN layer is crucial for determining
the electrical properties of the gate, such as its conductivity and threshold
voltage.
**Heavily Doping P+ Capping Layer**
- The last layer described in the text is a 10-nanometer heavily doping p+
capping layer. This layer is designed to facilitate the formation of an ohmic
contact between the gate electrode (p-GaN) and the metal contacts.
- The heavily doped p+ capping layer ensures low resistance at the gate/p-
GaN interface, allowing for efficient flow of current between the gate electrode
and the semiconductor material.
- By creating a good ohmic contact, the p+ capping layer helps in improving the
overall performance and reliability of the electronic devices fabricated on the
GaN-on-sapphire wafer.
Step 2:
**Fabrication Process Overview**
- The fabrication process of the high-voltage E-Mode p-GaN gate
HEMT on sapphire with gate termination extension (GTE) began with a
partial etch of the p-GaN layer. This partial etch left behind a thin
layer of p-GaN, which would eventually form the GTE region of the
device.
**Formation of GTE Region**
- After the partial etch, the thin p-GaN layer outside of the gate region
and the GTE region was further etched away. This step ensured that only
the desired areas of the p-GaN layer remained for the specific
functionality of the device.
**Passivation Layer Deposition**
- A 50-nm thick layer of silicon dioxide (SiO2) was deposited using
plasma-enhanced chemical vapor deposition (PECVD) for passivation
purposes. This SiO2 layer serves to protect the underlying components
and improve the overall performance and reliability of the device.
**Source/Drain Contact Formation**
- Source and drain contacts were then created by etching through the
SiO2 layer and depositing a stack of titanium (Ti), aluminum (Al),
nickel (Ni), and gold (Au) using electron-beam evaporation. This stack
of metals serves as the contact points for the source and drain regions of
the device.
**Thermal Annealing Process**
- Subsequently, a thermal annealing process in a nitrogen (N2)
atmosphere at 810 degrees Celsius for 30 seconds was carried out. This
annealing step helps to improve the electrical properties and stability of
the source/drain contacts.
**Planar Isolation**
- To achieve planar isolation between different regions of the device,
multienergy fluorine ion implantation was employed. This technique
helps in preventing unwanted electrical interactions between different
components of the device.
**Gate Contact Formation**
- The gate contact was formed by etching through the passivation
layer to create a gate window. A stack of nickel (Ni) and gold (Au)
was then deposited using electron-beam evaporation, followed by
thermal annealing in an oxygen (O2) ambient at 550 degrees Celsius for
4 minutes. This process ensures a reliable and low-resistance connection
for the gate electrode.
**Probing Pad Formation**
- Finally, a stack of titanium (Ti) and gold (Au) was formed to serve as
probing pads for testing and characterization of the device. These
probing pads allow for easy and reliable electrical connections to the
device during testing and evaluation.
**Absence of Metal Field Plate**
- It is important to note that the devices fabricated in this work do not
feature a metal field plate. The absence of a metal field plate may have
implications on the device's electrical characteristics and performance,
which should be considered during the design and optimization of the
device.
"Partial etch"
Partial etch" refers to a process in which only a portion of a material is
removed or dissolved through etching. Etching is a technique
commonly used in manufacturing and fabrication processes to
selectively remove material from a substrate, typically using
chemicals or physical means such as plasma.
In a partial etch process, the goal is to remove material from specific
areas while leaving other areas unaffected. This can be achieved through
various methods such as masking certain regions with a protective
material or controlling the etching parameters to limit the depth or extent
of material removal.
Partial etching finds applications in various industries such as
semiconductor manufacturing, microelectronics, MEMS (Micro-Electro-
Mechanical Systems), and photonics. It is often used to create intricate
patterns, structures, or features on substrates, allowing for the precise
customization and fabrication of devices and components.
Passivation
Passivation is a process used in various fields, including metallurgy,
electronics, and chemistry, to improve the corrosion resistance and
stability of metal surfaces. It involves treating the surface of a metal
to create a protective layer that helps prevent the metal from
reacting with its environment.
In metallurgy, passivation typically involves the formation of a thin
oxide layer on the surface of a metal, such as stainless steel, aluminum,
or titanium. This oxide layer acts as a barrier, preventing further
oxidation or corrosion of the underlying metal when exposed to air or
moisture. Passivation is commonly used in industries where corrosion
resistance is critical, such as aerospace, automotive, and medical device
manufacturing.
In electronics, passivation is often applied to semiconductor devices to
protect the underlying semiconductor material from environmental
factors such as moisture, contaminants, and surface states.
Passivation layers are typically dielectric materials, such as silicon
dioxide (SiO2) or silicon nitride (Si3N4), deposited on the surface of
