Ex.
No: REGISTERS
Date:
AIM:
To design and study the operation of 4-bit shift register to implement the following
operation using D flip flop
i. Serial in Serial out (SISO)
ii. Serial in Parallel out (SIPO)
iii. Parallel in Serial out (PISO)
iv. Parallel in Parallel out (PIPO)
APPARATUSREQUIRED:
Sl. No. Components Required Range Quantity
1 IC 7474
2 IC 7432
4 Function Generator
5 LED
6 Power Supply
7 Bread Board
8 Connecting Wires
9 Resistors
Theory:
Shift Register
The Shift Register is a type of sequential logic circuit that can be used for the storage or
the transfer of data in the form of binary numbers. This sequential device loads the data
present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence
the name “shift register”. Data bits may be fed in or out of a shift register serially, that is one
after the other from either the left or the right direction, or all together at the same time in a
parallel configuration.
The number of individual data latches required to make up a single Shift Register device
is usually determined by the number of bits to be stored with the most common being 8- bits
(one byte) wide constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers
before they are added together or to convert the data from either a serial to parallel or parallel
to serial format. The individual data latches that make up a single shift register are all driven
by a common clock (Clk) signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can
be “SET” or “RESET” as required. Generally, shift registers operate in one of four different
modes with the basic movement of data through a shift register being:
● Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT”
of the register, one bit at a time in either a left or right direction under clock
control.
● Serial-in to Parallel-out(SIPO)-the register is loaded with serial data, one bit
at a time, with the stored data being available at the output in parallel form.
● Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under
clock control.
● Parallel-into Parallel-out (PIPO)-the parallel data is loaded simultaneously
into the register, and transferred together of their respective outputs by the
same clock pulse.
Pin Layout
1. SERIAL INPUT SERIAL OUTPUT (SISO):
Procedure:
1. Connections are made as shown in the SISO circuit diagram.
2. The shift register is loaded with 4 bits of data one by one serially.
3. At the end of the 4th clock pulse, the first data ‘d0’ appears at Q0.
4. Another clock pulse will push the second data bit, ‘d1’ to Q0.
5. Yet another clock pulse gives the third data bit, ‘d2’ at Q0, and so on.
Circuit Diagram :
Truth Table:
2. SERIAL INPUT PARALLEL OUTPUT (SIPO):
Procedure:
1. Connections are made as shown in the SIPO circuit diagram.
2. On applying the first bit of data and then a clock pulse, it can be observed that this data
appears at (Q3).
3. Now, applying the second bit of data and a clock pulse, the bit at Q3 shifts to Q2 and
Q3 will be loaded with the new data.
4. This repeats until all 4 data bits are loaded.
5. At the end of the 4th clock pulse, all 4 bits are available at the parallel output pins Q3
through Q0.
Truth Table:
3. PARALLEL INPUT PARALLEL OUTPUT (PIPO):
Procedure:
1. Connections are made as shown in the PIPO mode circuit diagram.
2. Apply the 4 data bits as input to D3, D2, D1, D0.
3. Note that the 4 bit data at parallel inputs appears at the parallel output pins Q3, Q2, Q1,
Q0 with one clock pulse respectively.
4. PARALLEL INPUT SERIAL OUTPUT (PISO):
Procedure:
1. Connections are made as shown in the PISO circuit diagram.
2. Apply the 4-bit data at the parallel I/P pins D3, D2, D1, D0 and apply single clock pulse
to load the data to all 4 registers.
3. Now make all data bits as 0 and apply clock pulse one by one to get the data bit by bit at
the output line.
4. The data applied at the parallel input pins will shift and comes out serially at the output
line Q0.
Circuit Diagram :
Truth Table:
Clock Parallel I/P Serial O/P
A2 A3 A0 Q2 Q1 Q0
1 1 0 1 1 0 1
2 0 0 0 X X 0
3 0 0 0 X X 1
Viva Questions:
1. N bit shift register can store bit of information.
2. Assume a 6bit shift register is initially having a value 10000, what will happen after each
right shift?
3. Assume a 6 bit shift register is initially having a value 00001,what will happen after each
left shift?
4. What is flip flop? How is different from latch?
5. How many bits are there in your 1GByte pen drive?
6. How many address lines are needed to access 1000bytememory?
Maximum Marks
Marks Obtained
Circuit Design
Viva
Observation
Record
Result:
