CHAPTER

COMPUTER SYSTEM COMPONENTS

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Computer Components : Top Level View

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Microprocessor 8085: External View

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 Microprocessor 8085 (contd.)

• The pins of a 8085 microprocessor can be classified into several groups:

1. Address Bus: A15-A8, it carries the most significant 8-bits of memory/IO address.
2. Data Bus : AD7-AD0, it carries the least significant 8-bit address and data bus.
3. Control and status signals: RD,WR & ALE are three control signals.
Three status signals are IO/M, S0 & S1.
1. Power Supply: VCC indicates +5 V & VSS indicates ground signal.
2. Clock Signals: X1, X2, & CLK OUT are used as signals for clock.

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 Instruction Cycle
Two steps in a Instruction Cycle:
• Fetch
• Execute

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 Fetch Cycle
• Program Counter (PC) holds address of next instruction to fetch

• Processor fetches instruction from memory location pointed by PC

• Increment of PC

• Instruction loaded into Instruction Register (IR)

• Processor interprets instruction and performs required actions

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 Execution Cycle
• Processor - memory
▪ Data transfer between CPU and main memory

• Processor I/O
▪ Data transfer between CPU and I/O module

• Data processing
▪ Some arithmetic or logical operation on data

• Control
▪ Alteration of sequence of operations (e.g. jump)

• Combination of above
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Interrupts in an execution

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 Interrupts in an execution
• It is a mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing

• Program
▪ e.g. overflow, division by zero

• Timer
▪ Generated by internal processor timer
▪ Used in pre-emptive multi-tasking

• I/O
▪ from I/O controller

• Hardware failure
▪ e.g. memory parity error
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Instruction Cycle with Interrupts

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 Interrupt Cycle
• Added to instruction cycle

• Processor checks for interrupt

▪ Indicated by an interrupt signal

• If no interrupt, fetch next instruction

• If interrupt pending:
▪ Suspend execution of current program
▪ Save context
▪ Set PC to start address of interrupt handler routine
▪ Process interrupt
▪ Restore context and continue interrupted program
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 Interrupts in 8085
• There are 5 interrupt signals, i.e.TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

• INTA − Interrupt acknowledgment signal.

• RESET IN − Used to reset the microprocessor by setting the program counter to zero.

• RESET OUT − Ised to reset all the connected devices when the microprocessor is reset.

• READY − Indicates that the device is ready to send or receive data. If READY is low, then
the CPU has to wait for READY to go high.

• HOLD − This signal indicates that another master is requesting the use of the address and
data buses.

• HLDA (HOLD Acknowledge) - Indicates that the CPU has received the HOLD request and
it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD signal is
removed.
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Microprocessor 8085: External View

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System Bus Architecture

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 System Bus Architecture (contd.)
Data Bus
• Carries data

Address bus
• Identify the source or destination of data

Control bus
• Control and timing information

▪ Memory read/write signal

▪ Interrupt request
▪ Clock signals

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 Direct Memory Access (DMA)
• For high-bandwidth devices (like disks) interrupt-driven I/O would consume a lot of
processor cycles

• DMA – the I/O controller has the ability to transfer data directly to/from the memory
without involving the processor

1. The processor initiates the DMA transfer by supplying the I/O device address, the
operation to be performed, the memory address destination/source, the number
of bytes to transfer.
2. The I/O DMA controller manages the entire transfer (possibly thousand of bytes
in length), arbitrating for the bus
3. When the DMA transfer is complete, the I/O controller interrupts the processor
to let it know that the transfer is complete.

• There may be multiple DMA devices in one system

▪ Processor and I/O controllers contend for bus cycles and for memory 17
Language Comparison

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Language Comparison

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 Machine Language Instructions

• A machine language instruction

consists of:
▫ Operation code, telling which
operation to perform
▫ Address field, telling the
memory addresses of the values
on which the operation works.

▫ MIPS instruction format is given

below in three different styles, such
as R (Arithmetic), I (Branch, transfer
& immediate), and J (Jump)

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 Machine Language Instructions

• Example:
ADD X,Y :-Add content of memory locations X and Y, and store back in
memory location Y

Assume: opcode for ADD is 9, and addresses X=99,Y=100

Opcode (8 bits) Address 1 (16 bits) Address 2 (16 bits)

00001001 0000000001100011 0000000001100100

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 Typical Machine Instructions

• Notation:
▫ We use X,Y, Z to denote RAM cells
▫ Assume only one register R (for simplicity)
▫ Use English-like descriptions (should be binary)

• Data Transfer Instructions

▫ LOAD X Load content of memory location X to R
▫ STORE X Load content of R to memory location X
▫ MOVE X,Y Copy content of memory location X to location Y
(not absolutely necessary)

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 Typical Machine Instructions (contd.)

• Arithmetic operations
▫ ADD X,Y, Z CON(Z) = CON(X) + CON(Y)
▫ ADD X,Y CON(Y) = CON(X) + CON(Y)
▫ ADD X R = CON(X) + R
similar instructions for other operators, e.g. SUBTR,OR, ...

• Comparison operations
▫ COMPARE X,Y
Compare the content of memory cell X to the content of memory cell Y
and set the condition codes (CCR) accordingly.

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 Typical Machine Instructions (contd.)

• Branch
• JUMP X Load next instruction from memory loc. X
• JUMPGT X Load next instruction from memory loc. X only if GT flag in CCR is set,
otherwise load statement from next sequence location as usual.

( JUMPEQ, JUMPLT, JUMPGE, JUMPLE, JUMPNEQ )

• Control
• HALT Stop program execution.
1. **JUMP X:** This instruction unconditionally loads the next instruction from memory location `X`. It redirects the program flow to a different location specified by the memory address `X`.

2. **JUMPGT X:** This instruction checks if the "Greater Than" (GT) flag in the Condition Code Register (CCR) is set. If the GT flag is set (indicating that a previous comparison was true), it loads the next instruction from memory location `X`. Otherwise, it continues to load the next statement from the usual sequence location.

3. **JUMPEQ X:** Similar to JUMPGT, this instruction checks if the "Equal" (EQ) flag in the CCR is set. If the EQ flag is set (indicating that a previous comparison was true), it loads the next instruction from memory location `X`. Otherwise, it proceeds to the next statement in the usual sequence.

4. **JUMPLT X:** Checks if the "Less Than" (LT) flag in the CCR is set. If the LT flag is set (indicating a previous comparison was true), it loads the next instruction from memory location `X`. Otherwise, it continues with the next sequential statement.

5. **JUMPGE X:** This instruction checks if the "Greater Than or Equal" (GE) flag in the CCR is set. If the GE flag is set (indicating that a previous comparison was true), it loads the next instruction from memory location `X`. If not, it proceeds with the next sequential statement.

6. **JUMPLE X:** Checks if the "Less Than or Equal" (LE) flag in the CCR is set. If the LE flag is set (indicating a previous comparison was true), it loads the next instruction from memory location `X`. Otherwise, it continues to the next statement in the usual sequence.

7. **JUMPNEQ X:** This instruction checks if the "Not Equal" (NE) flag in the CCR is set. If the NE flag is set (indicating a previous comparison was true), it loads the next instruction from memory location `X`. If not, it proceeds with the next sequential statement.

These instructions allow the program to make decisions based on the results of previous comparisons (e.g., during conditional branches) and change the program's flow accordingly by specifying different memory locations for the next instruction.

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 Example
• Pseudo-code: Set A to B + C
• Assuming variable:
• A stored in memory cell 100, B stored in memory cell 150, C stored in
memory cell 151

• Machine language (really in binary)

LOAD 150
ADD 151
STORE 100
or
(ADD 150, 151, 100)

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 Exercise
• Pseudo-code:
Set X to Y * Z
Set P to Q / R
Then
Set K to X+ P

• Consider the following memory location of each variable:

X 656
Y 658
Z 690
P 1111
Q 100
R 101
K 99 26
 Exercise (Solution)
// Set X to Y*Z
LOAD 658
MULT 690 OR MULT 658, 690, 656
STORE 656

// Set P to Q / R
LOAD 100
DIV 101 OR DIV 100, 101, 1111
STORE 1111

// Set K to X +P
LOAD 656
DIV 1111 OR ADD 656, 1111, 99
STORE 99 27
 Program Execution
• Fetch phase
▪ PC MAR (put address of PC into MAR)
▪ Fetch signal (signal memory to fetch value into MDR)
▪ MDR IR (move value to Instruction Register)
▪ PC + 1 PC (Increase address in program counter)

• Decode Phase
▪ IR Instruction decoder (decode instruction in IR)
▪ Instruction decoder will then generate the signals to activate the circuitry to
carry out the instruction

• Execute Phase
▪ Differs from one instruction to the next.
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 Program Execution (contd.)

Example:

• LOAD X (load value in addr. X into register)

▪ IR_address MAR
▪ Fetch signal
▪ MDR R

• ADD X
▪ left as an exercise

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INSTRUCTION PIPELINING

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 Instruction Execute Cycle

Instruction
Obtain instruction from program storage
Fetch
Instruction
Determine required actions and instruction size
Infinite Cycle

Decode
Operand
Locate and obtain operand data
Fetch

Execute Compute result value and status

Writeback
Deposit results in storage for later use
Result

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 Instruction Execute Cycle (contd.)

PC
• Instruction Fetch
program
I1 I2 I3 I4 ...

• Instruction Decode memory

op1
read
fetch

1
• Operand Fetch op2 3 registers
3
registers

• Execute I1
instruction
register

• Result WriteBack

decode
write

write
2
flags ALU

5 execute
(output)
4

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What is Pipelining?

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 What is Pipelining?
▪ A technique used in advanced microprocessors where the microprocessor begins
executing a second instruction before the first has been completed.

A Pipeline is a series of stages, where some work is done at each stage. The work is not
finished until it has passed through all stages.

▪ With pipelining, the computer architecture allows the next instructions to be fetched
while the processor is performing arithmetic operations, holding them in a buffer
close to the processor until each instruction operation can performed.
• The pipeline is divided into segments and each segment can execute it operation
concurrently with the other segments.

• Once a segment completes an operation, it passes the result to the next segment in
the pipeline and fetches the next operations from the preceding segment.

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 What is Pipelining? (contd.)

Instruction 1 Instruction 2 IF ID EX M W
1
IF ID EX M W
X X 1
IF ID EX M W
Instruction 4 Instruction 3 1
IF ID EX M W
X X
Four sample instructions, executed linearly Four Pipelined Instructions

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 Pipelining Stages
Instruction Fetch
• The instruction Fetch (IF) stage is responsible for obtaining the requested
instruction from memory.
• The instruction and the program counter (which is incremented to the next
instruction) are stored in the IF/ID pipeline register as temporary storage so that
may be used in the next stage at the start of the next clock cycle.
- Read instruction from memory

Instruction Decode
• The Instruction Decode (ID) stage is responsible for decoding the instruction and
sending out the various control lines to the other parts of the processor.
• The instruction is sent to the control unit where it is decoded and the registers
are fetched from the register file.
- Read source registers and generate control signals
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 Pipelining Stages (contd.)
Execution
• The Execution (EX) stage is where any calculations are performed. The main component in
this stage is the ALU.
• The ALU is made up of arithmetic, logic and capabilities.
- Compute an R-type result or branch outcome

Memory and IO
• The Memory and IO (MEM) stage is responsible for storing and loading values to and from
memory. It also responsible for input or output from the processor.
• If the current instruction is not of Memory or IO type than the result from the ALU is
passed through to the write back stage.
- Read / Write data memory

Write Back
• The Write Back (WB) stage is responsible for writing the result of a calculation, memory
access or input into the register file.
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- Store a result in the destination register
 Operation Timings
Estimated timings for each of the stages:

Instruction Fetch 2ns

Instruction Decode 1ns

Execution 2ns

Memory and IO 2ns

Write Back 1ns

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 Characteristics of Pipelining
Hardware or software implementation :
Pipelining can be implemented in either software or hardware.

Large or Small Scale :

Stations in a pipeline can range from simplistic to powerful, and a pipeline can range in
length from short to long.

Synchronous or asynchronous flow :

A synchronous pipeline operates like an assembly line: at a given time, each station is
processing some amount of information. A asynchronous pipeline, allow a station to
forward information at any time.

Buffered or un buffered flow :

One stage of pipeline sends data directly to another one or a buffer is place between
each pairs of stages.
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 Characteristics of Pipelining (contd.)

Finite Chunks or Continuous Bit Streams :

The digital information that passes though a pipeline can consist of a sequence or
small data items or an arbitrarily long bit stream.

Automatic Data Feed Or Manual Data Feed :

Some implementations of pipelines use a separate mechanism to move
information, and other implementations require each stage to participate in
moving information.

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 Pros & Cons of Pipelining
Pros:

▪ More efficient use of processor

▪ Quicker time of execution of large number of instructions

Cons:

▪ Pipelining involves adding hardware to the chip

▪ Inability to continuously run the pipeline at full speed because of pipeline

hazards which disrupt the smooth execution of the pipeline.
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 Pipeline Hazards

▪ Data Hazards –
An instruction uses the result of the previous instruction. A hazard occurs exactly
when an instruction tries to read a register in its ID stage that an earlier
instruction intends to write in its WB stage.

▪ Control Hazards –
The location of an instruction depends on previous instruction

▪ Structural Hazards –
Two instructions need to access the same resource

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 Pipelined Execution
▪ Instruction execution can be divided into stages
▪ Pipelining makes it possible to start an instruction before completing the execution
of previous one
Stages
For k stages and n instructions, the number
S1 S2 S3 S4 S5 S6 of required cycles is: k + n – 1
1 I-1
2 I-1
3 I-1 Stages
4 I-1
S1 S2 S3 S4 S5 S6
5 I-1
Cycles

1 I-1
6 I-1
7 I-2
2 I-2 I-1

Cycles
8 I-2 3 I-2 I-1
9 I-2 4 I-2 I-1
10 I-2 5 I-2 I-1
11 I-2 6 I-2 I-1
12 I-2 7 I-2
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 Instruction Set Design

▪ Two different approaches are there in instruction set design:

• Reduced Instruction Set Computers (RISC)

• Instruction set as small and simple as possible.
• Minimizes amount of circuitry : faster computers

• Complex Instruction Set Computers (CISC)

• More instructions, many very complex
• Each instruction can do more work, but require more circuitry.

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 RISC Architecture
▪ RISC is a CPU design that recognizes only a limited number of instructions.

Features :
• Instructions are fixed in length & uniform format.
• Executes a series of simple instruction instead of a complex instruction.
• Instructions are executed within one clock cycle.
• Main concern is to maximizing the efficiency of pipelining.
• It is an attempt to produce more CPU power by simplifying the instruction set
of the CPU.

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 Advantages of RISC Architecture

• Best support is given by optimizing most used and most time consuming
architecture aspects.

• Less design complexity and reducing design cost.

• Reducing the time between designing & marketing.

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RISC & CISC Architecture : Comparison

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 Superscalar Architecture

▪ A superscalar processor has multiple execution pipelines

▪ The Pentium processor has two execution pipelines
▫ Called U and V pipes
▪ Here, stage S4 has 2 pipelines Stages

▫ Each pipeline still S4

requires 2 cycles 1
S1
I-1
S2 S3 u v S5 S6

▫ Second pipeline
2 I-2 I-1
3 I-3 I-2 I-1
eliminates wasted cycles

Cycles
4 I-4 I-3 I-2 I-1
5 I-4 I-3 I-1 I-2
▫ For k stages and n 6 I-4 I-3 I-2 I-1

instructions, number of
7 I-3 I-4 I-2 I-1
8 I-4 I-3 I-2
cycles = k + n 9 I-4 I-3
10 I-4

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THE END

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